EFM32 Happy Gecko Software Documentation
efm32hg-doc-5.1.2
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CMSIS Cortex-M Peripheral Access Layer Header File for EFM32HG322F64.
Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file efm32hg322f64.h.
#include "arm_math.h"
#include "core_cm0plus.h"
#include "system_efm32hg.h"
#include "efm32hg_aes.h"
#include "efm32hg_dma_ch.h"
#include "efm32hg_dma.h"
#include "efm32hg_usb_diep.h"
#include "efm32hg_usb_doep.h"
#include "efm32hg_usb.h"
#include "efm32hg_msc.h"
#include "efm32hg_emu.h"
#include "efm32hg_rmu.h"
#include "efm32hg_cmu.h"
#include "efm32hg_timer_cc.h"
#include "efm32hg_timer.h"
#include "efm32hg_acmp.h"
#include "efm32hg_usart.h"
#include "efm32hg_prs_ch.h"
#include "efm32hg_prs.h"
#include "efm32hg_idac.h"
#include "efm32hg_gpio_p.h"
#include "efm32hg_gpio.h"
#include "efm32hg_vcmp.h"
#include "efm32hg_adc.h"
#include "efm32hg_leuart.h"
#include "efm32hg_pcnt.h"
#include "efm32hg_i2c.h"
#include "efm32hg_rtc.h"
#include "efm32hg_wdog.h"
#include "efm32hg_mtb.h"
#include "efm32hg_dma_descriptor.h"
#include "efm32hg_devinfo.h"
#include "efm32hg_romtable.h"
#include "efm32hg_calibrate.h"
#include "efm32hg_prs_signals.h"
#include "efm32hg_dmareq.h"
#include "efm32hg_dmactrl.h"
#include "efm32hg_af_ports.h"
#include "efm32hg_af_pins.h"
Go to the source code of this file.
Macros | |
#define | __CM0PLUS_REV 0x001 |
#define | __MPU_PRESENT 0 |
#define | __NVIC_PRIO_BITS 2 |
#define | __Vendor_SysTickConfig 0 |
#define | __VTOR_PRESENT 1 |
#define | _EFM32_HAPPY_FAMILY 1 |
#define | _EFM_DEVICE |
#define | _SILICON_LABS_32B_PLATFORM 1 |
#define | _SILICON_LABS_32B_PLATFORM_1 |
#define | _SILICON_LABS_32B_SERIES 0 |
#define | _SILICON_LABS_32B_SERIES_0 |
#define | _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ |
#define | _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ |
#define | ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) |
#define | ACMP0_BASE (0x40001000UL) |
#define | ACMP_COUNT 1 |
#define | ACMP_PRESENT |
#define | ADC0 ((ADC_TypeDef *) ADC0_BASE) |
#define | ADC0_BASE (0x40002000UL) |
#define | ADC_COUNT 1 |
#define | ADC_PRESENT |
#define | AES ((AES_TypeDef *) AES_BASE) |
#define | AES_BASE (0x400E0000UL) |
#define | AES_COUNT 1 |
#define | AES_MEM_BASE ((uint32_t) 0x400E0000UL) |
#define | AES_MEM_BITS ((uint32_t) 0x10UL) |
#define | AES_MEM_END ((uint32_t) 0x400E03FFUL) |
#define | AES_MEM_SIZE ((uint32_t) 0x400UL) |
#define | AES_PRESENT |
#define | AFACHAN_MAX 27 |
#define | AFCHAN_MAX 42 |
#define | AFCHANLOC_MAX 7 |
#define | ANALOG_COUNT 1 |
#define | ANALOG_PRESENT |
#define | ARM_MATH_CM0PLUS |
#define | BOOTLOADER_COUNT 1 |
#define | BOOTLOADER_PRESENT |
#define | CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) |
#define | CALIBRATE_BASE (0x0FE08000UL) |
#define | CMU ((CMU_TypeDef *) CMU_BASE) |
#define | CMU_BASE (0x400C8000UL) |
#define | CMU_COUNT 1 |
#define | CMU_PRESENT |
#define | CMU_UNLOCK_CODE 0x580E |
#define | DBG_COUNT 1 |
#define | DBG_PRESENT |
#define | DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL) |
#define | DEVICE_MEM_BITS ((uint32_t) 0x12UL) |
#define | DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL) |
#define | DEVICE_MEM_SIZE ((uint32_t) 0x1000UL) |
#define | DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) |
#define | DEVINFO_BASE (0x0FE081B0UL) |
#define | DMA ((DMA_TypeDef *) DMA_BASE) |
#define | DMA_BASE (0x400C2000UL) |
#define | DMA_CHAN_COUNT 6 |
#define | DMA_COUNT 1 |
#define | DMA_PRESENT |
#define | EMU ((EMU_TypeDef *) EMU_BASE) |
#define | EMU_BASE (0x400C6000UL) |
#define | EMU_COUNT 1 |
#define | EMU_PRESENT |
#define | EMU_UNLOCK_CODE 0xADE8 |
#define | EXT_IRQ_COUNT 21 |
#define | FLASH_BASE (0x00000000UL) |
#define | FLASH_MEM_BASE ((uint32_t) 0x0UL) |
#define | FLASH_MEM_BITS ((uint32_t) 0x28UL) |
#define | FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) |
#define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | FLASH_PAGE_SIZE 1024 |
#define | FLASH_SIZE (0x00010000UL) |
#define | GPIO ((GPIO_TypeDef *) GPIO_BASE) |
#define | GPIO_BASE (0x40006000UL) |
#define | GPIO_COUNT 1 |
#define | GPIO_PRESENT |
#define | GPIO_UNLOCK_CODE 0xA534 |
#define | HFXTAL_COUNT 1 |
#define | HFXTAL_PRESENT |
#define | I2C0 ((I2C_TypeDef *) I2C0_BASE) |
#define | I2C0_BASE (0x4000A000UL) |
#define | I2C_COUNT 1 |
#define | I2C_PRESENT |
#define | IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) |
#define | IDAC0_BASE (0x40004000UL) |
#define | IDAC_COUNT 1 |
#define | IDAC_PRESENT |
#define | LE_COUNT 1 |
#define | LE_PRESENT |
#define | LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) |
#define | LEUART0_BASE (0x40084000UL) |
#define | LEUART_COUNT 1 |
#define | LEUART_PRESENT |
#define | LFXTAL_COUNT 1 |
#define | LFXTAL_PRESENT |
#define | LOCKBITS_BASE (0x0FE04000UL) |
#define | MSC ((MSC_TypeDef *) MSC_BASE) |
#define | MSC_BASE (0x400C0000UL) |
#define | MSC_COUNT 1 |
#define | MSC_PRESENT |
#define | MSC_UNLOCK_CODE 0x1B71 |
#define | MTB ((MTB_TypeDef *) MTB_BASE) |
#define | MTB_BASE (0xF0040000UL) |
#define | MTB_COUNT 1 |
#define | MTB_PRESENT |
#define | PART_NUMBER "EFM32HG322F64" |
#define | PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) |
#define | PCNT0_BASE (0x40086000UL) |
#define | PCNT_COUNT 1 |
#define | PCNT_PRESENT |
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
#define | PER_MEM_BITS ((uint32_t) 0x20UL) |
#define | PER_MEM_END ((uint32_t) 0x400DFFFFUL) |
#define | PER_MEM_SIZE ((uint32_t) 0xE0000UL) |
#define | PRS ((PRS_TypeDef *) PRS_BASE) |
#define | PRS_BASE (0x400CC000UL) |
#define | PRS_CHAN_COUNT 6 |
#define | PRS_COUNT 1 |
#define | PRS_PRESENT |
#define | RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
#define | RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) |
#define | RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) |
#define | RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM_MEM_BITS ((uint32_t) 0x18UL) |
#define | RAM_MEM_END ((uint32_t) 0x2003FFFFUL) |
#define | RAM_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | RMU ((RMU_TypeDef *) RMU_BASE) |
#define | RMU_BASE (0x400CA000UL) |
#define | RMU_COUNT 1 |
#define | RMU_PRESENT |
#define | ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) |
#define | ROMTABLE_BASE (0xF00FFFD0UL) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | RTC_BASE (0x40080000UL) |
#define | RTC_COUNT 1 |
#define | RTC_PRESENT |
#define | SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register. More... | |
#define | SRAM_BASE (0x20000000UL) |
#define | SRAM_SIZE (0x00002000UL) |
#define | TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) |
#define | TIMER0_BASE (0x40010000UL) |
#define | TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) |
#define | TIMER1_BASE (0x40010400UL) |
#define | TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) |
#define | TIMER2_BASE (0x40010800UL) |
#define | TIMER_COUNT 3 |
#define | TIMER_PRESENT |
#define | TIMER_UNLOCK_CODE 0xCE80 |
#define | USART0 ((USART_TypeDef *) USART0_BASE) |
#define | USART0_BASE (0x4000C000UL) |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | USART1_BASE (0x4000C400UL) |
#define | USART_COUNT 2 |
#define | USART_PRESENT |
#define | USB ((USB_TypeDef *) USB_BASE) |
#define | USB_BASE (0x400C4000UL) |
#define | USB_COUNT 1 |
#define | USB_PRESENT |
#define | USBC_COUNT 1 |
#define | USBC_MEM_BASE ((uint32_t) 0x40100000UL) |
#define | USBC_MEM_BITS ((uint32_t) 0x18UL) |
#define | USBC_MEM_END ((uint32_t) 0x4013FFFFUL) |
#define | USBC_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | USBC_PRESENT |
#define | USBLE_COUNT 1 |
#define | USBLE_PRESENT |
#define | USERDATA_BASE (0x0FE00000UL) |
#define | USHFRCO_COUNT 1 |
#define | USHFRCO_PRESENT |
#define | VCMP ((VCMP_TypeDef *) VCMP_BASE) |
#define | VCMP_BASE (0x40000000UL) |
#define | VCMP_COUNT 1 |
#define | VCMP_PRESENT |
#define | WDOG ((WDOG_TypeDef *) WDOG_BASE) |
#define | WDOG_BASE (0x40088000UL) |
#define | WDOG_COUNT 1 |
#define | WDOG_PRESENT |
Typedefs | |
typedef enum IRQn | IRQn_Type |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, ACMP0_IRQn = 3, ADC0_IRQn = 4, I2C0_IRQn = 5, GPIO_ODD_IRQn = 6, TIMER1_IRQn = 7, USART1_RX_IRQn = 8, USART1_TX_IRQn = 9, LEUART0_IRQn = 10, PCNT0_IRQn = 11, RTC_IRQn = 12, CMU_IRQn = 13, VCMP_IRQn = 14, MSC_IRQn = 15, AES_IRQn = 16, USART0_RX_IRQn = 17, USART0_TX_IRQn = 18, USB_IRQn = 19, TIMER2_IRQn = 20 } |