EFM32 Happy Gecko Software Documentation
efm32hg-doc-5.1.2
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Modules | |
EFM32HG322F64 Alternate Function | |
EFM32HG322F64 Bit Fields | |
EFM32HG322F64 Core | |
Processor and Core Peripheral Section. | |
EFM32HG322F64 Part | |
EFM32HG322F64 Peripheral Declarations | |
EFM32HG322F64 Peripheral Memory Map | |
EFM32HG322F64 Peripheral TypeDefs | |
Device Specific Peripheral Register Structures. | |
Macros | |
#define | ARM_MATH_CM0PLUS |
#define | SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register. More... | |
Typedefs | |
typedef enum IRQn | IRQn_Type |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, ACMP0_IRQn = 3, ADC0_IRQn = 4, I2C0_IRQn = 5, GPIO_ODD_IRQn = 6, TIMER1_IRQn = 7, USART1_RX_IRQn = 8, USART1_TX_IRQn = 9, LEUART0_IRQn = 10, PCNT0_IRQn = 11, RTC_IRQn = 12, CMU_IRQn = 13, VCMP_IRQn = 14, MSC_IRQn = 15, AES_IRQn = 16, USART0_RX_IRQn = 17, USART0_TX_IRQn = 18, USB_IRQn = 19, TIMER2_IRQn = 20 } |
#define SET_BIT_FIELD | ( | REG, | |
MASK, | |||
VALUE, | |||
OFFSET | |||
) | REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register.
REG | The register to update |
MASK | The mask for the bit field to update |
VALUE | The value to write to the bit field |
OFFSET | The number of bits that the field is offset within the register. 0 (zero) means LSB. |
Definition at line 395 of file efm32hg322f64.h.
enum IRQn |
Interrupt Number Definition
Definition at line 52 of file efm32hg322f64.h.