EFM32 Happy Gecko Software Documentation  efm32hg-doc-5.1.2
efm32hg322f64.h
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1 /**************************************************************************/
34 #ifndef EFM32HG322F64_H
35 #define EFM32HG322F64_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**************************************************************************/
46 /**************************************************************************/
52 typedef enum IRQn
53 {
54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
57  SVCall_IRQn = -5,
58  PendSV_IRQn = -2,
59  SysTick_IRQn = -1,
61 /****** EFM32HG Peripheral Interrupt Numbers ********************************************/
62  DMA_IRQn = 0,
65  ACMP0_IRQn = 3,
66  ADC0_IRQn = 4,
67  I2C0_IRQn = 5,
72  LEUART0_IRQn = 10,
73  PCNT0_IRQn = 11,
74  RTC_IRQn = 12,
75  CMU_IRQn = 13,
76  VCMP_IRQn = 14,
77  MSC_IRQn = 15,
78  AES_IRQn = 16,
81  USB_IRQn = 19,
82  TIMER2_IRQn = 20,
83 } IRQn_Type;
84 
85 /**************************************************************************/
90 #define __MPU_PRESENT 0
91 #define __VTOR_PRESENT 1
92 #define __NVIC_PRIO_BITS 2
93 #define __Vendor_SysTickConfig 0
97 /**************************************************************************/
103 #define _EFM32_HAPPY_FAMILY 1
104 #define _EFM_DEVICE
105 #define _SILICON_LABS_32B_SERIES_0
106 #define _SILICON_LABS_32B_SERIES 0
107 #define _SILICON_LABS_GECKO_INTERNAL_SDID 77
108 #define _SILICON_LABS_GECKO_INTERNAL_SDID_77
109 #define _SILICON_LABS_32B_PLATFORM_1
110 #define _SILICON_LABS_32B_PLATFORM 1
112 /* If part number is not defined as compiler option, define it */
113 #if !defined(EFM32HG322F64)
114 #define EFM32HG322F64 1
115 #endif
116 
118 #define PART_NUMBER "EFM32HG322F64"
121 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
122 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
123 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
124 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
125 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
126 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
127 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
128 #define AES_MEM_BITS ((uint32_t) 0x10UL)
129 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
130 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
131 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
132 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
133 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
134 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
135 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
136 #define PER_MEM_BITS ((uint32_t) 0x20UL)
137 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
138 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
139 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
140 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
141 #define DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL)
142 #define DEVICE_MEM_SIZE ((uint32_t) 0x1000UL)
143 #define DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL)
144 #define DEVICE_MEM_BITS ((uint32_t) 0x12UL)
145 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
146 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
147 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
148 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
151 #define FLASH_BASE (0x00000000UL)
152 #define FLASH_SIZE (0x00010000UL)
153 #define FLASH_PAGE_SIZE 1024
154 #define SRAM_BASE (0x20000000UL)
155 #define SRAM_SIZE (0x00002000UL)
156 #define __CM0PLUS_REV 0x001
157 #define PRS_CHAN_COUNT 6
158 #define DMA_CHAN_COUNT 6
159 #define EXT_IRQ_COUNT 21
162 #define AFCHAN_MAX 42
163 #define AFCHANLOC_MAX 7
164 
165 #define AFACHAN_MAX 27
166 
167 /* Part number capabilities */
168 
169 #define TIMER_PRESENT
170 #define TIMER_COUNT 3
171 #define ACMP_PRESENT
172 #define ACMP_COUNT 1
173 #define USART_PRESENT
174 #define USART_COUNT 2
175 #define IDAC_PRESENT
176 #define IDAC_COUNT 1
177 #define ADC_PRESENT
178 #define ADC_COUNT 1
179 #define LEUART_PRESENT
180 #define LEUART_COUNT 1
181 #define PCNT_PRESENT
182 #define PCNT_COUNT 1
183 #define I2C_PRESENT
184 #define I2C_COUNT 1
185 #define AES_PRESENT
186 #define AES_COUNT 1
187 #define DMA_PRESENT
188 #define DMA_COUNT 1
189 #define LE_PRESENT
190 #define LE_COUNT 1
191 #define USBC_PRESENT
192 #define USBC_COUNT 1
193 #define USBLE_PRESENT
194 #define USBLE_COUNT 1
195 #define USB_PRESENT
196 #define USB_COUNT 1
197 #define MSC_PRESENT
198 #define MSC_COUNT 1
199 #define EMU_PRESENT
200 #define EMU_COUNT 1
201 #define RMU_PRESENT
202 #define RMU_COUNT 1
203 #define CMU_PRESENT
204 #define CMU_COUNT 1
205 #define PRS_PRESENT
206 #define PRS_COUNT 1
207 #define GPIO_PRESENT
208 #define GPIO_COUNT 1
209 #define VCMP_PRESENT
210 #define VCMP_COUNT 1
211 #define RTC_PRESENT
212 #define RTC_COUNT 1
213 #define HFXTAL_PRESENT
214 #define HFXTAL_COUNT 1
215 #define LFXTAL_PRESENT
216 #define LFXTAL_COUNT 1
217 #define USHFRCO_PRESENT
218 #define USHFRCO_COUNT 1
219 #define WDOG_PRESENT
220 #define WDOG_COUNT 1
221 #define DBG_PRESENT
222 #define DBG_COUNT 1
223 #define MTB_PRESENT
224 #define MTB_COUNT 1
225 #define BOOTLOADER_PRESENT
226 #define BOOTLOADER_COUNT 1
227 #define ANALOG_PRESENT
228 #define ANALOG_COUNT 1
229 
232 #define ARM_MATH_CM0PLUS
233 #include "arm_math.h" /* To get __CLZ definitions etc. */
234 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
235 #include "system_efm32hg.h" /* System Header */
236 
237 /**************************************************************************/
243 #include "efm32hg_aes.h"
244 #include "efm32hg_dma_ch.h"
245 #include "efm32hg_dma.h"
246 #include "efm32hg_usb_diep.h"
247 #include "efm32hg_usb_doep.h"
248 #include "efm32hg_usb.h"
249 #include "efm32hg_msc.h"
250 #include "efm32hg_emu.h"
251 #include "efm32hg_rmu.h"
252 #include "efm32hg_cmu.h"
253 #include "efm32hg_timer_cc.h"
254 #include "efm32hg_timer.h"
255 #include "efm32hg_acmp.h"
256 #include "efm32hg_usart.h"
257 #include "efm32hg_prs_ch.h"
258 #include "efm32hg_prs.h"
259 #include "efm32hg_idac.h"
260 #include "efm32hg_gpio_p.h"
261 #include "efm32hg_gpio.h"
262 #include "efm32hg_vcmp.h"
263 #include "efm32hg_adc.h"
264 #include "efm32hg_leuart.h"
265 #include "efm32hg_pcnt.h"
266 #include "efm32hg_i2c.h"
267 #include "efm32hg_rtc.h"
268 #include "efm32hg_wdog.h"
269 #include "efm32hg_mtb.h"
270 #include "efm32hg_dma_descriptor.h"
271 #include "efm32hg_devinfo.h"
272 #include "efm32hg_romtable.h"
273 #include "efm32hg_calibrate.h"
274 
277 /**************************************************************************/
282 #define AES_BASE (0x400E0000UL)
283 #define DMA_BASE (0x400C2000UL)
284 #define USB_BASE (0x400C4000UL)
285 #define MSC_BASE (0x400C0000UL)
286 #define EMU_BASE (0x400C6000UL)
287 #define RMU_BASE (0x400CA000UL)
288 #define CMU_BASE (0x400C8000UL)
289 #define TIMER0_BASE (0x40010000UL)
290 #define TIMER1_BASE (0x40010400UL)
291 #define TIMER2_BASE (0x40010800UL)
292 #define ACMP0_BASE (0x40001000UL)
293 #define USART0_BASE (0x4000C000UL)
294 #define USART1_BASE (0x4000C400UL)
295 #define PRS_BASE (0x400CC000UL)
296 #define IDAC0_BASE (0x40004000UL)
297 #define GPIO_BASE (0x40006000UL)
298 #define VCMP_BASE (0x40000000UL)
299 #define ADC0_BASE (0x40002000UL)
300 #define LEUART0_BASE (0x40084000UL)
301 #define PCNT0_BASE (0x40086000UL)
302 #define I2C0_BASE (0x4000A000UL)
303 #define RTC_BASE (0x40080000UL)
304 #define WDOG_BASE (0x40088000UL)
305 #define MTB_BASE (0xF0040000UL)
306 #define CALIBRATE_BASE (0x0FE08000UL)
307 #define DEVINFO_BASE (0x0FE081B0UL)
308 #define ROMTABLE_BASE (0xF00FFFD0UL)
309 #define LOCKBITS_BASE (0x0FE04000UL)
310 #define USERDATA_BASE (0x0FE00000UL)
314 /**************************************************************************/
319 #define AES ((AES_TypeDef *) AES_BASE)
320 #define DMA ((DMA_TypeDef *) DMA_BASE)
321 #define USB ((USB_TypeDef *) USB_BASE)
322 #define MSC ((MSC_TypeDef *) MSC_BASE)
323 #define EMU ((EMU_TypeDef *) EMU_BASE)
324 #define RMU ((RMU_TypeDef *) RMU_BASE)
325 #define CMU ((CMU_TypeDef *) CMU_BASE)
326 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
327 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
328 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
329 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
330 #define USART0 ((USART_TypeDef *) USART0_BASE)
331 #define USART1 ((USART_TypeDef *) USART1_BASE)
332 #define PRS ((PRS_TypeDef *) PRS_BASE)
333 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)
334 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
335 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
336 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
337 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
338 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
339 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
340 #define RTC ((RTC_TypeDef *) RTC_BASE)
341 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
342 #define MTB ((MTB_TypeDef *) MTB_BASE)
343 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
344 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
345 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
349 /**************************************************************************/
354 #include "efm32hg_prs_signals.h"
355 #include "efm32hg_dmareq.h"
356 #include "efm32hg_dmactrl.h"
357 
358 /**************************************************************************/
362 #define MSC_UNLOCK_CODE 0x1B71
363 #define EMU_UNLOCK_CODE 0xADE8
364 #define CMU_UNLOCK_CODE 0x580E
365 #define TIMER_UNLOCK_CODE 0xCE80
366 #define GPIO_UNLOCK_CODE 0xA534
372 /**************************************************************************/
377 #include "efm32hg_af_ports.h"
378 #include "efm32hg_af_pins.h"
379 
382 /**************************************************************************/
395 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
396  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
397 
402 #ifdef __cplusplus
403 }
404 #endif
405 #endif /* EFM32HG322F64_H */
EFM32HG_ADC register and bit field definitions.
EFM32HG_ROMTABLE register and bit field definitions.
EFM32HG_IDAC register and bit field definitions.
EFM32HG_TIMER register and bit field definitions.
CMSIS Cortex-M System Layer for EFM32 devices.
EFM32HG_USART register and bit field definitions.
EFM32HG_AES register and bit field definitions.
EFM32HG_PCNT register and bit field definitions.
EFM32HG_DMA_CH register and bit field definitions.
EFM32HG_DEVINFO register and bit field definitions.
EFM32HG_WDOG register and bit field definitions.
EFM32HG_ACMP register and bit field definitions.
EFM32HG_DMA register and bit field definitions.
EFM32HG_USB register and bit field definitions.
EFM32HG_TIMER_CC register and bit field definitions.
EFM32HG_MSC register and bit field definitions.
IRQn
Definition: efm32hg322f64.h:52
enum IRQn IRQn_Type
EFM32HG_DMAREQ register and bit field definitions.
EFM32HG_USB_DOEP register and bit field definitions.
EFM32HG_RMU register and bit field definitions.
EFM32HG_GPIO_P register and bit field definitions.
EFM32HG_MTB register and bit field definitions.
EFM32HG_PRS_CH register and bit field definitions.
EFM32HG_RTC register and bit field definitions.
EFM32HG_CALIBRATE register and bit field definitions.
EFM32HG_LEUART register and bit field definitions.
EFM32HG_EMU register and bit field definitions.
EFM32HG_CMU register and bit field definitions.
EFM32HG_PRS register and bit field definitions.
EFM32HG_GPIO register and bit field definitions.
EFM32HG_VCMP register and bit field definitions.
EFM32HG_USB_DIEP register and bit field definitions.
EFM32HG_DMACTRL register and bit field definitions.
EFM32HG_I2C register and bit field definitions.
EFM32HG_DMA_DESCRIPTOR register and bit field definitions.
EFM32HG_AF_PINS register and bit field definitions.