EFM32 Happy Gecko Software Documentation  efm32hg-doc-5.1.2
efm32hg_msc.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IOM uint32_t READCTRL;
45  __IOM uint32_t WRITECTRL;
46  __IOM uint32_t WRITECMD;
47  __IOM uint32_t ADDRB;
49  uint32_t RESERVED0[1];
50  __IOM uint32_t WDATA;
51  __IM uint32_t STATUS;
53  uint32_t RESERVED1[3];
54  __IM uint32_t IF;
55  __IOM uint32_t IFS;
56  __IOM uint32_t IFC;
57  __IOM uint32_t IEN;
58  __IOM uint32_t LOCK;
59  __IOM uint32_t CMD;
60  __IM uint32_t CACHEHITS;
61  __IM uint32_t CACHEMISSES;
62  uint32_t RESERVED2[1];
63  __IOM uint32_t TIMEBASE;
64  __IOM uint32_t MASSLOCK;
65  __IOM uint32_t IRQLATENCY;
66 } MSC_TypeDef;
68 /**************************************************************************/
73 /* Bit fields for MSC CTRL */
74 #define _MSC_CTRL_RESETVALUE 0x00000001UL
75 #define _MSC_CTRL_MASK 0x00000001UL
76 #define MSC_CTRL_BUSFAULT (0x1UL << 0)
77 #define _MSC_CTRL_BUSFAULT_SHIFT 0
78 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL
79 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
80 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
81 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
82 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
83 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
84 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
86 /* Bit fields for MSC READCTRL */
87 #define _MSC_READCTRL_RESETVALUE 0x00000001UL
88 #define _MSC_READCTRL_MASK 0x0000009FUL
89 #define _MSC_READCTRL_MODE_SHIFT 0
90 #define _MSC_READCTRL_MODE_MASK 0x7UL
91 #define _MSC_READCTRL_MODE_WS0 0x00000000UL
92 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
93 #define _MSC_READCTRL_MODE_WS1 0x00000001UL
94 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
95 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
96 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
97 #define MSC_READCTRL_IFCDIS (0x1UL << 3)
98 #define _MSC_READCTRL_IFCDIS_SHIFT 3
99 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL
100 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL
101 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3)
102 #define MSC_READCTRL_AIDIS (0x1UL << 4)
103 #define _MSC_READCTRL_AIDIS_SHIFT 4
104 #define _MSC_READCTRL_AIDIS_MASK 0x10UL
105 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL
106 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4)
107 #define MSC_READCTRL_RAMCEN (0x1UL << 7)
108 #define _MSC_READCTRL_RAMCEN_SHIFT 7
109 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL
110 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL
111 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7)
113 /* Bit fields for MSC WRITECTRL */
114 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
115 #define _MSC_WRITECTRL_MASK 0x00000003UL
116 #define MSC_WRITECTRL_WREN (0x1UL << 0)
117 #define _MSC_WRITECTRL_WREN_SHIFT 0
118 #define _MSC_WRITECTRL_WREN_MASK 0x1UL
119 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
120 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
121 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
122 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
123 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
124 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
125 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
127 /* Bit fields for MSC WRITECMD */
128 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL
129 #define _MSC_WRITECMD_MASK 0x0000113FUL
130 #define MSC_WRITECMD_LADDRIM (0x1UL << 0)
131 #define _MSC_WRITECMD_LADDRIM_SHIFT 0
132 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
133 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
134 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
135 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
136 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
137 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
138 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
139 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
140 #define MSC_WRITECMD_WRITEEND (0x1UL << 2)
141 #define _MSC_WRITECMD_WRITEEND_SHIFT 2
142 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
143 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
144 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
145 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
146 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3
147 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
148 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
149 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
150 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
151 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4
152 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
153 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
154 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
155 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5)
156 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5
157 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL
158 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL
159 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)
160 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8)
161 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8
162 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL
163 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL
164 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)
165 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12)
166 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12
167 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL
168 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL
169 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)
171 /* Bit fields for MSC ADDRB */
172 #define _MSC_ADDRB_RESETVALUE 0x00000000UL
173 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL
174 #define _MSC_ADDRB_ADDRB_SHIFT 0
175 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
176 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
177 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
179 /* Bit fields for MSC WDATA */
180 #define _MSC_WDATA_RESETVALUE 0x00000000UL
181 #define _MSC_WDATA_MASK 0xFFFFFFFFUL
182 #define _MSC_WDATA_WDATA_SHIFT 0
183 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
184 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
185 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
187 /* Bit fields for MSC STATUS */
188 #define _MSC_STATUS_RESETVALUE 0x00000008UL
189 #define _MSC_STATUS_MASK 0x0000007FUL
190 #define MSC_STATUS_BUSY (0x1UL << 0)
191 #define _MSC_STATUS_BUSY_SHIFT 0
192 #define _MSC_STATUS_BUSY_MASK 0x1UL
193 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
194 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
195 #define MSC_STATUS_LOCKED (0x1UL << 1)
196 #define _MSC_STATUS_LOCKED_SHIFT 1
197 #define _MSC_STATUS_LOCKED_MASK 0x2UL
198 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
199 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
200 #define MSC_STATUS_INVADDR (0x1UL << 2)
201 #define _MSC_STATUS_INVADDR_SHIFT 2
202 #define _MSC_STATUS_INVADDR_MASK 0x4UL
203 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
204 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
205 #define MSC_STATUS_WDATAREADY (0x1UL << 3)
206 #define _MSC_STATUS_WDATAREADY_SHIFT 3
207 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL
208 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
209 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
210 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
211 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
212 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
213 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
214 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
215 #define MSC_STATUS_ERASEABORTED (0x1UL << 5)
216 #define _MSC_STATUS_ERASEABORTED_SHIFT 5
217 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
218 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
219 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
220 #define MSC_STATUS_PCRUNNING (0x1UL << 6)
221 #define _MSC_STATUS_PCRUNNING_SHIFT 6
222 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL
223 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL
224 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6)
226 /* Bit fields for MSC IF */
227 #define _MSC_IF_RESETVALUE 0x00000000UL
228 #define _MSC_IF_MASK 0x0000000FUL
229 #define MSC_IF_ERASE (0x1UL << 0)
230 #define _MSC_IF_ERASE_SHIFT 0
231 #define _MSC_IF_ERASE_MASK 0x1UL
232 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL
233 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
234 #define MSC_IF_WRITE (0x1UL << 1)
235 #define _MSC_IF_WRITE_SHIFT 1
236 #define _MSC_IF_WRITE_MASK 0x2UL
237 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL
238 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
239 #define MSC_IF_CHOF (0x1UL << 2)
240 #define _MSC_IF_CHOF_SHIFT 2
241 #define _MSC_IF_CHOF_MASK 0x4UL
242 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL
243 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2)
244 #define MSC_IF_CMOF (0x1UL << 3)
245 #define _MSC_IF_CMOF_SHIFT 3
246 #define _MSC_IF_CMOF_MASK 0x8UL
247 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL
248 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3)
250 /* Bit fields for MSC IFS */
251 #define _MSC_IFS_RESETVALUE 0x00000000UL
252 #define _MSC_IFS_MASK 0x0000000FUL
253 #define MSC_IFS_ERASE (0x1UL << 0)
254 #define _MSC_IFS_ERASE_SHIFT 0
255 #define _MSC_IFS_ERASE_MASK 0x1UL
256 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
257 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
258 #define MSC_IFS_WRITE (0x1UL << 1)
259 #define _MSC_IFS_WRITE_SHIFT 1
260 #define _MSC_IFS_WRITE_MASK 0x2UL
261 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
262 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
263 #define MSC_IFS_CHOF (0x1UL << 2)
264 #define _MSC_IFS_CHOF_SHIFT 2
265 #define _MSC_IFS_CHOF_MASK 0x4UL
266 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL
267 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2)
268 #define MSC_IFS_CMOF (0x1UL << 3)
269 #define _MSC_IFS_CMOF_SHIFT 3
270 #define _MSC_IFS_CMOF_MASK 0x8UL
271 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL
272 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3)
274 /* Bit fields for MSC IFC */
275 #define _MSC_IFC_RESETVALUE 0x00000000UL
276 #define _MSC_IFC_MASK 0x0000000FUL
277 #define MSC_IFC_ERASE (0x1UL << 0)
278 #define _MSC_IFC_ERASE_SHIFT 0
279 #define _MSC_IFC_ERASE_MASK 0x1UL
280 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
281 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
282 #define MSC_IFC_WRITE (0x1UL << 1)
283 #define _MSC_IFC_WRITE_SHIFT 1
284 #define _MSC_IFC_WRITE_MASK 0x2UL
285 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
286 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
287 #define MSC_IFC_CHOF (0x1UL << 2)
288 #define _MSC_IFC_CHOF_SHIFT 2
289 #define _MSC_IFC_CHOF_MASK 0x4UL
290 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL
291 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2)
292 #define MSC_IFC_CMOF (0x1UL << 3)
293 #define _MSC_IFC_CMOF_SHIFT 3
294 #define _MSC_IFC_CMOF_MASK 0x8UL
295 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL
296 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3)
298 /* Bit fields for MSC IEN */
299 #define _MSC_IEN_RESETVALUE 0x00000000UL
300 #define _MSC_IEN_MASK 0x0000000FUL
301 #define MSC_IEN_ERASE (0x1UL << 0)
302 #define _MSC_IEN_ERASE_SHIFT 0
303 #define _MSC_IEN_ERASE_MASK 0x1UL
304 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
305 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
306 #define MSC_IEN_WRITE (0x1UL << 1)
307 #define _MSC_IEN_WRITE_SHIFT 1
308 #define _MSC_IEN_WRITE_MASK 0x2UL
309 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
310 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
311 #define MSC_IEN_CHOF (0x1UL << 2)
312 #define _MSC_IEN_CHOF_SHIFT 2
313 #define _MSC_IEN_CHOF_MASK 0x4UL
314 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL
315 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2)
316 #define MSC_IEN_CMOF (0x1UL << 3)
317 #define _MSC_IEN_CMOF_SHIFT 3
318 #define _MSC_IEN_CMOF_MASK 0x8UL
319 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL
320 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3)
322 /* Bit fields for MSC LOCK */
323 #define _MSC_LOCK_RESETVALUE 0x00000000UL
324 #define _MSC_LOCK_MASK 0x0000FFFFUL
325 #define _MSC_LOCK_LOCKKEY_SHIFT 0
326 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
327 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
328 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
329 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
330 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
331 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
332 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
333 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
334 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
335 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
336 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
338 /* Bit fields for MSC CMD */
339 #define _MSC_CMD_RESETVALUE 0x00000000UL
340 #define _MSC_CMD_MASK 0x00000007UL
341 #define MSC_CMD_INVCACHE (0x1UL << 0)
342 #define _MSC_CMD_INVCACHE_SHIFT 0
343 #define _MSC_CMD_INVCACHE_MASK 0x1UL
344 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL
345 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0)
346 #define MSC_CMD_STARTPC (0x1UL << 1)
347 #define _MSC_CMD_STARTPC_SHIFT 1
348 #define _MSC_CMD_STARTPC_MASK 0x2UL
349 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL
350 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1)
351 #define MSC_CMD_STOPPC (0x1UL << 2)
352 #define _MSC_CMD_STOPPC_SHIFT 2
353 #define _MSC_CMD_STOPPC_MASK 0x4UL
354 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL
355 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2)
357 /* Bit fields for MSC CACHEHITS */
358 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL
359 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL
360 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0
361 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL
362 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL
363 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)
365 /* Bit fields for MSC CACHEMISSES */
366 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL
367 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL
368 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0
369 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL
370 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL
371 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)
373 /* Bit fields for MSC TIMEBASE */
374 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL
375 #define _MSC_TIMEBASE_MASK 0x0001003FUL
376 #define _MSC_TIMEBASE_BASE_SHIFT 0
377 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL
378 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL
379 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0)
380 #define MSC_TIMEBASE_PERIOD (0x1UL << 16)
381 #define _MSC_TIMEBASE_PERIOD_SHIFT 16
382 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL
383 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL
384 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL
385 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL
386 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16)
387 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16)
388 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16)
390 /* Bit fields for MSC MASSLOCK */
391 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL
392 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL
393 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0
394 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL
395 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL
396 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL
397 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL
398 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL
399 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL
400 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)
401 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)
402 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)
403 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)
404 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)
406 /* Bit fields for MSC IRQLATENCY */
407 #define _MSC_IRQLATENCY_RESETVALUE 0x00000000UL
408 #define _MSC_IRQLATENCY_MASK 0x000000FFUL
409 #define _MSC_IRQLATENCY_IRQLATENCY_SHIFT 0
410 #define _MSC_IRQLATENCY_IRQLATENCY_MASK 0xFFUL
411 #define _MSC_IRQLATENCY_IRQLATENCY_DEFAULT 0x00000000UL
412 #define MSC_IRQLATENCY_IRQLATENCY_DEFAULT (_MSC_IRQLATENCY_IRQLATENCY_DEFAULT << 0)
__IOM uint32_t MASSLOCK
Definition: efm32hg_msc.h:64
__IM uint32_t CACHEHITS
Definition: efm32hg_msc.h:60
__IOM uint32_t LOCK
Definition: efm32hg_msc.h:58
__IOM uint32_t IRQLATENCY
Definition: efm32hg_msc.h:65
__IOM uint32_t IEN
Definition: efm32hg_msc.h:57
__IM uint32_t STATUS
Definition: efm32hg_msc.h:51
__IOM uint32_t WDATA
Definition: efm32hg_msc.h:50
__IOM uint32_t TIMEBASE
Definition: efm32hg_msc.h:63
__IOM uint32_t READCTRL
Definition: efm32hg_msc.h:44
__IOM uint32_t IFC
Definition: efm32hg_msc.h:56
__IOM uint32_t ADDRB
Definition: efm32hg_msc.h:47
__IM uint32_t CACHEMISSES
Definition: efm32hg_msc.h:61
__IOM uint32_t IFS
Definition: efm32hg_msc.h:55
__IOM uint32_t WRITECTRL
Definition: efm32hg_msc.h:45
__IOM uint32_t CMD
Definition: efm32hg_msc.h:59
__IOM uint32_t CTRL
Definition: efm32hg_msc.h:43
__IM uint32_t IF
Definition: efm32hg_msc.h:54
__IOM uint32_t WRITECMD
Definition: efm32hg_msc.h:46