EFM32 Happy Gecko Software Documentation  efm32hg-doc-5.1.2
efm32hg_rtc.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IOM uint32_t CNT;
45  __IOM uint32_t COMP0;
46  __IOM uint32_t COMP1;
47  __IM uint32_t IF;
48  __IOM uint32_t IFS;
49  __IOM uint32_t IFC;
50  __IOM uint32_t IEN;
52  __IOM uint32_t FREEZE;
53  __IM uint32_t SYNCBUSY;
54 } RTC_TypeDef;
56 /**************************************************************************/
61 /* Bit fields for RTC CTRL */
62 #define _RTC_CTRL_RESETVALUE 0x00000000UL
63 #define _RTC_CTRL_MASK 0x00000007UL
64 #define RTC_CTRL_EN (0x1UL << 0)
65 #define _RTC_CTRL_EN_SHIFT 0
66 #define _RTC_CTRL_EN_MASK 0x1UL
67 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL
68 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0)
69 #define RTC_CTRL_DEBUGRUN (0x1UL << 1)
70 #define _RTC_CTRL_DEBUGRUN_SHIFT 1
71 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL
72 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
73 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1)
74 #define RTC_CTRL_COMP0TOP (0x1UL << 2)
75 #define _RTC_CTRL_COMP0TOP_SHIFT 2
76 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL
77 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL
78 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL
79 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL
80 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2)
81 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2)
82 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2)
84 /* Bit fields for RTC CNT */
85 #define _RTC_CNT_RESETVALUE 0x00000000UL
86 #define _RTC_CNT_MASK 0x00FFFFFFUL
87 #define _RTC_CNT_CNT_SHIFT 0
88 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL
89 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL
90 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0)
92 /* Bit fields for RTC COMP0 */
93 #define _RTC_COMP0_RESETVALUE 0x00000000UL
94 #define _RTC_COMP0_MASK 0x00FFFFFFUL
95 #define _RTC_COMP0_COMP0_SHIFT 0
96 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL
97 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL
98 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0)
100 /* Bit fields for RTC COMP1 */
101 #define _RTC_COMP1_RESETVALUE 0x00000000UL
102 #define _RTC_COMP1_MASK 0x00FFFFFFUL
103 #define _RTC_COMP1_COMP1_SHIFT 0
104 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL
105 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL
106 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0)
108 /* Bit fields for RTC IF */
109 #define _RTC_IF_RESETVALUE 0x00000000UL
110 #define _RTC_IF_MASK 0x00000007UL
111 #define RTC_IF_OF (0x1UL << 0)
112 #define _RTC_IF_OF_SHIFT 0
113 #define _RTC_IF_OF_MASK 0x1UL
114 #define _RTC_IF_OF_DEFAULT 0x00000000UL
115 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0)
116 #define RTC_IF_COMP0 (0x1UL << 1)
117 #define _RTC_IF_COMP0_SHIFT 1
118 #define _RTC_IF_COMP0_MASK 0x2UL
119 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL
120 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1)
121 #define RTC_IF_COMP1 (0x1UL << 2)
122 #define _RTC_IF_COMP1_SHIFT 2
123 #define _RTC_IF_COMP1_MASK 0x4UL
124 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL
125 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2)
127 /* Bit fields for RTC IFS */
128 #define _RTC_IFS_RESETVALUE 0x00000000UL
129 #define _RTC_IFS_MASK 0x00000007UL
130 #define RTC_IFS_OF (0x1UL << 0)
131 #define _RTC_IFS_OF_SHIFT 0
132 #define _RTC_IFS_OF_MASK 0x1UL
133 #define _RTC_IFS_OF_DEFAULT 0x00000000UL
134 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0)
135 #define RTC_IFS_COMP0 (0x1UL << 1)
136 #define _RTC_IFS_COMP0_SHIFT 1
137 #define _RTC_IFS_COMP0_MASK 0x2UL
138 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL
139 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1)
140 #define RTC_IFS_COMP1 (0x1UL << 2)
141 #define _RTC_IFS_COMP1_SHIFT 2
142 #define _RTC_IFS_COMP1_MASK 0x4UL
143 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL
144 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2)
146 /* Bit fields for RTC IFC */
147 #define _RTC_IFC_RESETVALUE 0x00000000UL
148 #define _RTC_IFC_MASK 0x00000007UL
149 #define RTC_IFC_OF (0x1UL << 0)
150 #define _RTC_IFC_OF_SHIFT 0
151 #define _RTC_IFC_OF_MASK 0x1UL
152 #define _RTC_IFC_OF_DEFAULT 0x00000000UL
153 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0)
154 #define RTC_IFC_COMP0 (0x1UL << 1)
155 #define _RTC_IFC_COMP0_SHIFT 1
156 #define _RTC_IFC_COMP0_MASK 0x2UL
157 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL
158 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1)
159 #define RTC_IFC_COMP1 (0x1UL << 2)
160 #define _RTC_IFC_COMP1_SHIFT 2
161 #define _RTC_IFC_COMP1_MASK 0x4UL
162 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL
163 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2)
165 /* Bit fields for RTC IEN */
166 #define _RTC_IEN_RESETVALUE 0x00000000UL
167 #define _RTC_IEN_MASK 0x00000007UL
168 #define RTC_IEN_OF (0x1UL << 0)
169 #define _RTC_IEN_OF_SHIFT 0
170 #define _RTC_IEN_OF_MASK 0x1UL
171 #define _RTC_IEN_OF_DEFAULT 0x00000000UL
172 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0)
173 #define RTC_IEN_COMP0 (0x1UL << 1)
174 #define _RTC_IEN_COMP0_SHIFT 1
175 #define _RTC_IEN_COMP0_MASK 0x2UL
176 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL
177 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1)
178 #define RTC_IEN_COMP1 (0x1UL << 2)
179 #define _RTC_IEN_COMP1_SHIFT 2
180 #define _RTC_IEN_COMP1_MASK 0x4UL
181 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL
182 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2)
184 /* Bit fields for RTC FREEZE */
185 #define _RTC_FREEZE_RESETVALUE 0x00000000UL
186 #define _RTC_FREEZE_MASK 0x00000001UL
187 #define RTC_FREEZE_REGFREEZE (0x1UL << 0)
188 #define _RTC_FREEZE_REGFREEZE_SHIFT 0
189 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL
190 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
191 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL
192 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL
193 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0)
194 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0)
195 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0)
197 /* Bit fields for RTC SYNCBUSY */
198 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL
199 #define _RTC_SYNCBUSY_MASK 0x00000007UL
200 #define RTC_SYNCBUSY_CTRL (0x1UL << 0)
201 #define _RTC_SYNCBUSY_CTRL_SHIFT 0
202 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL
203 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
204 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0)
205 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1)
206 #define _RTC_SYNCBUSY_COMP0_SHIFT 1
207 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL
208 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL
209 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1)
210 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2)
211 #define _RTC_SYNCBUSY_COMP1_SHIFT 2
212 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL
213 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL
214 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2)
__IOM uint32_t IFC
Definition: efm32hg_rtc.h:49
__IM uint32_t IF
Definition: efm32hg_rtc.h:47
__IM uint32_t SYNCBUSY
Definition: efm32hg_rtc.h:53
__IOM uint32_t CTRL
Definition: efm32hg_rtc.h:43
__IOM uint32_t COMP0
Definition: efm32hg_rtc.h:45
__IOM uint32_t IEN
Definition: efm32hg_rtc.h:50
__IOM uint32_t IFS
Definition: efm32hg_rtc.h:48
__IOM uint32_t FREEZE
Definition: efm32hg_rtc.h:52
__IOM uint32_t COMP1
Definition: efm32hg_rtc.h:46
__IOM uint32_t CNT
Definition: efm32hg_rtc.h:44