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efm32hg_rtc.h
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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typedef
struct
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{
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__IOM uint32_t
CTRL
;
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__IOM uint32_t
CNT
;
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__IOM uint32_t
COMP0
;
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__IOM uint32_t
COMP1
;
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__IM uint32_t
IF
;
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__IOM uint32_t
IFS
;
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__IOM uint32_t
IFC
;
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__IOM uint32_t
IEN
;
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__IOM uint32_t
FREEZE
;
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__IM uint32_t
SYNCBUSY
;
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}
RTC_TypeDef
;
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/**************************************************************************/
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/* Bit fields for RTC CTRL */
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#define _RTC_CTRL_RESETVALUE 0x00000000UL
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#define _RTC_CTRL_MASK 0x00000007UL
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#define RTC_CTRL_EN (0x1UL << 0)
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#define _RTC_CTRL_EN_SHIFT 0
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#define _RTC_CTRL_EN_MASK 0x1UL
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#define _RTC_CTRL_EN_DEFAULT 0x00000000UL
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#define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0)
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#define RTC_CTRL_DEBUGRUN (0x1UL << 1)
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#define _RTC_CTRL_DEBUGRUN_SHIFT 1
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#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL
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#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
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#define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1)
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#define RTC_CTRL_COMP0TOP (0x1UL << 2)
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#define _RTC_CTRL_COMP0TOP_SHIFT 2
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#define _RTC_CTRL_COMP0TOP_MASK 0x4UL
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#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL
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#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL
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#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL
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#define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2)
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#define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2)
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#define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2)
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/* Bit fields for RTC CNT */
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#define _RTC_CNT_RESETVALUE 0x00000000UL
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#define _RTC_CNT_MASK 0x00FFFFFFUL
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#define _RTC_CNT_CNT_SHIFT 0
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#define _RTC_CNT_CNT_MASK 0xFFFFFFUL
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#define _RTC_CNT_CNT_DEFAULT 0x00000000UL
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#define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0)
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/* Bit fields for RTC COMP0 */
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#define _RTC_COMP0_RESETVALUE 0x00000000UL
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#define _RTC_COMP0_MASK 0x00FFFFFFUL
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#define _RTC_COMP0_COMP0_SHIFT 0
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#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL
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#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL
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#define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0)
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/* Bit fields for RTC COMP1 */
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#define _RTC_COMP1_RESETVALUE 0x00000000UL
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#define _RTC_COMP1_MASK 0x00FFFFFFUL
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#define _RTC_COMP1_COMP1_SHIFT 0
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#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL
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#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL
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#define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0)
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/* Bit fields for RTC IF */
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#define _RTC_IF_RESETVALUE 0x00000000UL
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#define _RTC_IF_MASK 0x00000007UL
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#define RTC_IF_OF (0x1UL << 0)
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#define _RTC_IF_OF_SHIFT 0
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#define _RTC_IF_OF_MASK 0x1UL
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#define _RTC_IF_OF_DEFAULT 0x00000000UL
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#define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0)
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#define RTC_IF_COMP0 (0x1UL << 1)
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#define _RTC_IF_COMP0_SHIFT 1
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#define _RTC_IF_COMP0_MASK 0x2UL
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#define _RTC_IF_COMP0_DEFAULT 0x00000000UL
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#define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1)
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#define RTC_IF_COMP1 (0x1UL << 2)
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#define _RTC_IF_COMP1_SHIFT 2
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#define _RTC_IF_COMP1_MASK 0x4UL
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#define _RTC_IF_COMP1_DEFAULT 0x00000000UL
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#define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2)
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/* Bit fields for RTC IFS */
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#define _RTC_IFS_RESETVALUE 0x00000000UL
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#define _RTC_IFS_MASK 0x00000007UL
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#define RTC_IFS_OF (0x1UL << 0)
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#define _RTC_IFS_OF_SHIFT 0
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#define _RTC_IFS_OF_MASK 0x1UL
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#define _RTC_IFS_OF_DEFAULT 0x00000000UL
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#define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0)
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#define RTC_IFS_COMP0 (0x1UL << 1)
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#define _RTC_IFS_COMP0_SHIFT 1
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#define _RTC_IFS_COMP0_MASK 0x2UL
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#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL
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#define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1)
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#define RTC_IFS_COMP1 (0x1UL << 2)
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#define _RTC_IFS_COMP1_SHIFT 2
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#define _RTC_IFS_COMP1_MASK 0x4UL
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#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL
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#define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2)
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/* Bit fields for RTC IFC */
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#define _RTC_IFC_RESETVALUE 0x00000000UL
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#define _RTC_IFC_MASK 0x00000007UL
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#define RTC_IFC_OF (0x1UL << 0)
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#define _RTC_IFC_OF_SHIFT 0
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#define _RTC_IFC_OF_MASK 0x1UL
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#define _RTC_IFC_OF_DEFAULT 0x00000000UL
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#define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0)
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#define RTC_IFC_COMP0 (0x1UL << 1)
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#define _RTC_IFC_COMP0_SHIFT 1
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#define _RTC_IFC_COMP0_MASK 0x2UL
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#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL
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#define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1)
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#define RTC_IFC_COMP1 (0x1UL << 2)
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#define _RTC_IFC_COMP1_SHIFT 2
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#define _RTC_IFC_COMP1_MASK 0x4UL
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#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL
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#define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2)
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/* Bit fields for RTC IEN */
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#define _RTC_IEN_RESETVALUE 0x00000000UL
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#define _RTC_IEN_MASK 0x00000007UL
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#define RTC_IEN_OF (0x1UL << 0)
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#define _RTC_IEN_OF_SHIFT 0
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#define _RTC_IEN_OF_MASK 0x1UL
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#define _RTC_IEN_OF_DEFAULT 0x00000000UL
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#define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0)
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#define RTC_IEN_COMP0 (0x1UL << 1)
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#define _RTC_IEN_COMP0_SHIFT 1
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#define _RTC_IEN_COMP0_MASK 0x2UL
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#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL
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#define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1)
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#define RTC_IEN_COMP1 (0x1UL << 2)
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#define _RTC_IEN_COMP1_SHIFT 2
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#define _RTC_IEN_COMP1_MASK 0x4UL
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#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL
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#define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2)
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/* Bit fields for RTC FREEZE */
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#define _RTC_FREEZE_RESETVALUE 0x00000000UL
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#define _RTC_FREEZE_MASK 0x00000001UL
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#define RTC_FREEZE_REGFREEZE (0x1UL << 0)
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#define _RTC_FREEZE_REGFREEZE_SHIFT 0
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#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL
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#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
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#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL
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#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL
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#define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0)
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#define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0)
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#define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0)
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/* Bit fields for RTC SYNCBUSY */
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#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL
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#define _RTC_SYNCBUSY_MASK 0x00000007UL
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#define RTC_SYNCBUSY_CTRL (0x1UL << 0)
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#define _RTC_SYNCBUSY_CTRL_SHIFT 0
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#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL
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#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
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#define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0)
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#define RTC_SYNCBUSY_COMP0 (0x1UL << 1)
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#define _RTC_SYNCBUSY_COMP0_SHIFT 1
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#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL
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#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL
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#define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1)
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#define RTC_SYNCBUSY_COMP1 (0x1UL << 2)
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#define _RTC_SYNCBUSY_COMP1_SHIFT 2
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#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL
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#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL
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#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2)
RTC_TypeDef::IFC
__IOM uint32_t IFC
Definition:
efm32hg_rtc.h:49
RTC_TypeDef::IF
__IM uint32_t IF
Definition:
efm32hg_rtc.h:47
RTC_TypeDef::SYNCBUSY
__IM uint32_t SYNCBUSY
Definition:
efm32hg_rtc.h:53
RTC_TypeDef
Definition:
efm32hg_rtc.h:41
RTC_TypeDef::CTRL
__IOM uint32_t CTRL
Definition:
efm32hg_rtc.h:43
RTC_TypeDef::COMP0
__IOM uint32_t COMP0
Definition:
efm32hg_rtc.h:45
RTC_TypeDef::IEN
__IOM uint32_t IEN
Definition:
efm32hg_rtc.h:50
RTC_TypeDef::IFS
__IOM uint32_t IFS
Definition:
efm32hg_rtc.h:48
RTC_TypeDef::FREEZE
__IOM uint32_t FREEZE
Definition:
efm32hg_rtc.h:52
RTC_TypeDef::COMP1
__IOM uint32_t COMP1
Definition:
efm32hg_rtc.h:46
RTC_TypeDef::CNT
__IOM uint32_t CNT
Definition:
efm32hg_rtc.h:44
platform
Device
SiliconLabs
EFM32HG
Include
efm32hg_rtc.h
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