20 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
54 volatile unsigned long loops_per_jiffy = (1<<12);
61 static void calibrate_delay(
void);
62 __STATIC_INLINE uint32_t clock(
void);
63 static void _delay( uint32_t delay);
75 bool rtcRestore =
false;
76 bool leClkTurnoff =
false;
77 bool rtcClkTurnoff =
false;
78 bool lfaClkSrcRestore =
false;
79 bool lfaClkTurnoff =
false;
80 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
81 RTCC_Init_TypeDef init = RTCC_INIT_DEFAULT;
82 uint32_t rtcCtrl=0, rtcIen=0;
85 uint32_t rtcCtrl=0, rtcComp0=0, rtcComp1=0, rtcIen=0;
90 #if defined (_CMU_HFBUSCLKEN0_MASK)
91 if ( !(
CMU->HFBUSCLKEN0 & CMU_HFBUSCLKEN0_LE) )
100 #if defined (CMU_LFECLKEN0_RTCC)
106 #if defined( UDELAY_LFXO )
109 lfaClkTurnoff =
true;
115 lfaClkSrcRestore =
true;
116 #if defined (CMU_LFECLKEN0_RTCC)
126 lfaClkSrcRestore =
true;
130 lfaClkTurnoff =
true;
133 #if defined (CMU_LFECLKEN0_RTCC)
141 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
143 if ( !(
CMU->LFECLKEN0 & CMU_LFECLKEN0_RTCC) )
147 rtcClkTurnoff =
true;
156 rtcClkTurnoff =
true;
162 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
163 if ( RTCC->CTRL & RTCC_CTRL_ENABLE )
166 rtcCtrl = RTCC->CTRL;
169 RTCC->CTRL = _RTCC_CTRL_RESETVALUE;
171 RTCC->IFC = _RTCC_IEN_MASK;
173 NVIC_ClearPendingIRQ( RTCC_IRQn );
177 init.precntWrapOnCCV0 =
false;
178 init.cntWrapOnCCV1 =
false;
179 init.presc = rtccCntPresc_256;
188 rtcComp0 =
RTC->COMP0;
189 rtcComp1 =
RTC->COMP1;
213 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
215 RTCC->CTRL = rtcCtrl;
220 #if defined(_EFM32_GECKO_FAMILY)
223 RTC->COMP0 = rtcComp0;
224 RTC->COMP1 = rtcComp1;
232 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
241 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
248 if ( lfaClkSrcRestore )
250 #if defined (CMU_LFECLKEN0_RTCC)
259 #if defined( UDELAY_LFXO )
272 #if defined(__GNUC__)
287 #if ( __CORTEX_M == 0x00 )
288 " .syntax unified \n"
295 " lsls r2, r2, #8 \n"
300 " movs r0, %0, lsr #11 \n"
301 " movs r2, r2, lsr #11 \n"
304 " movs r0, r0, lsr #6 \n"
310 #if ( __CORTEX_M == 0x00 )
312 " .syntax divided \n" : :
"r" (usecs),
"r" (&loops_per_jiffy) :
"r0",
"r2",
"cc" );
314 "2: \n" : :
"r" (usecs),
"r" (&loops_per_jiffy) :
"r0",
"r2",
"cc" );
321 static void calibrate_delay(
void)
324 unsigned long loopbit;
326 int lps_precision = LPS_PREC;
328 loops_per_jiffy = (1<<12);
330 while (loops_per_jiffy <<= 1) {
333 while (ticks == clock())
337 _delay(loops_per_jiffy);
338 ticks = clock() - ticks;
346 loops_per_jiffy >>= 1;
347 loopbit = loops_per_jiffy;
348 while ( lps_precision-- && (loopbit >>= 1) ) {
349 loops_per_jiffy |= loopbit;
351 while (ticks == clock());
353 _delay(loops_per_jiffy);
354 if (clock() != ticks)
355 loops_per_jiffy &= ~loopbit;
359 __STATIC_INLINE uint32_t clock(
void)
361 #if defined( RTCC_PRESENT ) && ( RTCC_COUNT == 1 )
362 return RTCC_CounterGet();
368 #if defined(__ICCARM__)
369 static void _delay( uint32_t delay)
374 " bhi.n _delay_1 \n" );
384 " lsls r2, r2, #8 \n"
389 " movs r0, %0, lsr #11 \n"
390 " movs r2, r2, lsr #11 \n"
393 " movs r0, r0, lsr #6 \n"
400 "udelay_2: \n" : :
"r" (usecs),
"r" (&loops_per_jiffy) :
"r0",
"r2",
"cc");
404 #if defined(__GNUC__)
405 static void _delay( uint32_t delay )
408 #if ( __CORTEX_M == 0x00 )
409 " .syntax unified \n"
413 #if ( __CORTEX_M == 0x00 )
415 " .syntax divided \n" : :
"r" (delay) );
417 " bhi.n 1b \n" : :
"r" (delay) );
422 #if defined(__CC_ARM)
423 static __ASM
void _delay( uint32_t delay)
431 __ASM
void UDELAY_Delay( uint32_t usecs __attribute__ ((unused)) )
433 IMPORT loops_per_jiffy
443 ldr r2, =loops_per_jiffy
Clock management unit (CMU) API.
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
#define CORE_DECLARE_IRQ_STATE
#define _RTC_CTRL_RESETVALUE
__STATIC_INLINE uint32_t RTC_CounterGet(void)
Get RTC counter value.
void UDELAY_Calibrate(void)
Calibrates the microsecond delay loop.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define RTC_SYNCBUSY_COMP0
uint32_t CMU_ClkDiv_TypeDef
#define CMU_LFACLKEN0_RTC
#define CORE_ENTER_ATOMIC()
Microsecond delay routine.
Real Time Counter (RTCC) peripheral API.
void RTC_Init(const RTC_Init_TypeDef *init)
Initialize RTC.
Core interrupt handling API.
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
#define CORE_EXIT_ATOMIC()
Real Time Counter (RTC) peripheral API.
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
#define RTC_SYNCBUSY_COMP1
void RTC_Enable(bool enable)
Enable/disable RTC.
#define CMU_STATUS_LFXOENS
void RTC_FreezeEnable(bool enable)
RTC register synchronization freeze control.
#define RTC_SYNCBUSY_CTRL
#define CMU_HFCORECLKEN0_LE
#define CMU_STATUS_LFRCOENS
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
void UDELAY_Delay(uint32_t usecs)
Microsecond active wait delay routine.
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.