55 #define CORE_ATOMIC_METHOD_PRIMASK 0
58 #define CORE_ATOMIC_METHOD_BASEPRI 1
61 #define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32)
64 #define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16)
67 #if (CORE_NVIC_REG_WORDS > 3)
68 #error "em_core: Unexpected NVIC external interrupt count."
85 #define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState
88 #define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq()
91 #define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq()
94 #define CORE_CRITICAL_SECTION(yourcode) \
96 CORE_DECLARE_IRQ_STATE; \
97 CORE_ENTER_CRITICAL(); \
101 CORE_EXIT_CRITICAL(); \
106 #define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical()
110 #define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState)
113 #define CORE_YIELD_CRITICAL() CORE_YieldCritical(void)
120 #define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq()
123 #define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq()
126 #define CORE_ATOMIC_SECTION(yourcode) \
128 CORE_DECLARE_IRQ_STATE; \
129 CORE_ENTER_ATOMIC(); \
133 CORE_EXIT_ATOMIC(); \
138 #define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic()
142 #define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState)
145 #define CORE_YIELD_ATOMIC() CORE_YieldAtomic(void)
153 #define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState
158 #define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x
163 #define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = {{0}}
168 #define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask)
173 #define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask)
180 #define CORE_NVIC_SECTION(mask, yourcode) \
182 CORE_DECLARE_NVIC_STATE; \
183 CORE_ENTER_NVIC(mask); \
194 #define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState,disable)
198 #define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState)
203 #define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable)
210 #define CORE_IRQ_DISABLED() CORE_IrqIsDisabled()
213 #define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext()
263 uint32_t *targetTable,
265 void *defaultHandler,
266 bool overwriteActive);
bool CORE_NvicIRQDisabled(IRQn_Type irqN)
Check if a NVIC interrupt is disabled.
void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)
Utility function to set the handler for a specific interrupt.
void CORE_CriticalDisableIrq(void)
Disable interrupts.
void CORE_YieldAtomic(void)
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
General purpose utilities.
void CORE_NvicDisableMask(const CORE_nvicMask_t *disable)
Disable NVIC interrupts.
bool CORE_InIrqContext(void)
Check if current cpu operation mode is handler mode.
bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask)
Get NVIC disable state for a given mask.
void CORE_ExitAtomic(CORE_irqState_t irqState)
Exit an ATOMIC section.
#define CORE_NVIC_REG_WORDS
void CORE_YieldCritical(void)
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
void CORE_CriticalEnableIrq(void)
Enable interrupts.
CORE_irqState_t CORE_EnterCritical(void)
Enter a CRITICAL section.
void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask)
Get current NVIC enable mask state.
void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)
Enter a NVIC mask section.
bool CORE_IrqIsBlocked(IRQn_Type irqN)
Check if a specific interrupt is disabled or blocked.
bool CORE_IrqIsDisabled(void)
Check if interrupts are disabled.
void CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)
Initialize an interrupt vector table by copying table entries from a source to a target table...
void * CORE_GetNvicRamTableHandler(IRQn_Type irqN)
Utility function to get the handler for a specific interrupt.
void CORE_AtomicEnableIrq(void)
Enable interrupts.
void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)
Utility function to set an IRQn bit in a NVIC enable/disable mask.
void CORE_NvicEnableMask(const CORE_nvicMask_t *enable)
Set current NVIC interrupt enable mask.
void CORE_ExitCritical(CORE_irqState_t irqState)
Exit a CRITICAL section.
void CORE_AtomicDisableIrq(void)
Disable interrupts.
CORE_irqState_t CORE_EnterAtomic(void)
Enter an ATOMIC section.