33 #if defined( CMU_PRESENT )
64 #if defined( _SILICON_LABS_32B_SERIES_1 )
66 #define CMU_MAX_FREQ_0WS 26000000
68 #define CMU_MAX_FREQ_1WS 40000000
69 #elif defined( _SILICON_LABS_32B_SERIES_0 )
71 #define CMU_MAX_FREQ_0WS 16000000
73 #define CMU_MAX_FREQ_1WS 32000000
75 #error "Max Flash wait-state frequencies are not defined for this platform."
79 #if defined( CMU_CTRL_HFLE )
81 #if defined( _SILICON_LABS_32B_SERIES_0 ) \
82 && (defined( _EFM32_WONDER_FAMILY ) \
83 || defined( _EZR32_WONDER_FAMILY ))
84 #define CMU_MAX_FREQ_HFLE 24000000
87 #elif defined( _SILICON_LABS_32B_SERIES_0 ) \
88 && (defined( _EFM32_GIANT_FAMILY ) \
89 || defined( _EFM32_LEOPARD_FAMILY ) \
90 || defined( _EZR32_LEOPARD_FAMILY ))
91 #define CMU_MAX_FREQ_HFLE maxFreqHfle()
93 #elif defined( CMU_CTRL_WSHFLE )
95 #define CMU_MAX_FREQ_HFLE 32000000
103 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
104 static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
106 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
107 #define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK)
118 #if defined( _SILICON_LABS_32B_SERIES_0 ) \
119 && (defined( _EFM32_GIANT_FAMILY ) \
120 || defined( _EFM32_LEOPARD_FAMILY ) \
121 || defined( _EZR32_LEOPARD_FAMILY ))
126 static uint32_t maxFreqHfle(
void)
128 uint16_t majorMinorRev;
144 if (majorMinorRev >= 0x0204)
164 #if defined( CMU_MAX_FREQ_HFLE )
167 #if defined( CMU_CTRL_HFLE )
168 #define CMU_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK
169 #define CMU_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT
170 #define CMU_HFLE_PRESC_REG CMU->HFCORECLKDIV
171 #define CMU_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK
172 #define CMU_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT
173 #elif defined( CMU_CTRL_WSHFLE )
174 #define CMU_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK
175 #define CMU_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT
176 #define CMU_HFLE_PRESC_REG CMU->HFPRESC
177 #define CMU_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK
178 #define CMU_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
191 static void setHfLeConfig(uint32_t hfFreq, uint32_t maxLeFreq)
195 EFM_ASSERT((CMU_HFLE_WS_MASK >> CMU_HFLE_WS_SHIFT) == 0x1);
196 EFM_ASSERT((CMU_HFLE_PRESC_MASK >> CMU_HFLE_PRESC_SHIFT) == 0x1);
200 unsigned int val = (hfFreq <= maxLeFreq) ? 0 : 1;
213 static uint32_t getHfLeConfig(
void)
216 uint32_t presc =
BUS_RegBitRead(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT);
220 EFM_ASSERT(ws == presc);
234 static uint32_t auxClkGet(
void)
238 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
241 #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
279 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
280 case CMU_AUXHFRCOCTRL_BAND_28MHZ:
308 static uint32_t dbgClkGet(
void)
343 static void flashWaitStateControl(uint32_t coreFreq)
347 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
352 mscLocked =
MSC->LOCK;
357 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
362 #if defined( MSC_READCTRL_MODE_WS2 )
363 case MSC_READCTRL_MODE_WS2:
376 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
380 #if defined( MSC_READCTRL_MODE_WS2 )
381 else if (coreFreq > CMU_MAX_FREQ_1WS)
383 mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
386 else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
400 #if defined( MSC_READCTRL_MODE_WS2 )
401 else if (coreFreq > CMU_MAX_FREQ_1WS)
403 mode = MSC_READCTRL_MODE_WS2;
406 else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
433 static void flashWaitStateMax(
void)
439 #if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)
444 static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh)
446 uint32_t regIshUpper;
447 const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
448 >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
450 regIshUpper =
SL_MIN(steadyStateRegIsh + 3, upperMax);
451 regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
477 #if defined( _CMU_LFCCLKEN0_MASK )
480 #if defined( _CMU_LFECLKSEL_MASK )
496 #if defined( _CMU_LFCLKSEL_MASK )
498 #elif defined( _CMU_LFACLKSEL_MASK )
499 sel = (
CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
506 #if defined( _CMU_LFCLKSEL_MASK )
508 #elif defined( _CMU_LFBCLKSEL_MASK )
509 sel = (
CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
515 #if defined( _CMU_LFCCLKEN0_MASK )
521 #if defined( _CMU_LFECLKSEL_MASK )
523 sel = (
CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
533 #if defined( _CMU_LFCLKSEL_MASK )
544 #if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
546 #if defined( CMU_MAX_FREQ_HFLE )
556 #if defined( CMU_LFCLKSEL_LFAE )
577 #if defined( _CMU_LFACLKSEL_MASK )
580 case _CMU_LFACLKSEL_LFA_LFRCO:
584 case _CMU_LFACLKSEL_LFA_LFXO:
588 case _CMU_LFACLKSEL_LFA_ULFRCO:
592 #if defined( CMU_LFACLKSEL_LFA_PLFRCO )
593 case _CMU_LFACLKSEL_LFA_PLFRCO:
598 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
599 case _CMU_LFACLKSEL_LFA_HFCLKLE:
600 ret = ((
CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
601 == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
605 #elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
606 case _CMU_LFBCLKSEL_LFB_HFCLKLE:
607 ret = ((
CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
608 == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
614 case _CMU_LFACLKSEL_LFA_DISABLED:
632 __STATIC_INLINE
void syncReg(uint32_t mask)
641 while (
CMU->SYNCBUSY & mask)
647 #if defined(USB_PRESENT)
655 static uint32_t usbCClkGet(
void)
690 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
707 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
748 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
749 case cmuAUXHFRCOBand_28MHz:
750 tuning = (
DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
751 >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
761 CMU->AUXHFRCOCTRL = (
CMU->AUXHFRCOCTRL &
771 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
782 static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
787 case cmuAUXHFRCOFreq_1M0Hz:
788 case cmuAUXHFRCOFreq_2M0Hz:
789 case cmuAUXHFRCOFreq_4M0Hz:
792 case cmuAUXHFRCOFreq_7M0Hz:
795 case cmuAUXHFRCOFreq_13M0Hz:
798 case cmuAUXHFRCOFreq_16M0Hz:
801 case cmuAUXHFRCOFreq_19M0Hz:
804 case cmuAUXHFRCOFreq_26M0Hz:
807 case cmuAUXHFRCOFreq_32M0Hz:
810 case cmuAUXHFRCOFreq_38M0Hz:
820 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
835 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
848 freqCal = CMU_AUXHFRCODevinfoGet(setFreq);
849 EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
850 auxHfrcoFreq = setFreq;
859 case cmuAUXHFRCOFreq_1M0Hz:
860 freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
861 | CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
864 case cmuAUXHFRCOFreq_2M0Hz:
865 freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
866 | CMU_AUXHFRCOCTRL_CLKDIV_DIV2;
869 case cmuAUXHFRCOFreq_4M0Hz:
870 freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
871 | CMU_AUXHFRCOCTRL_CLKDIV_DIV1;
877 CMU->AUXHFRCOCTRL = freqCal;
937 CMU->CALCNT = HFCycles;
942 #if defined( CMU_STATUS_CALRDY )
958 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
989 uint32_t calCtrl =
CMU->CALCTRL
1024 CMU->CALCNT = downCycles;
1054 CMU->CALCTRL = calCtrl;
1076 #if defined( CMU_CALCTRL_CONT )
1079 #if defined( CMU_STATUS_CALRDY )
1114 #if defined( _SILICON_LABS_32B_SERIES_1 )
1115 return 1 + (uint32_t)CMU_ClockPrescGet(clock);
1117 #elif defined( _SILICON_LABS_32B_SERIES_0 )
1122 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1126 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1127 case CMU_HFCLKDIV_REG:
1133 case CMU_HFPERCLKDIV_REG:
1140 case CMU_HFCORECLKDIV_REG:
1147 case CMU_LFAPRESC0_REG:
1156 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1157 case cmuClock_LETIMER0:
1159 >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
1164 #if defined(_CMU_LFAPRESC0_LCD_MASK)
1165 case cmuClock_LCDpre:
1167 >> _CMU_LFAPRESC0_LCD_SHIFT)
1173 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
1174 case cmuClock_LESENSE:
1176 >> _CMU_LFAPRESC0_LESENSE_SHIFT);
1188 case CMU_LFBPRESC0_REG:
1191 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1199 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1200 case cmuClock_LEUART1:
1202 >> _CMU_LFBPRESC0_LEUART1_SHIFT);
1246 #if defined( _SILICON_LABS_32B_SERIES_1 )
1247 CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
1249 #elif defined( _SILICON_LABS_32B_SERIES_0 )
1254 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1258 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1259 case CMU_HFCLKDIV_REG:
1263 flashWaitStateMax();
1274 flashWaitStateControl(freq);
1278 case CMU_HFPERCLKDIV_REG:
1286 case CMU_HFCORECLKDIV_REG:
1290 flashWaitStateMax();
1292 #if defined( CMU_MAX_FREQ_HFLE )
1299 CMU->HFCORECLKDIV = (
CMU->HFCORECLKDIV
1308 flashWaitStateControl(freq);
1311 case CMU_LFAPRESC0_REG:
1327 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1328 case cmuClock_LETIMER0:
1337 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
1338 | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
1342 #if defined(LCD_PRESENT)
1343 case cmuClock_LCDpre:
1352 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
1354 << _CMU_LFAPRESC0_LCD_SHIFT);
1358 #if defined(LESENSE_PRESENT)
1359 case cmuClock_LESENSE:
1368 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
1369 | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
1379 case CMU_LFBPRESC0_REG:
1382 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1397 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1398 case cmuClock_LEUART1:
1407 CMU->LFBPRESC0 = (
CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
1408 | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
1455 volatile uint32_t *reg;
1460 switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
1462 #if defined( _CMU_CTRL_HFPERCLKEN_MASK )
1463 case CMU_CTRL_EN_REG:
1468 #if defined( _CMU_HFCORECLKEN0_MASK )
1469 case CMU_HFCORECLKEN0_EN_REG:
1470 reg = &
CMU->HFCORECLKEN0;
1471 #if defined( CMU_MAX_FREQ_HFLE )
1477 #if defined( _CMU_HFBUSCLKEN0_MASK )
1478 case CMU_HFBUSCLKEN0_EN_REG:
1479 reg = &
CMU->HFBUSCLKEN0;
1483 #if defined( _CMU_HFPERCLKDIV_MASK )
1484 case CMU_HFPERCLKDIV_EN_REG:
1485 reg = &
CMU->HFPERCLKDIV;
1489 case CMU_HFPERCLKEN0_EN_REG:
1490 reg = &
CMU->HFPERCLKEN0;
1493 case CMU_LFACLKEN0_EN_REG:
1494 reg = &
CMU->LFACLKEN0;
1498 case CMU_LFBCLKEN0_EN_REG:
1499 reg = &
CMU->LFBCLKEN0;
1503 #if defined( _CMU_LFCCLKEN0_MASK )
1504 case CMU_LFCCLKEN0_EN_REG:
1505 reg = &
CMU->LFCCLKEN0;
1510 #if defined( _CMU_LFECLKEN0_MASK )
1511 case CMU_LFECLKEN0_EN_REG:
1512 reg = &
CMU->LFECLKEN0;
1513 sync = CMU_SYNCBUSY_LFECLKEN0;
1517 case CMU_PCNT_EN_REG:
1518 reg = &
CMU->PCNTCTRL;
1527 bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
1554 switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
1556 case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1560 case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1563 #if defined( _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK )
1567 #if defined( _CMU_HFPERPRESC_PRESC_MASK )
1568 ret /= 1U + ((
CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
1569 >> _CMU_HFPERPRESC_PRESC_SHIFT);
1573 #if defined( _SILICON_LABS_32B_SERIES_1 )
1574 #if defined( CRYPTO_PRESENT ) \
1575 || defined( LDMA_PRESENT ) \
1576 || defined( GPCRC_PRESENT ) \
1577 || defined( PRS_PRESENT ) \
1578 || defined( GPIO_PRESENT )
1579 case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1584 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1586 ret /= 1U + ((
CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
1587 >> _CMU_HFCOREPRESC_PRESC_SHIFT);
1590 case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1592 ret /= 1U + ((
CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
1593 >> _CMU_HFEXPPRESC_PRESC_SHIFT);
1597 #if defined( _SILICON_LABS_32B_SERIES_0 )
1598 #if defined( AES_PRESENT ) \
1599 || defined( DMA_PRESENT ) \
1600 || defined( EBI_PRESENT ) \
1601 || defined( USB_PRESENT )
1602 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1609 case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1613 #if defined( _CMU_LFACLKEN0_RTC_MASK )
1614 case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1621 #if defined( _CMU_LFECLKEN0_RTCC_MASK )
1622 case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1623 ret = lfClkGet(cmuClock_LFE);
1627 #if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
1628 case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1630 #if defined( _SILICON_LABS_32B_SERIES_0 )
1631 ret >>= (
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1632 >> _CMU_LFAPRESC0_LETIMER0_SHIFT;
1633 #elif defined( _SILICON_LABS_32B_SERIES_1 )
1635 >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
1640 #if defined( _CMU_LFACLKEN0_LCD_MASK )
1641 case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1643 ret >>= ((
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1644 >> _CMU_LFAPRESC0_LCD_SHIFT)
1648 case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1650 ret >>= (
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1651 >> _CMU_LFAPRESC0_LCD_SHIFT;
1652 ret /= 1U + ((
CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
1653 >> _CMU_LCDCTRL_FDIV_SHIFT);
1657 #if defined( _CMU_LFACLKEN0_LESENSE_MASK )
1658 case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1660 ret >>= (
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1661 >> _CMU_LFAPRESC0_LESENSE_SHIFT;
1665 case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1669 #if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
1670 case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1672 #if defined( _SILICON_LABS_32B_SERIES_0 )
1675 #elif defined( _SILICON_LABS_32B_SERIES_1 )
1682 #if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
1683 case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1685 #if defined( _SILICON_LABS_32B_SERIES_0 )
1686 ret >>= (
CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1687 >> _CMU_LFBPRESC0_LEUART1_SHIFT;
1688 #elif defined( _SILICON_LABS_32B_SERIES_1 )
1690 >> _CMU_LFBPRESC0_LEUART1_SHIFT);
1695 #if defined( _CMU_LFBCLKEN0_CSEN_MASK )
1696 case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1699 >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4);
1703 #if defined( _SILICON_LABS_32B_SERIES_1 )
1704 case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1705 ret = lfClkGet(cmuClock_LFE);
1709 case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1713 case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1717 #if defined(USB_PRESENT)
1718 case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1733 #if defined( _SILICON_LABS_32B_SERIES_1 )
1752 prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1756 case CMU_HFPRESC_REG:
1757 ret = ((
CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
1758 >> _CMU_HFPRESC_PRESC_SHIFT);
1761 case CMU_HFEXPPRESC_REG:
1762 ret = ((
CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
1763 >> _CMU_HFEXPPRESC_PRESC_SHIFT);
1766 case CMU_HFCLKLEPRESC_REG:
1767 ret = ((
CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
1768 >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
1771 case CMU_HFPERPRESC_REG:
1772 ret = ((
CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
1773 >> _CMU_HFPERPRESC_PRESC_SHIFT);
1776 case CMU_HFCOREPRESC_REG:
1777 ret = ((
CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
1778 >> _CMU_HFCOREPRESC_PRESC_SHIFT);
1781 case CMU_LFAPRESC0_REG:
1784 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
1785 case cmuClock_LETIMER0:
1786 ret = (((
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1787 >> _CMU_LFAPRESC0_LETIMER0_SHIFT));
1793 #if defined( _CMU_LFAPRESC0_LESENSE_MASK )
1794 case cmuClock_LESENSE:
1795 ret = (((
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1796 >> _CMU_LFAPRESC0_LESENSE_SHIFT));
1809 case CMU_LFBPRESC0_REG:
1812 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
1821 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
1822 case cmuClock_LEUART1:
1823 ret = (((
CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1824 >> _CMU_LFBPRESC0_LEUART1_SHIFT));
1830 #if defined( _CMU_LFBPRESC0_CSEN_MASK )
1831 case cmuClock_CSEN_LF:
1832 ret = (((
CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK)
1833 >> _CMU_LFBPRESC0_CSEN_SHIFT));
1846 case CMU_LFEPRESC0_REG:
1849 #if defined( RTCC_PRESENT )
1853 ret = _CMU_LFEPRESC0_RTCC_DIV1;
1875 #if defined( _SILICON_LABS_32B_SERIES_1 )
1900 prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1904 case CMU_HFPRESC_REG:
1905 EFM_ASSERT(presc < 32U);
1908 flashWaitStateMax();
1909 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
1911 CMU->HFPRESC = (
CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
1912 | (presc << _CMU_HFPRESC_PRESC_SHIFT);
1917 flashWaitStateControl(freq);
1921 case CMU_HFEXPPRESC_REG:
1922 EFM_ASSERT(presc < 32U);
1924 CMU->HFEXPPRESC = (
CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
1925 | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
1928 case CMU_HFCLKLEPRESC_REG:
1929 EFM_ASSERT(presc < 2U);
1933 CMU->HFPRESC = (
CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
1934 | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
1937 case CMU_HFPERPRESC_REG:
1938 EFM_ASSERT(presc < 512U);
1940 CMU->HFPERPRESC = (
CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
1941 | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
1944 case CMU_HFCOREPRESC_REG:
1945 EFM_ASSERT(presc < 512U);
1948 flashWaitStateMax();
1949 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
1951 CMU->HFCOREPRESC = (
CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
1952 | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
1957 flashWaitStateControl(freq);
1961 case CMU_LFAPRESC0_REG:
1964 #if defined( RTC_PRESENT )
1966 EFM_ASSERT(presc <= 32768U);
1969 presc = CMU_PrescToLog2(presc);
1979 #if defined( RTCC_PRESENT )
1981 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
1983 EFM_ASSERT(presc <= 0U);
1986 syncReg(CMU_SYNCBUSY_LFEPRESC0);
1988 CMU->LFEPRESC0 = (
CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
1989 | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
1991 EFM_ASSERT(presc <= 32768U);
1994 presc = CMU_PrescToLog2(presc);
1999 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
2000 | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
2005 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
2006 case cmuClock_LETIMER0:
2007 EFM_ASSERT(presc <= 32768U);
2010 presc = CMU_PrescToLog2(presc);
2015 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
2016 | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
2020 #if defined( _CMU_LFAPRESC0_LESENSE_MASK )
2021 case cmuClock_LESENSE:
2022 EFM_ASSERT(presc <= 8);
2025 presc = CMU_PrescToLog2(presc);
2030 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
2031 | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT);
2041 case CMU_LFBPRESC0_REG:
2044 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
2046 EFM_ASSERT(presc <= 8U);
2049 presc = CMU_PrescToLog2(presc);
2059 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
2060 case cmuClock_LEUART1:
2061 EFM_ASSERT(presc <= 8U);
2064 presc = CMU_PrescToLog2(presc);
2069 CMU->LFBPRESC0 = (
CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
2070 | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
2074 #if defined( _CMU_LFBPRESC0_CSEN_MASK )
2075 case cmuClock_CSEN_LF:
2076 EFM_ASSERT((presc <= 127U) && (presc >= 15U));
2080 presc = CMU_PrescToLog2(presc) - 4;
2085 CMU->LFBPRESC0 = (
CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK)
2086 | (presc << _CMU_LFBPRESC0_CSEN_SHIFT);
2096 case CMU_LFEPRESC0_REG:
2099 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
2101 EFM_ASSERT(presc <= 0U);
2104 syncReg(CMU_SYNCBUSY_LFEPRESC0);
2106 CMU->LFEPRESC0 = (
CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
2107 | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
2151 selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2155 case CMU_HFCLKSEL_REG:
2156 #if defined( _CMU_HFCLKSTATUS_MASK )
2157 switch (
CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
2159 case CMU_HFCLKSTATUS_SELECTED_LFXO:
2163 case CMU_HFCLKSTATUS_SELECTED_LFRCO:
2167 case CMU_HFCLKSTATUS_SELECTED_HFXO:
2197 #if defined( CMU_STATUS_USHFRCODIV2SEL )
2210 #if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFACLKSEL_MASK )
2211 case CMU_LFACLKSEL_REG:
2212 #if defined( _CMU_LFCLKSEL_MASK )
2223 #if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
2230 #if defined( CMU_LFCLKSEL_LFAE )
2242 #elif defined( _CMU_LFACLKSEL_MASK )
2243 switch (
CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
2245 case CMU_LFACLKSEL_LFA_LFRCO:
2249 case CMU_LFACLKSEL_LFA_LFXO:
2253 case CMU_LFACLKSEL_LFA_ULFRCO:
2257 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2258 case CMU_LFACLKSEL_LFA_HFCLKLE:
2263 #if defined( CMU_LFACLKSEL_LFA_PLFRCO )
2264 case CMU_LFACLKSEL_LFA_PLFRCO:
2265 ret = cmuSelect_PLFRCO;
2277 #if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFBCLKSEL_MASK )
2278 case CMU_LFBCLKSEL_REG:
2279 #if defined( _CMU_LFCLKSEL_MASK )
2290 #if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
2296 #if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
2297 case CMU_LFCLKSEL_LFB_HFCLKLE:
2303 #if defined( CMU_LFCLKSEL_LFBE )
2315 #elif defined( _CMU_LFBCLKSEL_MASK )
2316 switch (
CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
2318 case CMU_LFBCLKSEL_LFB_LFRCO:
2322 case CMU_LFBCLKSEL_LFB_LFXO:
2326 case CMU_LFBCLKSEL_LFB_ULFRCO:
2330 case CMU_LFBCLKSEL_LFB_HFCLKLE:
2334 #if defined( CMU_LFBCLKSEL_LFB_PLFRCO )
2335 case CMU_LFBCLKSEL_LFB_PLFRCO:
2336 ret = cmuSelect_PLFRCO;
2348 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2349 case CMU_LFCCLKSEL_REG:
2367 #if defined( _CMU_LFECLKSEL_LFE_MASK )
2368 case CMU_LFECLKSEL_REG:
2369 switch (
CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
2371 case CMU_LFECLKSEL_LFE_LFRCO:
2375 case CMU_LFECLKSEL_LFE_LFXO:
2379 case CMU_LFECLKSEL_LFE_ULFRCO:
2383 #if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
2384 case CMU_LFECLKSEL_LFE_HFCLKLE:
2389 #if defined( CMU_LFECLKSEL_LFE_PLFRCO )
2390 case CMU_LFECLKSEL_LFE_PLFRCO:
2391 ret = cmuSelect_PLFRCO;
2402 case CMU_DBGCLKSEL_REG:
2403 #if defined( _CMU_DBGCLKSEL_DBG_MASK )
2404 switch (
CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
2406 case CMU_DBGCLKSEL_DBG_HFCLK:
2410 case CMU_DBGCLKSEL_DBG_AUXHFRCO:
2415 #elif defined( _CMU_CTRL_DBGCLK_MASK )
2416 switch(
CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
2418 case CMU_CTRL_DBGCLK_AUXHFRCO:
2422 case CMU_CTRL_DBGCLK_HFCLK:
2431 #if defined( USB_PRESENT )
2432 case CMU_USBCCLKSEL_REG:
2435 #
if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2436 | CMU_STATUS_USBCHFCLKSEL
2443 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2444 case CMU_STATUS_USBCHFCLKSEL:
2449 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2528 #if defined( _SILICON_LABS_32B_SERIES_1 )
2529 volatile uint32_t *selReg = NULL;
2531 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2532 uint32_t lfExtended = 0;
2535 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
2536 uint32_t vScaleFrequency = 0;
2550 if (vScaleFrequency != 0)
2552 EMU_VScaleEM01ByClock(vScaleFrequency,
false);
2557 selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2561 case CMU_HFCLKSEL_REG:
2565 #if defined( _SILICON_LABS_32B_SERIES_1 )
2566 select = CMU_HFCLKSEL_HF_LFXO;
2567 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2574 #if defined( _SILICON_LABS_32B_SERIES_1 )
2575 select = CMU_HFCLKSEL_HF_LFRCO;
2576 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2583 #if defined( CMU_HFCLKSEL_HF_HFXO )
2584 select = CMU_HFCLKSEL_HF_HFXO;
2585 #elif defined( CMU_CMD_HFCLKSEL_HFXO )
2589 #if defined( CMU_MAX_FREQ_HFLE )
2592 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
2594 #if defined( CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ )
2599 | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ;
2604 | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
2610 #if defined( _SILICON_LABS_32B_SERIES_1 )
2611 select = CMU_HFCLKSEL_HF_HFRCO;
2612 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2616 #if defined( CMU_MAX_FREQ_HFLE )
2619 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
2623 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
2630 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
2646 flashWaitStateMax();
2648 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
2650 if (vScaleFrequency != 0)
2657 #if defined( _CMU_HFCLKSEL_MASK )
2658 CMU->HFCLKSEL = select;
2662 #if defined( CMU_MAX_FREQ_HFLE )
2673 flashWaitStateControl(freq);
2675 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
2678 if (vScaleFrequency == 0)
2680 EMU_VScaleEM01ByClock(0,
true);
2685 #if defined( _SILICON_LABS_32B_SERIES_1 )
2686 case CMU_LFACLKSEL_REG:
2687 selReg = (selReg == NULL) ? &
CMU->LFACLKSEL : selReg;
2688 #
if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2694 case CMU_LFECLKSEL_REG:
2695 selReg = (selReg == NULL) ? &
CMU->LFECLKSEL : selReg;
2696 #
if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
2702 case CMU_LFBCLKSEL_REG:
2703 selReg = (selReg == NULL) ? &
CMU->LFBCLKSEL : selReg;
2707 tmp = _CMU_LFACLKSEL_LFA_DISABLED;
2713 tmp = _CMU_LFACLKSEL_LFA_LFXO;
2719 tmp = _CMU_LFACLKSEL_LFA_LFRCO;
2726 tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
2731 tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
2734 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
2735 case cmuSelect_PLFRCO:
2738 tmp = _CMU_LFACLKSEL_LFA_PLFRCO;
2749 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2750 case CMU_LFACLKSEL_REG:
2751 case CMU_LFBCLKSEL_REG:
2771 #if defined( CMU_MAX_FREQ_HFLE )
2774 setHfLeConfig(freq, CMU_MAX_FREQ_HFLE);
2781 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2796 if (selRegId == CMU_LFACLKSEL_REG)
2798 #if defined( _CMU_LFCLKSEL_LFAE_MASK )
2799 CMU->LFCLKSEL = (
CMU->LFCLKSEL
2810 #if defined( _CMU_LFCLKSEL_LFBE_MASK )
2811 CMU->LFCLKSEL = (
CMU->LFCLKSEL
2822 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2823 case CMU_LFCCLKSEL_REG:
2855 #if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
2856 case CMU_DBGCLKSEL_REG:
2859 #if defined( CMU_DBGCLKSEL_DBG )
2862 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
2867 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
2871 #if defined( CMU_CTRL_DBGCLK )
2874 CMU->CTRL = (
CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2875 | CMU_CTRL_DBGCLK_AUXHFRCO;
2880 CMU->CTRL = (
CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2881 | CMU_CTRL_DBGCLK_HFCLK;
2893 #if defined( USB_PRESENT )
2894 case CMU_USBCCLKSEL_REG:
2925 #if defined( CMU_STATUS_USBCHFCLKSEL )
2929 CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
2931 while((
CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
2937 #if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
2965 #if defined( CMU_MAX_FREQ_HFLE )
3011 while (
CMU->SYNCBUSY)
3024 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
3040 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
3083 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
3084 case cmuHFRCOBand_28MHz:
3085 tuning = (
DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
3086 >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
3100 flashWaitStateMax();
3104 CMU->HFRCOCTRL = (
CMU->HFRCOCTRL &
3114 flashWaitStateControl(freq);
3117 #if defined(CMU_MAX_FREQ_HFLE)
3126 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
3137 static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
3142 case cmuHFRCOFreq_1M0Hz:
3143 case cmuHFRCOFreq_2M0Hz:
3144 case cmuHFRCOFreq_4M0Hz:
3147 case cmuHFRCOFreq_7M0Hz:
3150 case cmuHFRCOFreq_13M0Hz:
3153 case cmuHFRCOFreq_16M0Hz:
3156 case cmuHFRCOFreq_19M0Hz:
3159 case cmuHFRCOFreq_26M0Hz:
3162 case cmuHFRCOFreq_32M0Hz:
3165 case cmuHFRCOFreq_38M0Hz:
3183 return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
3200 freqCal = CMU_HFRCODevinfoGet(setFreq);
3201 EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
3202 SystemHfrcoFreq = (uint32_t)setFreq;
3207 flashWaitStateMax();
3215 EFM_ASSERT(freqCal != UINT_MAX);
3220 case cmuHFRCOFreq_1M0Hz:
3221 freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3222 | CMU_HFRCOCTRL_CLKDIV_DIV4;
3225 case cmuHFRCOFreq_2M0Hz:
3226 freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3227 | CMU_HFRCOCTRL_CLKDIV_DIV2;
3230 case cmuHFRCOFreq_4M0Hz:
3231 freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3232 | CMU_HFRCOCTRL_CLKDIV_DIV1;
3244 setHfLeConfig(setFreq, CMU_MAX_FREQ_HFLE);
3247 CMU->HFRCOCTRL = freqCal;
3255 EFM_ASSERT(sysFreq <= (uint32_t)setFreq);
3256 EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
3257 EFM_ASSERT(setFreq == SystemHfrcoFreq);
3258 flashWaitStateControl(sysFreq);
3265 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
3266 EMU_VScaleEM01ByClock(0,
true);
3271 #if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
3301 EFM_ASSERT(delay <= 31);
3310 #if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
3330 void CMU_HFXOAutostartEnable(uint32_t userSel,
3332 bool enEM0EM1StartSel)
3338 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
3339 userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK;
3344 hfxoCtrl =
CMU->HFXOCTRL & ~( userSel
3345 | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
3346 | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
3349 | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
3350 | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
3353 if (userSel || enEM0EM1StartSel)
3356 flashWaitStateControl(hfxoFreq);
3357 setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE);
3362 CMU->HFXOCTRL = hfxoCtrl;
3385 #if defined( _EMU_PWRCTRL_REGPWRSEL_MASK )
3386 EFM_ASSERT(
EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD);
3392 #if defined( _CMU_HFXOCTRL_MASK )
3395 EFM_ASSERT(!(hfxoInit->autoStartEm01
3396 || hfxoInit->autoSelEm01
3397 || hfxoInit->autoStartSelOnRacWakeup));
3399 uint32_t mode = CMU_HFXOCTRL_MODE_XTAL;
3405 mode = CMU_HFXOCTRL_MODE_EXTCLK;
3410 _CMU_HFXOCTRL_LOWPOWER_MASK | _CMU_HFXOCTRL_MODE_MASK,
3411 (hfxoInit->lowPowerMode ? CMU_HFXOCTRL_LOWPOWER : 0) | mode);
3415 #if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK)
3418 _CMU_HFXOCTRL1_PEAKDETTHR_MASK,
3419 hfxoInit->thresholdPeakDetect);
3424 _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
3425 | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK,
3426 (hfxoInit->ctuneStartup
3427 << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
3428 | (hfxoInit->xoCoreBiasTrimStartup
3429 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT));
3432 _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
3433 | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
3434 | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
3435 | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
3436 (hfxoInit->ctuneSteadyState
3437 << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
3438 | (hfxoInit->regIshSteadyState
3439 << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
3440 | (hfxoInit->xoCoreBiasTrimSteadyState
3441 << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
3442 | getRegIshUpperVal(hfxoInit->regIshSteadyState));
3446 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
3447 | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
3448 | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
3449 | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
3450 (hfxoInit->timeoutShuntOptimization
3451 << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
3452 | (hfxoInit->timeoutPeakDetect
3453 << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
3454 | (hfxoInit->timeoutSteady
3455 << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
3456 | (hfxoInit->timeoutStartup
3457 << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
3481 #if defined( LCD_PRESENT )
3482 return (
CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
3504 #if defined( LCD_PRESENT )
3508 if (
CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
3513 div <<= _CMU_LCDCTRL_FDIV_SHIFT;
3514 div &= _CMU_LCDCTRL_FDIV_MASK;
3515 CMU->LCDCTRL = (
CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div;
3542 #if defined( _CMU_LFXOCTRL_MASK )
3544 _CMU_LFXOCTRL_TUNING_MASK
3545 | _CMU_LFXOCTRL_GAIN_MASK
3546 | _CMU_LFXOCTRL_TIMEOUT_MASK
3547 | _CMU_LFXOCTRL_MODE_MASK,
3548 (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)
3549 | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)
3550 | (lfxoInit->
timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT)
3551 | (lfxoInit->
mode << _CMU_LFXOCTRL_MODE_SHIFT));
3553 bool cmuBoost = (lfxoInit->
boost & 0x2);
3563 #if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
3564 bool emuReduce = (lfxoInit->
boost & 0x1);
3597 #if defined( _SILICON_LABS_32B_SERIES_1 )
3600 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
3601 uint32_t hfxoTrimStatus;
3613 #if defined( _SILICON_LABS_32B_SERIES_1 )
3622 #if defined( _SILICON_LABS_32B_SERIES_1 )
3631 #if defined( _SILICON_LABS_32B_SERIES_1 )
3640 #if defined( _SILICON_LABS_32B_SERIES_1 )
3649 #if defined( _SILICON_LABS_32B_SERIES_1 )
3654 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
3659 #if defined( _SILICON_LABS_32B_SERIES_1 )
3665 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
3667 enBit = CMU_OSCENCMD_PLFRCOEN;
3668 disBit = CMU_OSCENCMD_PLFRCODIS;
3669 rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT;
3670 ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT;
3684 #if defined( _CMU_HFXOCTRL_MASK )
3685 bool firstHfxoEnable =
false;
3691 ((
CMU->HFXOCTRL & (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK))
3692 == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
3694 firstHfxoEnable =
true;
3697 if ((
CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_EXTCLK)
3699 CMU->HFXOCTRL = (
CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
3700 | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
3704 CMU->OSCENCMD = enBit;
3706 #if defined( _SILICON_LABS_32B_SERIES_1 )
3717 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
3720 if ((
CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) == CMU_HFXOCTRL_MODE_EXTCLK)
3723 CMU_OscillatorTuningOptimize(
cmuOsc_HFXO, cmuHFXOTuningMode_ShuntCommand,
true);
3728 CMU_OscillatorTuningWait(
cmuOsc_HFXO, cmuHFXOTuningMode_Auto);
3738 CMU->OSCENCMD = enBit;
3746 CMU->OSCENCMD = disBit;
3748 #if defined( _SILICON_LABS_32B_SERIES_1 )
3793 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3795 ret =
CMU->HFXOTRIMSTATUS & ( _CMU_HFXOTRIMSTATUS_REGISH_MASK
3796 | _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK);
3832 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3833 uint32_t regIshUpper;
3842 #if defined( _SILICON_LABS_32B_SERIES_1 )
3853 #if defined( _SILICON_LABS_32B_SERIES_1 )
3866 #if defined( _SILICON_LABS_32B_SERIES_1 )
3875 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3883 CMU->HFXOCTRL = (
CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
3884 | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
3886 regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK)
3887 >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT);
3890 _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
3891 | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
3892 | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
3903 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3919 CMU_HFXOTuningMode_TypeDef mode)
3928 == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD)
3930 waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
3937 case cmuHFXOTuningMode_ShuntCommand:
3938 waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY;
3941 case cmuHFXOTuningMode_Auto:
3943 case cmuHFXOTuningMode_PeakShuntCommand:
3944 waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
3952 while ((
CMU->STATUS & waitFlags) != waitFlags);
3955 if (waitFlags & CMU_STATUS_HFXOPEAKDETRDY)
3957 return (
CMU->IF & CMU_IF_HFXOPEAKDETERR ?
true :
false);
3983 CMU_HFXOTuningMode_TypeDef mode,
3992 CMU->IFC = CMU_IFC_HFXOPEAKDETERR;
3997 return CMU_OscillatorTuningWait(osc, mode);
4025 #if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
4030 #if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
4032 setting =
CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
4035 #if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
4037 setting =
CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
4047 return (setting ?
true :
false);
4063 #if defined( PCNT_PRESENT )
4064 uint32_t setting = 0;
4082 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
4098 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
4109 uint32_t fineTuning;
4122 fineTuning = (
DEVINFO->USHFRCOCAL0
4130 fineTuning = (
DEVINFO->USHFRCOCAL0
Clock management unit (CMU) API.
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT
#define _CMU_LFCLKSEL_LFC_LFXO
#define _CMU_LFCLKSEL_LFA_MASK
#define _CMU_LFCLKSEL_LFBE_MASK
#define CMU_CALCTRL_DOWNSEL_LFRCO
#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK
#define CMU_OSCENCMD_LFXODIS
#define _CMU_LFRCOCTRL_TUNING_SHIFT
#define CMU_LFCLKSEL_LFC_LFRCO
#define CMU_LFCLKSEL_LFB_LFXO
uint32_t SystemCoreClockGet(void)
Get the current core clock frequency.
#define CMU_CALCTRL_UPSEL_HFRCO
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
#define _CMU_USHFRCOTUNE_FINETUNING_MASK
#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT
void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
Set AUXHFRCO band and the tuning value based on the value in the calibration table made during produc...
CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
Get USHFRCO band in use.
#define _CMU_LFCLKSEL_LFBE_SHIFT
#define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT
#define _DEVINFO_HFRCOCAL0_BAND1_MASK
Emlib peripheral API "assert" implementation.
#define _CMU_HFCORECLKEN0_LE_SHIFT
#define CMU_AUXHFRCOCTRL_BAND_11MHZ
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT
#define _CMU_HFRCOCTRL_BAND_SHIFT
#define _CMU_USHFRCOCONF_BAND_SHIFT
#define CMU_CMD_HFCLKSEL_HFXO
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
#define _CMU_CTRL_LFXOBOOST_MASK
RAM and peripheral bit-field set and clear API.
CMU_LFXOBoost_TypeDef boost
#define _ROMTABLE_PID3_REVMINORLSB_MASK
#define _CMU_CALCNT_CALCNT_MASK
#define CMU_LFCLKSEL_LFC_LFXO
#define CMU_AUXHFRCOCTRL_BAND_14MHZ
#define _CMU_USHFRCOTUNE_FINETUNING_SHIFT
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK
#define _CMU_CTRL_LFXOTIMEOUT_MASK
#define CMU_STATUS_USBCUSHFRCOSEL
#define _CMU_CALCTRL_DOWNSEL_MASK
#define _CMU_LFBPRESC0_LEUART0_SHIFT
#define _CMU_CALCTRL_CONT_SHIFT
#define _CMU_HFRCOCTRL_TUNING_SHIFT
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
#define _CMU_LFAPRESC0_RTC_SHIFT
#define MSC_READCTRL_MODE_WS0
#define _CMU_LFRCOCTRL_TUNING_MASK
#define _CMU_LFCLKSEL_LFA_LFXO
#define CMU_SYNCBUSY_LFBPRESC0
#define CMU_SYNCBUSY_LFAPRESC0
#define _CMU_AUXHFRCOCTRL_BAND_SHIFT
#define CMU_LFCLKSEL_LFA_LFRCO
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
#define _CMU_STATUS_LFRCOENS_SHIFT
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
#define _CMU_CALCNT_CALCNT_SHIFT
#define _CMU_LFCLKSEL_LFC_LFRCO
#define CMU_STATUS_LFXOSEL
void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
Set HFXO control registers.
#define CMU_STATUS_USHFRCODIV2SEL
#define CMU_CMD_HFCLKSEL_USHFRCODIV2
#define _CMU_CTRL_LFXOTIMEOUT_SHIFT
#define _CMU_STATUS_USHFRCORDY_SHIFT
#define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT
#define _CMU_STATUS_USHFRCOENS_SHIFT
#define _CMU_CTRL_HFXOMODE_SHIFT
#define _CMU_CTRL_HFXOTIMEOUT_SHIFT
#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT
uint32_t CMU_ClkDiv_TypeDef
General purpose utilities.
#define _CMU_CTRL_HFCLKDIV_SHIFT
#define CMU_OSCENCMD_LFXOEN
#define _CMU_HFRCOCTRL_BAND_MASK
uint32_t CMU_HFRCOStartupDelayGet(void)
Get the HFRCO startup delay.
#define CMU_AUXHFRCOCTRL_BAND_7MHZ
#define CMU_STATUS_HFXOSEL
#define CMU_CMD_HFCLKSEL_LFRCO
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
#define _CMU_HFRCOCTRL_TUNING_MASK
#define CMU_OSCENCMD_HFRCOEN
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
#define _ROMTABLE_PID2_REVMINORMSB_MASK
#define _CMU_CTRL_HFXOBOOST_SHIFT
#define _CMU_CTRL_HFXOGLITCHDETEN_MASK
#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2
#define _DEVINFO_HFRCOCAL0_BAND11_MASK
#define _CMU_CTRL_HFXOBUFCUR_MASK
#define CMU_CALCTRL_DOWNSEL_HFXO
#define _CMU_CTRL_LFXOMODE_MASK
__STATIC_INLINE uint8_t SYSTEM_GetProdRev(void)
Get the production revision for this part.
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
#define _CMU_STATUS_HFRCOENS_SHIFT
#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT
uint32_t SystemLFXOClockGet(void)
Get low frequency crystal oscillator clock frequency for target system.
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
Get family identifier of the MCU.
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)
Configure clock calibration.
#define _DEVINFO_HFRCOCAL1_BAND21_MASK
#define _MSC_READCTRL_MODE_MASK
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT
#define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK
#define _CMU_CTRL_HFXOMODE_MASK
#define _CMU_CALCTRL_UPSEL_MASK
#define CMU_CALCTRL_UPSEL_AUXHFRCO
#define _CMU_HFRCOCTRL_SUDELAY_MASK
#define _CMU_STATUS_LFXORDY_SHIFT
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
Get HFRCO band in use.
#define _DEVINFO_HFRCOCAL0_BAND14_MASK
#define _CMU_LFCLKSEL_LFC_MASK
uint32_t SystemHFClockGet(void)
Get the current HFCLK frequency.
#define CMU_OSCENCMD_AUXHFRCODIS
#define CMU_SYNCBUSY_LFBCLKEN0
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
#define _CMU_LFCLKSEL_LFA_DISABLED
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
#define _CMU_STATUS_HFRCORDY_SHIFT
uint32_t SystemHFXOClockGet(void)
Get high frequency crystal oscillator clock frequency for target system.
#define _CMU_CTRL_HFCLKDIV_MASK
#define CMU_STATUS_USBCLFRCOSEL
#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT
#define CMU_STATUS_HFXOENS
#define _CMU_STATUS_AUXHFRCORDY_SHIFT
#define _CMU_USHFRCOCONF_BAND_MASK
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
#define _CMU_USHFRCOCTRL_TUNING_SHIFT
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
#define CMU_LFCLKSEL_LFA_LFXO
#define CMU_STATUS_LFRCOSEL
#define CMU_OSCENCMD_USHFRCOEN
#define _CMU_LFAPRESC0_RTC_MASK
#define _DEVINFO_HFRCOCAL0_BAND7_MASK
uint32_t SystemULFRCOClockGet(void)
Get ultra low frequency RC oscillator clock frequency for target system.
void CMU_HFRCOStartupDelaySet(uint32_t delay)
Set the HFRCO startup delay.
#define CMU_OSCENCMD_LFRCOEN
#define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT
#define CMU_OSCENCMD_HFXOEN
#define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT
#define _CMU_STATUS_LFXOENS_SHIFT
#define _CMU_LFBPRESC0_LEUART0_MASK
uint32_t SystemMaxCoreClockGet(void)
Get the maximum core clock frequency.
#define _CMU_LFCLKSEL_LFB_SHIFT
#define _CMU_CTRL_LFXOBOOST_SHIFT
#define CMU_OSCENCMD_HFXODIS
#define CMU_AUXHFRCOCTRL_BAND_1MHZ
#define CMU_CMD_USBCCLKSEL_USHFRCO
#define _CMU_CTRL_HFXOBOOST_MASK
#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2
__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, uint32_t mask)
Perform a peripheral register masked read.
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT
uint32_t SystemLFRCOClockGet(void)
Get low frequency RC oscillator clock frequency for target system.
Energy management unit (EMU) peripheral API.
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT
#define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT
#define CMU_OSCENCMD_HFRCODIS
#define _CMU_LFCLKSEL_LFB_MASK
#define _CMU_HFRCOCTRL_SUDELAY_SHIFT
#define CMU_OSCENCMD_USHFRCODIS
#define CMU_CALCTRL_DOWNSEL_LFXO
#define _CMU_AUXHFRCOCTRL_BAND_MASK
#define _CMU_AUXHFRCOCTRL_TUNING_MASK
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
#define _CMU_CTRL_HFXOTIMEOUT_MASK
#define CMU_SYNCBUSY_LFACLKEN0
#define _CMU_STATUS_LFRCORDY_SHIFT
#define CMU_CALCTRL_UPSEL_LFRCO
#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK
#define _CMU_STATUS_CALBSY_SHIFT
#define MSC_READCTRL_MODE_WS1
#define SL_MIN(a, b)
Macro for getting minimum value. No sideeffects, a and b are evaluated once only. ...
#define _CMU_LFCLKSEL_LFA_SHIFT
#define CMU_FREEZE_REGFREEZE
#define CMU_CMD_HFCLKSEL_HFRCO
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT
#define CMU_AUXHFRCOCTRL_BAND_21MHZ
#define _ROMTABLE_PID0_REVMAJOR_MASK
#define CMU_CALCTRL_UPSEL_LFXO
#define _CMU_LFCLKSEL_LFAE_MASK
#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK
#define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT
#define _CMU_LFCLKSEL_LFAE_SHIFT
#define CMU_LFCLKSEL_LFB_LFRCO
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define CMU_CMD_USBCCLKSEL_LFRCO
#define _CMU_STATUS_HFXOENS_SHIFT
#define _CMU_LFCLKSEL_LFC_SHIFT
#define CMU_CTRL_HFXOGLITCHDETEN
#define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
#define _CMU_STATUS_HFXORDY_SHIFT
#define CMU_STATUS_USBCLFXOSEL
void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)
Set LFXO control registers.
#define CMU_CMD_HFCLKSEL_LFXO
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
Set HFRCO band and the tuning value based on the value in the calibration table made during productio...
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
#define _CMU_CTRL_LFXOMODE_SHIFT
#define _CMU_STATUS_AUXHFRCOENS_SHIFT
#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK
#define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK
#define _CMU_STATUS_USBCUSHFRCOSEL_MASK
#define _CMU_LFCLKSEL_LFA_LFRCO
#define CMU_CMD_USBCCLKSEL_LFXO
#define CMU_STATUS_HFRCOSEL
void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
Set USHFRCO band to use.
#define CMU_CALCTRL_DOWNSEL_HFRCO
#define _CMU_USHFRCOCTRL_TUNING_MASK
#define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK
#define CMU_OSCENCMD_AUXHFRCOEN
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
#define CMU_SYNCBUSY_LFCCLKEN0
#define CMU_OSCENCMD_LFRCODIS
CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
Get AUXHFRCO band in use.
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
#define CMU_CALCTRL_UPSEL_HFXO
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.
#define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT