EFM32 Happy Gecko Software Documentation
efm32hg-doc-5.1.2
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Core interrupt handling API.
The purpose of the CORE interrupt API is to provide simple and safe means to disable and enable interrupts to protect sections of code.
This is often referred to as "critical sections" and this module provide support for three types of critical sections, each with different interrupt blocking capabilities.
em_core also has an API for manipulating RAM based interrupt vector tables.
The following #defines are used to configure em_core:
// The interrupt priority level used inside ATOMIC sections. #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 // Method used for interrupt disable/enable within ATOMIC sections. #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK
If the default values does not support your needs, they can be overridden by supplying -D compiler flags on the compiler command line or by collecting all macro redefinitions in a file named emlib_config.h and then supplying -DEMLIB_USER_CONFIG on compiler command line.
The primary em_core API is the macro API. The macro API will map to correct CORE functions according to the selected CORE_ATOMIC_METHOD and similar configurations (the full CORE API is of course also available). The most useful macros are:
CORE_DECLARE_IRQ_STATE
CORE_ENTER_ATOMIC()
CORE_EXIT_ATOMIC()
Used together to implement an ATOMIC section.
{ CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior // atomic section entry. CORE_ENTER_ATOMIC(); // Enter atomic section ... ... your code goes here ... ... CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored }
CORE_ATOMIC_SECTION(yourcode)
A concatenation of all three macros above.
{ CORE_ATOMIC_SECTION( ... ... your code goes here ... ... ) }
CORE_DECLARE_IRQ_STATE
CORE_ENTER_CRITICAL()
CORE_EXIT_CRITICAL()
CORE_CRITICAL_SECTION(yourcode)
These macros implement CRITICAL sections in a similar fashion as described above for ATOMIC sections.
CORE_DECLARE_NVIC_STATE
CORE_ENTER_NVIC()
CORE_EXIT_NVIC()
CORE_NVIC_SECTION(yourcode)
These macros implement NVIC mask sections in a similar fashion as described above for ATOMIC sections. See Examples for an example.
Refer to Macros or Macro Definition Documentation below for a full list of macros.
Most of the functions in the API are implemented as weak functions. This means that it is easy to reimplement them when special needs arise. Shown below is a reimplementation of CRITICAL sections suitable if FreeRTOS is used:
CORE_irqState_t CORE_EnterCritical(void) { vPortEnterCritical(); return 0; } void CORE_ExitCritical(CORE_irqState_t irqState) { (void)irqState; vPortExitCritical(); }
Also note that CORE_Enter/ExitCritical() are not implemented as inline functions. As a result, reimplementations will be possible even when original implementations reside inside a linked library.
Some RTOS'es must be notified on interrupt handler entry and exit. Macros CORE_INTERRUPT_ENTRY() and CORE_INTERRUPT_EXIT() are suitable placeholders for inserting such code. Insert these macros in all your interrupt handlers and then override the default macro implementations. Here is an example suitable if uC/OS is used:
// In emlib_config.h: #define CORE_INTERRUPT_ENTRY() OSIntEnter() #define CORE_INTERRUPT_EXIT() OSIntExit()
When using RAM based interrupt vector tables it is the users responsibility to allocate the table space correctly. The tables must be aligned as specified in the cpu reference manual.
CORE_InitNvicVectorTable()
Initialize a RAM based vector table by copying table entries from a source vector table to a target table. VTOR is set to the address of the target vector table.
CORE_GetNvicRamTableHandler()
CORE_SetNvicRamTableHandler()
Use these functions to get or set the interrupt handler for a specific IRQn. They both use the interrupt vector table defined by current VTOR register value.
Implement a NVIC critical section:
{ CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask // Set mask bits for IRQ's we wish to block in the NVIC critical section // In many cases you can create the disable mask once upon application // startup and use the mask globally throughout application lifetime. CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); // Enter NVIC critical section with the disable mask CORE_NVIC_SECTION(&mask, ... ... your code goes here ... ... ) }
Existing code using INT_Enable() and INT_Disable() must be ported to the em_core API. While em_int used a global counter to store the interrupt state, em_core uses a local variable. Any usage of INT_Disable() therefore needs to be replaced with a declaration of the interrupt state variable before entering the critical section.
Since the state variable is in the local scope, the critical section exit needs to occur within the scope of the variable. If multiple nested critical sections are used, each needs to have its own state variable in its own scope.
In many cases, completely disabling all interrupts using CRITICAL sections might be more heavy-handed than needed. When porting, consider whether other types of sections, like ATOMIC or NVIC mask, can be used to only disable a subset of the interrupts.
Replacing em_int calls with em_core function calls:
void func(void) { // INT_Disable(); CORE_DECLARE_IRQ_STATE; CORE_ENTER_ATOMIC(); . . . // INT_Enable(); CORE_EXIT_ATOMIC(); }
Data Structures | |
struct | CORE_nvicMask_t |
Typedefs | |
typedef uint32_t | CORE_irqState_t |
Functions | |
void | CORE_AtomicDisableIrq (void) |
Disable interrupts. More... | |
void | CORE_AtomicEnableIrq (void) |
Enable interrupts. More... | |
void | CORE_CriticalDisableIrq (void) |
Disable interrupts. More... | |
void | CORE_CriticalEnableIrq (void) |
Enable interrupts. More... | |
CORE_irqState_t | CORE_EnterAtomic (void) |
Enter an ATOMIC section. More... | |
CORE_irqState_t | CORE_EnterCritical (void) |
Enter a CRITICAL section. More... | |
void | CORE_EnterNvicMask (CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable) |
Enter a NVIC mask section. More... | |
void | CORE_ExitAtomic (CORE_irqState_t irqState) |
Exit an ATOMIC section. More... | |
void | CORE_ExitCritical (CORE_irqState_t irqState) |
Exit a CRITICAL section. More... | |
void | CORE_GetNvicEnabledMask (CORE_nvicMask_t *mask) |
Get current NVIC enable mask state. More... | |
bool | CORE_GetNvicMaskDisableState (const CORE_nvicMask_t *mask) |
Get NVIC disable state for a given mask. More... | |
void * | CORE_GetNvicRamTableHandler (IRQn_Type irqN) |
Utility function to get the handler for a specific interrupt. More... | |
bool | CORE_InIrqContext (void) |
Check if current cpu operation mode is handler mode. More... | |
void | CORE_InitNvicVectorTable (uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive) |
Initialize an interrupt vector table by copying table entries from a source to a target table. More... | |
bool | CORE_IrqIsBlocked (IRQn_Type irqN) |
Check if a specific interrupt is disabled or blocked. More... | |
bool | CORE_IrqIsDisabled (void) |
Check if interrupts are disabled. More... | |
void | CORE_NvicDisableMask (const CORE_nvicMask_t *disable) |
Disable NVIC interrupts. More... | |
void | CORE_NvicEnableMask (const CORE_nvicMask_t *enable) |
Set current NVIC interrupt enable mask. More... | |
bool | CORE_NvicIRQDisabled (IRQn_Type irqN) |
Check if a NVIC interrupt is disabled. More... | |
void | CORE_NvicMaskClearIRQ (IRQn_Type irqN, CORE_nvicMask_t *mask) |
Utility function to clear an IRQn bit in a NVIC enable/disable mask. More... | |
void | CORE_NvicMaskSetIRQ (IRQn_Type irqN, CORE_nvicMask_t *mask) |
Utility function to set an IRQn bit in a NVIC enable/disable mask. More... | |
void | CORE_SetNvicRamTableHandler (IRQn_Type irqN, void *handler) |
Utility function to set the handler for a specific interrupt. More... | |
void | CORE_YieldAtomic (void) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts. More... | |
void | CORE_YieldCritical (void) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts. More... | |
void | CORE_YieldNvicMask (const CORE_nvicMask_t *enable) |
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts. More... | |
#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 |
The interrupt priority level disabled within ATOMIC regions. Interrupts with priority level equal to or lower than this definition will be disabled within ATOMIC regions.
Definition at line 271 of file em_core.c.
Referenced by CORE_AtomicDisableIrq(), CORE_EnterAtomic(), CORE_IrqIsDisabled(), and CORE_YieldAtomic().
#define CORE_ATOMIC_IRQ_DISABLE | ( | ) | CORE_AtomicDisableIrq() |
#define CORE_ATOMIC_IRQ_ENABLE | ( | ) | CORE_AtomicEnableIrq() |
#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK |
#define CORE_ATOMIC_METHOD_BASEPRI 1 |
#define CORE_ATOMIC_METHOD_PRIMASK 0 |
#define CORE_ATOMIC_SECTION | ( | yourcode | ) |
Convenience macro for implementing an ATOMIC section.
Definition at line 126 of file em_core.h.
Referenced by DMADRV_TransferDone(), DMADRV_TransferRemainingCount(), GPIOINT_CallbackRegister(), RTCDRV_FreeTimer(), SPIDRV_GetTransferStatus(), UARTDRV_Transmit(), USBD_AbortAllTransfers(), USBD_Connect(), USBD_Disconnect(), USBD_StallEp(), and USBD_UnStallEp().
#define CORE_CRITICAL_IRQ_DISABLE | ( | ) | CORE_CriticalDisableIrq() |
#define CORE_CRITICAL_IRQ_ENABLE | ( | ) | CORE_CriticalEnableIrq() |
#define CORE_CRITICAL_SECTION | ( | yourcode | ) |
Convenience macro for implementing a CRITICAL section.
Definition at line 94 of file em_core.h.
Referenced by CORE_EnterNvicMask(), CORE_GetNvicEnabledMask(), CORE_GetNvicMaskDisableState(), CORE_NvicDisableMask(), CORE_NvicEnableMask(), and CORE_YieldNvicMask().
#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState |
Allocate storage for PRIMASK or BASEPRI value for use by CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros.
Definition at line 85 of file em_core.h.
Referenced by CAPLESENSE_Init(), DMADRV_AllocateChannel(), DMADRV_DeInit(), DMADRV_FreeChannel(), DMADRV_Init(), RETARGET_ReadChar(), RTCDRV_AllocateTimer(), RTCDRV_IsRunning(), RTCDRV_StartTimer(), RTCDRV_StopTimer(), RTCDRV_TimeRemaining(), SLEEP_Sleep(), SPIDRV_AbortTransfer(), SPIDRV_Init(), SPIDRV_MTransferSingleItemB(), SPIDRV_SetBitrate(), SPIDRV_SetFramelength(), UARTDRV_Abort(), UARTDRV_InitLeuart(), UARTDRV_InitUart(), UDELAY_Calibrate(), USBD_AbortTransfer(), USBD_Init(), USBD_Read(), USBD_RemoteWakeup(), USBD_Write(), USBTIMER_Start(), and USBTIMER_Stop().
#define CORE_DECLARE_NVIC_MASK | ( | x | ) | CORE_nvicMask_t x |
#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState |
#define CORE_DECLARE_NVIC_ZEROMASK | ( | x | ) | CORE_nvicMask_t x = {{0}} |
#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) |
#define CORE_ENTER_ATOMIC | ( | ) | irqState = CORE_EnterAtomic() |
Enter ATOMIC section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line 138 of file em_core.h.
Referenced by CAPLESENSE_Init(), DMADRV_AllocateChannel(), DMADRV_DeInit(), DMADRV_FreeChannel(), DMADRV_Init(), RETARGET_ReadChar(), RTCDRV_AllocateTimer(), RTCDRV_IsRunning(), RTCDRV_StartTimer(), RTCDRV_StopTimer(), RTCDRV_TimeRemaining(), SPIDRV_AbortTransfer(), SPIDRV_Init(), SPIDRV_MTransferSingleItemB(), SPIDRV_SetBitrate(), SPIDRV_SetFramelength(), UARTDRV_Abort(), UARTDRV_InitLeuart(), UARTDRV_InitUart(), UDELAY_Calibrate(), USBD_AbortTransfer(), USBD_Init(), USBD_Read(), USBD_RemoteWakeup(), USBD_Write(), USBTIMER_Start(), and USBTIMER_Stop().
#define CORE_ENTER_CRITICAL | ( | ) | irqState = CORE_EnterCritical() |
Enter CRITICAL section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line 106 of file em_core.h.
Referenced by SLEEP_Sleep().
#define CORE_ENTER_NVIC | ( | disable | ) | CORE_EnterNvicMask(&nvicState,disable) |
Enter NVIC mask section. Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.
[in] | disable | Mask specifying which NVIC interrupts to disable within the section. |
#define CORE_EXIT_ATOMIC | ( | ) | CORE_ExitAtomic(irqState) |
Exit ATOMIC section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line 142 of file em_core.h.
Referenced by CAPLESENSE_Init(), DMADRV_AllocateChannel(), DMADRV_DeInit(), DMADRV_FreeChannel(), DMADRV_Init(), RETARGET_ReadChar(), RTCDRV_AllocateTimer(), RTCDRV_IsRunning(), RTCDRV_StartTimer(), RTCDRV_StopTimer(), RTCDRV_TimeRemaining(), SPIDRV_AbortTransfer(), SPIDRV_Init(), SPIDRV_MTransferSingleItemB(), SPIDRV_SetBitrate(), SPIDRV_SetFramelength(), UARTDRV_Abort(), UARTDRV_InitLeuart(), UARTDRV_InitUart(), UDELAY_Calibrate(), USBD_AbortTransfer(), USBD_Init(), USBD_Read(), USBD_RemoteWakeup(), USBD_Write(), USBTIMER_Start(), and USBTIMER_Stop().
#define CORE_EXIT_CRITICAL | ( | ) | CORE_ExitCritical(irqState) |
Exit CRITICAL section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line 110 of file em_core.h.
Referenced by SLEEP_Sleep().
#define CORE_EXIT_NVIC | ( | ) | CORE_NvicEnableMask(&nvicState) |
Exit NVIC mask section. Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.
#define CORE_IN_IRQ_CONTEXT | ( | ) | CORE_InIrqContext() |
#define CORE_INTERRUPT_ENTRY | ( | ) |
#define CORE_INTERRUPT_EXIT | ( | ) |
#define CORE_IRQ_DISABLED | ( | ) | CORE_IrqIsDisabled() |
#define CORE_NVIC_DISABLE | ( | mask | ) | CORE_NvicDisableMask(mask) |
#define CORE_NVIC_ENABLE | ( | mask | ) | CORE_NvicEnableMask(mask) |
#define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) |
#define CORE_NVIC_SECTION | ( | mask, | |
yourcode | |||
) |
Convenience macro for implementing a NVIC mask section.
[in] | mask | Mask specifying which NVIC interrupts to disable within the section. |
[in] | yourcode | The code for the section. |
#define CORE_YIELD_ATOMIC | ( | ) | CORE_YieldAtomic(void) |
#define CORE_YIELD_CRITICAL | ( | ) | CORE_YieldCritical(void) |
#define CORE_YIELD_NVIC | ( | enable | ) | CORE_YieldNvicMask(enable) |
typedef uint32_t CORE_irqState_t |
SL_WEAK void CORE_AtomicDisableIrq | ( | void | ) |
Disable interrupts.
Disable interrupts with priority lower or equal to CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register to CORE_ATOMIC_BASE_PRIORITY_LEVEL.
Definition at line 390 of file em_core.c.
References __NVIC_PRIO_BITS, and CORE_ATOMIC_BASE_PRIORITY_LEVEL.
SL_WEAK void CORE_AtomicEnableIrq | ( | void | ) |
Enable interrupts.
Enable interrupts by setting core BASEPRI register to 0.
SL_WEAK void CORE_CriticalDisableIrq | ( | void | ) |
SL_WEAK void CORE_CriticalEnableIrq | ( | void | ) |
SL_WEAK CORE_irqState_t CORE_EnterAtomic | ( | void | ) |
Enter an ATOMIC section.
When an ATOMIC section is entered, interrupts with priority lower or equal to CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled.
Definition at line 437 of file em_core.c.
References __NVIC_PRIO_BITS, and CORE_ATOMIC_BASE_PRIORITY_LEVEL.
SL_WEAK CORE_irqState_t CORE_EnterCritical | ( | void | ) |
void CORE_EnterNvicMask | ( | CORE_nvicMask_t * | nvicState, |
const CORE_nvicMask_t * | disable | ||
) |
Enter a NVIC mask section.
When a NVIC mask section is entered, specified NVIC interrupts are disabled.
[out] | nvicState | Return NVIC interrupts enable mask prior to section entry. |
[in] | disable | Mask specifying which NVIC interrupts to disable within the section. |
Definition at line 515 of file em_core.c.
References CORE_CRITICAL_SECTION.
SL_WEAK void CORE_ExitAtomic | ( | CORE_irqState_t | irqState | ) |
Exit an ATOMIC section.
[in] | irqState | The interrupt priority blocking level to restore to BASEPRI when exiting the ATOMIC section. This value is usually the one returned by a prior call to CORE_EnterAtomic(). |
SL_WEAK void CORE_ExitCritical | ( | CORE_irqState_t | irqState | ) |
Exit a CRITICAL section.
[in] | irqState | The interrupt priority blocking level to restore to PRIMASK when exiting the CRITICAL section. This value is usually the one returned by a prior call to CORE_EnterCritical(). |
void CORE_GetNvicEnabledMask | ( | CORE_nvicMask_t * | mask | ) |
Get current NVIC enable mask state.
[out] | mask | Current NVIC enable mask. |
Definition at line 728 of file em_core.c.
References CORE_CRITICAL_SECTION.
bool CORE_GetNvicMaskDisableState | ( | const CORE_nvicMask_t * | mask | ) |
Get NVIC disable state for a given mask.
[in] | mask | NVIC mask to check. |
Definition at line 745 of file em_core.c.
References CORE_nvicMask_t::a, and CORE_CRITICAL_SECTION.
void * CORE_GetNvicRamTableHandler | ( | IRQn_Type | irqN | ) |
Utility function to get the handler for a specific interrupt.
[in] | irqN | The IRQn_Type enumerator for the interrupt. |
Definition at line 800 of file em_core.c.
References EXT_IRQ_COUNT.
SL_WEAK bool CORE_InIrqContext | ( | void | ) |
void CORE_InitNvicVectorTable | ( | uint32_t * | sourceTable, |
uint32_t | sourceSize, | ||
uint32_t * | targetTable, | ||
uint32_t | targetSize, | ||
void * | defaultHandler, | ||
bool | overwriteActive | ||
) |
Initialize an interrupt vector table by copying table entries from a source to a target table.
[in] | sourceTable | Address of source vector table. |
[in] | sourceSize | Number of entries is source vector table. |
[in] | targetTable | Address of target (new) vector table. |
[in] | targetSize | Number of entries is target vector table. |
[in] | defaultHandler | Address of interrupt handler used for target entries for which where there is no corresponding source entry (i.e. target table is larger than source table). |
[in] | overwriteActive | When true, a target table entry is always overwritten with the corresponding source entry. If false, a target table entry is only overwritten if it is zero. This makes it possible for an application to partly initialize a target table before passing it to this function. |
Definition at line 856 of file em_core.c.
References RAM_MEM_BASE, and RAM_MEM_SIZE.
Check if a specific interrupt is disabled or blocked.
[in] | irqN | The IRQn_Type enumerator for the interrupt to check. |
Definition at line 662 of file em_core.c.
References __NVIC_PRIO_BITS, CORE_NvicIRQDisabled(), EXT_IRQ_COUNT, and SVCall_IRQn.
Referenced by UARTDRV_ForceTransmit().
SL_WEAK bool CORE_IrqIsDisabled | ( | void | ) |
Check if interrupts are disabled.
Definition at line 709 of file em_core.c.
References __NVIC_PRIO_BITS, and CORE_ATOMIC_BASE_PRIORITY_LEVEL.
void CORE_NvicDisableMask | ( | const CORE_nvicMask_t * | disable | ) |
Disable NVIC interrupts.
[in] | disable | Mask specifying which NVIC interrupts to disable. |
Definition at line 531 of file em_core.c.
References CORE_CRITICAL_SECTION.
void CORE_NvicEnableMask | ( | const CORE_nvicMask_t * | enable | ) |
Set current NVIC interrupt enable mask.
[out] | enable | Mask specifying which NVIC interrupts are currently enabled. |
Definition at line 545 of file em_core.c.
References CORE_CRITICAL_SECTION.
bool CORE_NvicIRQDisabled | ( | IRQn_Type | irqN | ) |
Check if a NVIC interrupt is disabled.
[in] | irqN | The IRQn_Type enumerator for the interrupt to check. |
Definition at line 778 of file em_core.c.
References CORE_nvicMask_t::a, and EXT_IRQ_COUNT.
Referenced by CORE_IrqIsBlocked().
void CORE_NvicMaskClearIRQ | ( | IRQn_Type | irqN, |
CORE_nvicMask_t * | mask | ||
) |
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
[in] | irqN | The IRQn_Type enumerator for the interrupt. |
[in,out] | mask | The mask to clear interrupt bit in. |
Definition at line 633 of file em_core.c.
References CORE_nvicMask_t::a, and EXT_IRQ_COUNT.
void CORE_NvicMaskSetIRQ | ( | IRQn_Type | irqN, |
CORE_nvicMask_t * | mask | ||
) |
Utility function to set an IRQn bit in a NVIC enable/disable mask.
[in] | irqN | The IRQn_Type enumerator for the interrupt. |
[in,out] | mask | The mask to set interrupt bit in. |
Definition at line 617 of file em_core.c.
References CORE_nvicMask_t::a, and EXT_IRQ_COUNT.
void CORE_SetNvicRamTableHandler | ( | IRQn_Type | irqN, |
void * | handler | ||
) |
Utility function to set the handler for a specific interrupt.
[in] | irqN | The IRQn_Type enumerator for the interrupt. |
[in] | handler | The handler address. |
Definition at line 819 of file em_core.c.
References EXT_IRQ_COUNT.
SL_WEAK void CORE_YieldAtomic | ( | void | ) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
Definition at line 486 of file em_core.c.
References __NVIC_PRIO_BITS, and CORE_ATOMIC_BASE_PRIORITY_LEVEL.
SL_WEAK void CORE_YieldCritical | ( | void | ) |
void CORE_YieldNvicMask | ( | const CORE_nvicMask_t * | enable | ) |
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
[in] | enable | Mask specifying which NVIC interrupts to briefly enable. |
Definition at line 563 of file em_core.c.
References CORE_nvicMask_t::a, and CORE_CRITICAL_SECTION.