36 #if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )
60 #if (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN)
61 #error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions
63 #if (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN)
64 #error Conflict in HFXOENS and HFXOEN bitpositions
66 #if (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN)
67 #error Conflict in LFRCOENS and LFRCOEN bitpositions
69 #if (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN)
70 #error Conflict in LFXOENS and LFXOEN bitpositions
74 #if defined( _SILICON_LABS_32B_SERIES_0 )
77 #if defined( _EFM32_GECKO_FAMILY )
78 #define ERRATA_FIX_EMU_E107_EN
79 #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))
80 #define NON_WIC_INT_MASK_1 (~(0x0U))
82 #elif defined( _EFM32_TINY_FAMILY )
83 #define ERRATA_FIX_EMU_E107_EN
84 #define NON_WIC_INT_MASK_0 (~(0x001be323U))
85 #define NON_WIC_INT_MASK_1 (~(0x0U))
87 #elif defined( _EFM32_GIANT_FAMILY )
88 #define ERRATA_FIX_EMU_E107_EN
89 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
90 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
92 #elif defined( _EFM32_WONDER_FAMILY )
93 #define ERRATA_FIX_EMU_E107_EN
94 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
95 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
101 #if defined(_SILICON_LABS_32B_SERIES_0) && defined( _EFM32_HAPPY_FAMILY )
102 #define ERRATA_FIX_EMU_E108_EN
106 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
107 #define ERRATA_FIX_EMU_E208_EN
111 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
112 #define ERRATA_FIX_DCDC_FETCNT_SET_EN
116 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
117 #define ERRATA_FIX_DCDC_LNHS_BLOCK_EN
121 errataFixDcdcHsTrimSet,
122 errataFixDcdcHsBypassLn,
123 errataFixDcdcHsLnWaitDone
124 } errataFixDcdcHs_TypeDef;
125 static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit;
131 #define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block))
135 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
136 #define RAM1_BLOCKS 2
137 #define RAM1_BLOCK_SIZE 0x10000 // 64 kB blocks
138 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
139 #define RAM0_BLOCKS 2
140 #define RAM0_BLOCK_SIZE 0x4000
141 #define RAM1_BLOCKS 2
142 #define RAM1_BLOCK_SIZE 0x4000 // 16 kB blocks
143 #elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY)
144 #define RAM0_BLOCKS 4
145 #define RAM0_BLOCK_SIZE 0x8000 // 32 kB blocks
146 #elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY)
147 #define RAM0_BLOCKS 4
148 #define RAM0_BLOCK_SIZE 0x1000 // 4 kB blocks
151 #if defined(_SILICON_LABS_32B_SERIES_0)
153 #define RAM0_END (SRAM_BASE + SRAM_SIZE - 1)
155 #define RAM0_END RAM_MEM_END
161 #if defined( _EMU_DCDCCTRL_MASK )
163 #if !defined(PWRCFG_DCDCTODVDD_VMIN)
164 #define PWRCFG_DCDCTODVDD_VMIN 1800
166 #if !defined(PWRCFG_DCDCTODVDD_VMAX)
167 #define PWRCFG_DCDCTODVDD_VMAX 3000
178 #if defined( _EMU_DCDCCTRL_MASK )
179 static uint16_t dcdcMaxCurrent_mA;
180 static uint16_t dcdcEm01LoadCurrent_mA;
181 static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl;
183 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
184 static EMU_EM01Init_TypeDef vScaleEM01Config = {
false};
195 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
197 __STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level)
199 return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level);
220 static void emState(emState_TypeDef action)
224 static uint32_t cmuStatus;
226 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
227 static uint8_t vScaleStatus;
232 if (action == emState_Save)
235 cmuStatus =
CMU->STATUS;
237 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
240 vScaleStatus = (uint8_t)((
EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
241 >> _EMU_STATUS_VSCALE_SHIFT);
244 else if (action == emState_Restore)
247 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
250 EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus);
267 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
270 CMU->OSCENCMD = oscEnCmd;
272 #if defined( _EMU_STATUS_VSCALE_MASK )
298 #if defined( ERRATA_FIX_EMU_E107_EN )
300 __STATIC_INLINE
bool getErrataFixEmuE107En(
void)
305 uint16_t majorMinorRev;
319 #if defined( _EFM32_GECKO_FAMILY )
320 return (majorMinorRev <= 0x0103);
321 #elif defined( _EFM32_TINY_FAMILY )
322 return (majorMinorRev <= 0x0102);
323 #elif defined( _EFM32_GIANT_FAMILY )
324 return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);
325 #elif defined( _EFM32_WONDER_FAMILY )
326 return (majorMinorRev == 0x0100);
335 #define DCDC_LP_PFET_CNT 7
336 #define DCDC_LP_NFET_CNT 7
337 #if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
338 static void currentLimitersUpdate(
void);
339 static void dcdcFetCntSet(
bool lpModeSet)
342 static uint32_t emuDcdcMiscCtrlReg;
346 emuDcdcMiscCtrlReg =
EMU->DCDCMISCCTRL;
347 tmp =
EMU->DCDCMISCCTRL
348 & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK);
349 tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT)
350 | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
351 EMU->DCDCMISCCTRL = tmp;
352 currentLimitersUpdate();
356 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;
357 currentLimitersUpdate();
362 #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
363 static void dcdcHsFixLnBlock(
void)
365 #define EMU_DCDCSTATUS (* (volatile uint32_t *)(EMU_BASE + 0x7C))
366 if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet)
367 || (errataFixDcdcHsState == errataFixDcdcHsBypassLn))
370 if ((
EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
372 while (!(EMU_DCDCSTATUS & (0x1 << 16)));
374 errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;
380 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
382 static void vScaleDownEM23Setup(
void)
384 uint32_t hfSrcClockFrequency;
386 EMU_VScaleEM23_TypeDef scaleEM23Voltage =
387 (EMU_VScaleEM23_TypeDef)((
EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK)
388 >> _EMU_CTRL_EM23VSCALE_SHIFT);
390 EMU_VScaleEM01_TypeDef currentEM01Voltage =
391 (EMU_VScaleEM01_TypeDef)((
EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
392 >> _EMU_STATUS_VSCALE_SHIFT);
398 if ((uint32_t)scaleEM23Voltage > (uint32_t)currentEM01Voltage)
401 if (scaleEM23Voltage == emuVScaleEM23_LowPower)
405 if (hfSrcClockFrequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)
482 #if defined( ERRATA_FIX_EMU_E107_EN )
483 bool errataFixEmuE107En;
484 uint32_t nonWicIntEn[2];
488 emState(emState_Save);
490 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
491 vScaleDownEM23Setup();
495 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
499 #if defined( ERRATA_FIX_EMU_E107_EN )
500 errataFixEmuE107En = getErrataFixEmuE107En();
501 if (errataFixEmuE107En)
503 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
504 NVIC->ICER[0] = nonWicIntEn[0];
505 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
506 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
507 NVIC->ICER[1] = nonWicIntEn[1];
512 #if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
515 #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
521 #if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
522 dcdcFetCntSet(
false);
526 #if defined( ERRATA_FIX_EMU_E107_EN )
527 if (errataFixEmuE107En)
529 NVIC->ISER[0] = nonWicIntEn[0];
530 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
531 NVIC->ISER[1] = nonWicIntEn[1];
539 emState(emState_Restore);
601 #if defined( ERRATA_FIX_EMU_E107_EN )
602 bool errataFixEmuE107En;
603 uint32_t nonWicIntEn[2];
607 emState(emState_Save);
609 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
610 vScaleDownEM23Setup();
627 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
631 #if defined( ERRATA_FIX_EMU_E107_EN )
632 errataFixEmuE107En = getErrataFixEmuE107En();
633 if (errataFixEmuE107En)
635 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
636 NVIC->ICER[0] = nonWicIntEn[0];
637 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
638 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
639 NVIC->ICER[1] = nonWicIntEn[1];
644 #if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
647 #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
653 #if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
654 dcdcFetCntSet(
false);
658 #if defined( ERRATA_FIX_EMU_E107_EN )
659 if (errataFixEmuE107En)
661 NVIC->ISER[0] = nonWicIntEn[0];
662 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
663 NVIC->ISER[1] = nonWicIntEn[1];
671 emState(emState_Restore);
694 emState(emState_Restore);
709 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
710 uint32_t em4seq2 = (
EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
711 | (2 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
712 uint32_t em4seq3 = (
EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
713 | (3 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
724 #if defined( _EMU_EM4CTRL_MASK )
725 if ((
EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S)
727 uint32_t dcdcMode =
EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK;
728 if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE
729 || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)
738 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
739 if (
EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H)
744 *(
volatile uint32_t *)(
EMU_BASE + 0x190) = 0x0000ADE8UL;
745 *(
volatile uint32_t *)(
EMU_BASE + 0x198) |= (0x1UL << 7);
746 *(
volatile uint32_t *)(
EMU_BASE + 0x88) |= (0x1UL << 8);
750 #if defined( ERRATA_FIX_EMU_E108_EN )
753 *(
volatile uint32_t *)0x400C80E4 = 0;
756 #if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
759 #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
763 for (i = 0; i < 4; i++)
765 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
766 EMU->EM4CTRL = em4seq2;
767 EMU->EM4CTRL = em4seq3;
769 EMU->EM4CTRL = em4seq2;
778 #if defined( _EMU_EM4CTRL_MASK )
787 void EMU_EnterEM4H(
void)
801 void EMU_EnterEM4S(
void)
827 #if defined( _EMU_MEMCTRL_MASK )
828 EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK;
829 #elif defined( _EMU_RAM0CTRL_MASK )
830 EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK;
882 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12
884 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 0;
885 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000) << 1;
886 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000) << 2;
887 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000) << 3;
888 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1
890 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000) << 0;
891 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000) << 1;
892 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 2;
893 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000) << 3;
894 #elif defined(RAM0_BLOCKS)
896 for (
int i = 1; i < RAM0_BLOCKS; i++)
898 mask |= ADDRESS_NOT_IN_BLOCK(start,
RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1);
904 #if defined( _EMU_MEMCTRL_MASK )
905 EMU->MEMCTRL =
EMU->MEMCTRL | mask;
906 #elif defined( _EMU_RAM0CTRL_MASK )
907 EMU->RAM0CTRL =
EMU->RAM0CTRL | mask;
914 #if defined(RAM1_MEM_END)
916 if (end > RAM1_MEM_END)
918 for (
int i = 0; i < RAM1_BLOCKS; i++)
920 mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i;
923 EMU->RAM1CTRL |= mask;
927 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
943 void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask,
bool enable)
946 EMU->EM23PERNORETAINCTRL = periMask & emuPeripheralRetention_ALL;
960 emState(emState_Save);
964 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
979 void EMU_VScaleEM01ByClock(uint32_t clockFrequency,
bool wait)
981 uint32_t hfSrcClockFrequency;
982 uint32_t hfPresc = 1U + ((
CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
983 >> _CMU_HFPRESC_PRESC_SHIFT);
986 if (clockFrequency == 0)
992 hfSrcClockFrequency = clockFrequency;
996 if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable
997 && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX))
999 EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_LowPower);
1003 EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_HighPerformance);
1014 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
1033 void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage,
bool wait)
1035 uint32_t hfSrcClockFrequency;
1036 uint32_t hfPresc = 1U + ((
CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
1037 >> _CMU_HFPRESC_PRESC_SHIFT);
1040 if (voltage == emuVScaleEM01_LowPower)
1042 EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX);
1045 EMU->CMD = vScaleEM01Cmd(voltage);
1054 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
1062 void EMU_EM01Init(
const EMU_EM01Init_TypeDef *em01Init)
1064 vScaleEM01Config.vScaleEM01LowPowerVoltageEnable =
1065 em01Init->vScaleEM01LowPowerVoltageEnable;
1066 EMU_VScaleEM01ByClock(0,
true);
1080 #if defined( _EMU_CTRL_EMVREG_MASK )
1083 #elif defined( _EMU_CTRL_EM23VREG_MASK )
1085 : (
EMU->CTRL & ~EMU_CTRL_EM23VREG);
1090 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
1091 EMU->CTRL = (
EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK)
1092 | (em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT);
1097 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
1105 void EMU_EM4Init(
const EMU_EM4Init_TypeDef *em4Init)
1107 #if defined( _EMU_EM4CONF_MASK )
1109 uint32_t em4conf =
EMU->EM4CONF;
1112 em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK
1113 | _EMU_EM4CONF_OSC_MASK
1114 | _EMU_EM4CONF_BURTCWU_MASK
1115 | _EMU_EM4CONF_VREGEN_MASK);
1118 em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)
1120 | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)
1121 | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);
1124 EMU->EM4CONF = em4conf;
1126 #elif defined( _EMU_EM4CTRL_MASK )
1129 uint32_t em4ctrl =
EMU->EM4CTRL;
1131 em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK
1132 | _EMU_EM4CTRL_RETAINLFRCO_MASK
1133 | _EMU_EM4CTRL_RETAINULFRCO_MASK
1134 | _EMU_EM4CTRL_EM4STATE_MASK
1135 | _EMU_EM4CTRL_EM4IORETMODE_MASK);
1137 em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0)
1138 | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0)
1139 | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)
1140 | (em4Init->em4State ? EMU_EM4CTRL_EM4STATE_EM4H : 0)
1141 | (em4Init->pinRetentionMode);
1143 EMU->EM4CTRL = em4ctrl;
1146 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
1147 EMU->CTRL = (
EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK)
1148 | (em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT);
1154 #if defined( BU_PRESENT )
1162 void EMU_BUPDInit(
const EMU_BUPDInit_TypeDef *bupdInit)
1167 reg =
EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK
1168 | _EMU_PWRCONF_VOUTSTRONG_MASK
1169 | _EMU_PWRCONF_VOUTMED_MASK
1170 | _EMU_PWRCONF_VOUTWEAK_MASK);
1172 reg |= bupdInit->resistor
1173 | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)
1174 | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)
1175 | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT);
1180 reg =
EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
1181 reg |= (bupdInit->inactivePower);
1185 reg =
EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK);
1186 reg |= (bupdInit->activePower);
1190 reg =
EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK
1191 | _EMU_BUCTRL_BODCAL_MASK
1192 | _EMU_BUCTRL_STATEN_MASK
1193 | _EMU_BUCTRL_EN_MASK);
1197 reg |= bupdInit->probe
1198 | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)
1199 | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)
1200 | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT);
1206 EMU_BUPinEnable(bupdInit->enable);
1223 EFM_ASSERT(value<8);
1224 EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));
1229 EMU->BUACT = (
EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)
1230 | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);
1233 EMU->BUINACT = (
EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)
1234 | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);
1250 EFM_ASSERT(value < 4);
1251 EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));
1256 EMU->BUACT = (
EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)
1257 | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);
1260 EMU->BUINACT = (
EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)
1261 | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);
1269 #if defined( _EMU_DCDCCTRL_MASK )
1271 #if defined( _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK )
1272 #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK
1273 #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT
1274 #elif defined( _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK )
1275 #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK
1276 #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT
1278 #if defined( _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK )
1279 #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK
1280 #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT
1281 #elif defined( _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK )
1282 #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK
1283 #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT
1289 dcdcTrimMode_EM234H_LP = 0,
1290 #if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
1291 dcdcTrimMode_EM01_LP,
1294 } dcdcTrimMode_TypeDef;
1304 static bool dcdcConstCalibrationLoad(
void)
1306 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
1308 volatile uint32_t *reg;
1311 volatile uint32_t*
const diCal_EMU_DCDCLNFREQCTRL = (
volatile uint32_t *)(0x0FE08038);
1312 volatile uint32_t*
const diCal_EMU_DCDCLNVCTRL = (
volatile uint32_t *)(0x0FE08040);
1313 volatile uint32_t*
const diCal_EMU_DCDCLPCTRL = (
volatile uint32_t *)(0x0FE08048);
1314 volatile uint32_t*
const diCal_EMU_DCDCLPVCTRL = (
volatile uint32_t *)(0x0FE08050);
1315 volatile uint32_t*
const diCal_EMU_DCDCTRIM0 = (
volatile uint32_t *)(0x0FE08058);
1316 volatile uint32_t*
const diCal_EMU_DCDCTRIM1 = (
volatile uint32_t *)(0x0FE08060);
1318 if (
DEVINFO->DCDCLPVCTRL0 != UINT_MAX)
1320 val = *(diCal_EMU_DCDCLNFREQCTRL + 1);
1321 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;
1324 val = *(diCal_EMU_DCDCLNVCTRL + 1);
1325 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL;
1328 val = *(diCal_EMU_DCDCLPCTRL + 1);
1329 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLPCTRL;
1332 val = *(diCal_EMU_DCDCLPVCTRL + 1);
1333 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL;
1336 val = *(diCal_EMU_DCDCTRIM0 + 1);
1337 reg = (
volatile uint32_t *)*diCal_EMU_DCDCTRIM0;
1340 val = *(diCal_EMU_DCDCTRIM1 + 1);
1341 reg = (
volatile uint32_t *)*diCal_EMU_DCDCTRIM1;
1361 static void dcdcValidatedConfigSet(
void)
1364 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1)
1366 #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2)
1367 #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44))
1369 uint32_t lnForceCcm;
1371 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
1372 uint32_t dcdcTiming;
1377 EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;
1383 lnForceCcm =
BUS_RegBitRead(&
EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT);
1395 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
1396 EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
1397 EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS
1398 | EMU_DCDCMISCCTRL_LPCMPHYSHI;
1401 if ((rev.
major == 1)
1403 && (errataFixDcdcHsState == errataFixDcdcHsInit))
1406 EMU_DCDCSMCTRL |= 1;
1408 dcdcTiming =
EMU->DCDCTIMING;
1409 dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
1410 |_EMU_DCDCTIMING_LNWAIT_MASK
1411 |_EMU_DCDCTIMING_BYPWAIT_MASK);
1413 dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
1414 | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
1415 | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));
1416 EMU->DCDCTIMING = dcdcTiming;
1418 errataFixDcdcHsState = errataFixDcdcHsTrimSet;
1431 static void currentLimitersUpdate(
void)
1434 uint32_t zdetLimSel;
1436 uint16_t maxReverseCurrent_mA;
1443 const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2))
1444 / (5 * (DCDC_LP_PFET_CNT + 1)))
1446 const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT;
1449 pFetCnt = (
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK)
1450 >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;
1455 lncLimSel = (((dcdcMaxCurrent_mA + 40) + ((dcdcMaxCurrent_mA + 40) / 2))
1456 / (5 * (pFetCnt + 1)))
1460 lncLimSel =
SL_MIN(lncLimSel,
1461 _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
1462 >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT);
1464 lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT;
1467 EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0);
1468 EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0);
1470 EMU->DCDCMISCCTRL = (
EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
1471 | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK))
1472 | (lncLimSel | lpcLimSel);
1478 if (dcdcReverseCurrentControl >= 0)
1481 maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl;
1483 zdetLimSel = ( ((maxReverseCurrent_mA + 40) + ((maxReverseCurrent_mA + 40) / 2))
1484 / ((2 * (pFetCnt + 1)) + ((pFetCnt + 1) / 2)) );
1486 zdetLimSel =
SL_MIN(zdetLimSel,
1487 _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK
1488 >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT);
1490 zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT;
1493 EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0);
1495 EMU->DCDCZDETCTRL = (
EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK)
1512 static void userCurrentLimitsSet(uint32_t maxCurrent_mA,
1513 EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl)
1515 dcdcMaxCurrent_mA = maxCurrent_mA;
1516 dcdcReverseCurrentControl = reverseCurrentControl;
1527 static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp)
1531 case emuDcdcLnCompCtrl_1u0F:
1532 EMU->DCDCLNCOMPCTRL = 0x57204077UL;
1535 case emuDcdcLnCompCtrl_4u7F:
1536 EMU->DCDCLNCOMPCTRL = 0xB7102137UL;
1557 static bool lpCmpHystCalibrationLoad(
bool lpAttenuation,
1559 dcdcTrimMode_TypeDef trimMode)
1561 uint32_t lpcmpHystSel;
1564 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1565 uint8_t devinfoRev = SYSTEM_GetDevinfoRev();
1574 lpcmpHystSel =
DEVINFO->DCDCLPCMPHYSSEL0;
1578 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK)
1579 >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;
1583 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)
1584 >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;
1590 lpcmpHystSel =
DEVINFO->DCDCLPCMPHYSSEL1;
1594 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK)
1595 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;
1599 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK)
1600 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;
1604 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK)
1605 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;
1609 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK)
1610 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;
1621 if (trimMode == dcdcTrimMode_EM234H_LP)
1624 lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT;
1625 if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK)
1631 EMU->DCDCLPCTRL = (
EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel;
1634 #if defined( _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK )
1635 if (trimMode == dcdcTrimMode_EM01_LP)
1638 lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT;
1639 if (lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK)
1645 EMU->DCDCLPEM01CFG = (
EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel;
1666 static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL,
1671 uint32_t vrefLow = 0;
1672 uint32_t vrefHigh = 0;
1676 uint32_t switchVal = (lpcmpBias << 8) | (lpAttenuation ? 1 : 0);
1679 case ((0 << 8) | 1):
1680 vrefLow =
DEVINFO->DCDCLPVCTRL2;
1681 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK)
1682 >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
1683 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK)
1684 >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
1687 case ((1 << 8) | 1):
1688 vrefLow =
DEVINFO->DCDCLPVCTRL2;
1689 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK)
1690 >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
1691 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK)
1692 >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
1695 case ((2 << 8) | 1):
1696 vrefLow =
DEVINFO->DCDCLPVCTRL3;
1697 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK)
1698 >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
1699 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK)
1700 >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
1703 case ((3 << 8) | 1):
1704 vrefLow =
DEVINFO->DCDCLPVCTRL3;
1705 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK)
1706 >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
1707 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK)
1708 >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
1711 case ((0 << 8) | 0):
1712 vrefLow =
DEVINFO->DCDCLPVCTRL0;
1713 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK)
1714 >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT;
1715 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK)
1716 >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT;
1719 case ((1 << 8) | 0):
1720 vrefLow =
DEVINFO->DCDCLPVCTRL0;
1721 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK)
1722 >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT;
1723 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK)
1724 >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT;
1727 case ((2 << 8) | 0):
1728 vrefLow =
DEVINFO->DCDCLPVCTRL1;
1729 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK)
1730 >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT;
1731 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK)
1732 >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT;
1735 case ((3 << 8) | 0):
1736 vrefLow =
DEVINFO->DCDCLPVCTRL1;
1737 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK)
1738 >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT;
1739 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK)
1740 >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT;
1762 uint32_t currentDcdcMode = (
EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK);
1764 if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode)
1770 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1772 while(
EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
1774 BUS_RegBitWrite(&
EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);
1777 if (((EMU_DcdcMode_TypeDef)currentDcdcMode == emuDcdcMode_Bypass)
1778 && (dcdcMode == emuDcdcMode_LowNoise))
1780 errataFixDcdcHsState = errataFixDcdcHsBypassLn;
1786 if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS))
1787 && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise)))
1790 EMU_IntClear(EMU_IFC_DCDCLNRUNNING);
1791 while(
EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
1792 EMU->DCDCCTRL = (
EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE;
1793 while(!(EMU_IntGet() & EMU_IF_DCDCLNRUNNING));
1798 while(
EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
1799 EMU->DCDCCTRL = (
EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode;
1815 EMU_DcdcMode_TypeDef currentDcdcMode
1816 = (EMU_DcdcMode_TypeDef)(
EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK);
1817 EMU_DcdcLnRcoBand_TypeDef rcoBand
1818 = (EMU_DcdcLnRcoBand_TypeDef)((
EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
1819 >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
1823 EMU_IntClear(EMU_IFC_DCDCINBYPASS);
1825 while(
EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
1826 while(!(EMU_IntGet() & EMU_IF_DCDCINBYPASS));
1827 if (conductionMode == emuDcdcConductionMode_DiscontinuousLN)
1829 EMU->DCDCMISCCTRL &= ~ EMU_DCDCMISCCTRL_LNFORCECCM;
1837 EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz);
1842 EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM;
1871 uint32_t lpCmpBiasSelEM234H;
1873 #if defined(_EMU_PWRCFG_MASK)
1876 EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD;
1880 if ((
EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD)
1891 dcdcConstCalibrationLoad();
1894 EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200);
1895 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA);
1896 EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200);
1898 if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise)
1901 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200);
1903 #if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80)
1904 else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower)
1907 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10);
1912 EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000);
1914 if (dcdcInit->em234LoadCurrent_uA < 75)
1916 lpCmpBiasSelEM234H = 0;
1918 else if (dcdcInit->em234LoadCurrent_uA < 500)
1920 lpCmpBiasSelEM234H = 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
1922 else if (dcdcInit->em234LoadCurrent_uA < 2500)
1924 lpCmpBiasSelEM234H = 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
1928 lpCmpBiasSelEM234H = 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
1937 EMU->DCDCMISCCTRL = (
EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK
1938 | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK))
1939 | ((uint32_t)lpCmpBiasSelEM234H
1940 | (dcdcInit->reverseCurrentControl >= 0 ?
1941 EMU_DCDCMISCCTRL_LNFORCECCM : 0));
1942 #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
1944 EMU->DCDCLPEM01CFG = (
EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
1945 | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3;
1951 dcdcValidatedConfigSet();
1955 userCurrentLimitsSet(dcdcInit->maxCurrent_mA,
1956 dcdcInit->reverseCurrentControl);
1957 dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA;
1970 compCtrlSet(dcdcInit->dcdcLnCompCtrl);
1980 #if ( _SILICON_LABS_GECKO_INTERNAL_SDID == 80 )
1984 _EMU_PWRCTRL_ANASW_SHIFT,
1985 dcdcInit->anaPeripheralPower ? 1 : 0);
1988 #if defined(_EMU_PWRCTRL_REGPWRSEL_MASK)
1991 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD;
1999 #if ( _SILICON_LABS_GECKO_INTERNAL_SDID != 80 )
2003 _EMU_PWRCTRL_ANASW_SHIFT,
2004 dcdcInit->anaPeripheralPower ? 1 : 0);
2024 #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )
2026 #define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1)
2027 bool validOutVoltage;
2028 bool attenuationSet;
2030 uint32_t mVhigh = 0;
2032 uint32_t vrefVal[DCDC_TRIM_MODES] = {0};
2033 uint32_t vrefLow[DCDC_TRIM_MODES] = {0};
2034 uint32_t vrefHigh[DCDC_TRIM_MODES] = {0};
2035 uint8_t lpcmpBias[DCDC_TRIM_MODES] = {0};
2039 validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)
2040 && (mV <= PWRCFG_DCDCTODVDD_VMAX));
2042 if (!validOutVoltage)
2050 attenuationSet = (mV > 1800);
2055 mVdiff = mVhigh - mVlow;
2061 mVdiff = mVhigh - mVlow;
2069 vrefLow[dcdcTrimMode_LN] =
DEVINFO->DCDCLNVCTRL0;
2070 vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
2071 >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
2072 vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)
2073 >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
2077 vrefLow[dcdcTrimMode_LN] =
DEVINFO->DCDCLNVCTRL0;
2078 vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)
2079 >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
2080 vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)
2081 >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
2086 lpcmpBias[dcdcTrimMode_EM234H_LP] = (
EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK)
2087 >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
2088 lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP],
2089 &vrefHigh[dcdcTrimMode_EM234H_LP],
2091 lpcmpBias[dcdcTrimMode_EM234H_LP]);
2093 #if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
2095 lpcmpBias[dcdcTrimMode_EM01_LP] = (
EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
2096 >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT;
2097 lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP],
2098 &vrefHigh[dcdcTrimMode_EM01_LP],
2100 lpcmpBias[dcdcTrimMode_EM01_LP]);
2105 vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN]))
2107 vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN];
2109 vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP]))
2111 vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP];
2113 #if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
2114 vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP]))
2116 vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP];
2120 if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN])
2121 || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN])
2122 #
if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
2123 || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP])
2124 || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP])
2126 || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP])
2127 || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP]))
2137 EMU->DCDCLNVCTRL = (
EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK))
2138 | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT)
2139 | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0);
2145 if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP)))
2152 #if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
2154 if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP)))
2162 vrefVal[dcdcTrimMode_EM234H_LP] =
SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]);
2166 vrefVal[dcdcTrimMode_EM234H_LP] =
SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U);
2167 EMU->DCDCLPVCTRL = (
EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK))
2168 | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT)
2169 | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0);
2186 uint32_t sliceCount = 0;
2187 uint32_t rcoBand = (
EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
2188 >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;
2191 if ((
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= emuDcdcLnRcoBand_5MHz))
2193 if (em0LoadCurrent_mA < 20)
2197 else if ((em0LoadCurrent_mA >= 20) && (em0LoadCurrent_mA < 40))
2206 else if ((!(
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= emuDcdcLnRcoBand_4MHz))
2208 if (em0LoadCurrent_mA < 10)
2212 else if ((em0LoadCurrent_mA >= 10) && (em0LoadCurrent_mA < 20))
2221 else if ((
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= emuDcdcLnRcoBand_4MHz))
2223 if (em0LoadCurrent_mA < 40)
2243 sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT
2244 | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
2245 EMU->DCDCMISCCTRL = (
EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK
2246 | _EMU_DCDCMISCCTRL_NFETCNT_MASK))
2250 currentLimitersUpdate();
2263 forcedCcm =
BUS_RegBitRead(&
EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT);
2266 EFM_ASSERT((!forcedCcm && band <= emuDcdcLnRcoBand_4MHz) || forcedCcm);
2268 EMU->DCDCLNFREQCTRL = (
EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
2269 | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
2292 #if defined(_EMU_PWRCFG_MASK)
2294 EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD;
2298 #if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH)
2299 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH;
2300 #elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD)
2301 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD;
2306 while(
EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
2307 EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF;
2309 dcdcModeSet = (
EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF);
2310 EFM_ASSERT(dcdcModeSet);
2317 #if defined( EMU_STATUS_VMONRDY )
2319 __STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(
int mV)
2321 return (mV - 1200) / 200;
2324 __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(
int mV, uint32_t coarseThreshold)
2326 return (mV - 1200 - (coarseThreshold * 200)) / 20;
2342 void EMU_VmonInit(
const EMU_VmonInit_TypeDef *vmonInit)
2344 uint32_t thresholdCoarse, thresholdFine;
2345 EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980));
2347 thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->threshold);
2348 thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->threshold, thresholdCoarse);
2350 switch(vmonInit->channel)
2352 case emuVmonChannel_AVDD:
2353 EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
2354 | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
2355 | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
2356 | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
2357 | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
2358 | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
2359 | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
2361 case emuVmonChannel_ALTAVDD:
2362 EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)
2363 | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)
2364 | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)
2365 | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)
2366 | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0);
2368 case emuVmonChannel_DVDD:
2369 EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)
2370 | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)
2371 | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)
2372 | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)
2373 | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0);
2375 case emuVmonChannel_IOVDD0:
2376 EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)
2377 | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)
2378 | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)
2379 | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)
2380 | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)
2381 | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0);
2400 void EMU_VmonHystInit(
const EMU_VmonHystInit_TypeDef *vmonInit)
2402 uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;
2404 EFM_ASSERT((vmonInit->riseThreshold >= 1200) && (vmonInit->riseThreshold < 4000));
2405 EFM_ASSERT((vmonInit->fallThreshold >= 1200) && (vmonInit->fallThreshold < 4000));
2407 EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold);
2409 riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->riseThreshold);
2410 riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->riseThreshold, riseThresholdCoarse);
2411 fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->fallThreshold);
2412 fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->fallThreshold, fallThresholdCoarse);
2414 switch(vmonInit->channel)
2416 case emuVmonChannel_AVDD:
2417 EMU->VMONAVDDCTRL = (riseThresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
2418 | (riseThresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
2419 | (fallThresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
2420 | (fallThresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
2421 | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
2422 | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
2423 | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
2441 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel,
bool enable)
2443 uint32_t
volatile * reg;
2448 case emuVmonChannel_AVDD:
2449 reg = &(
EMU->VMONAVDDCTRL);
2450 bit = _EMU_VMONAVDDCTRL_EN_SHIFT;
2452 case emuVmonChannel_ALTAVDD:
2453 reg = &(
EMU->VMONALTAVDDCTRL);
2454 bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;
2456 case emuVmonChannel_DVDD:
2457 reg = &(
EMU->VMONDVDDCTRL);
2458 bit = _EMU_VMONDVDDCTRL_EN_SHIFT;
2460 case emuVmonChannel_IOVDD0:
2461 reg = &(
EMU->VMONIO0CTRL);
2462 bit = _EMU_VMONIO0CTRL_EN_SHIFT;
2482 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)
2487 case emuVmonChannel_AVDD:
2488 bit = _EMU_STATUS_VMONAVDD_SHIFT;
2490 case emuVmonChannel_ALTAVDD:
2491 bit = _EMU_STATUS_VMONALTAVDD_SHIFT;
2493 case emuVmonChannel_DVDD:
2494 bit = _EMU_STATUS_VMONDVDD_SHIFT;
2496 case emuVmonChannel_IOVDD0:
2497 bit = _EMU_STATUS_VMONIO0_SHIFT;
2508 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
2522 void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode)
2524 #define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190))
2525 #define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164))
2526 #define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C))
2527 #define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C))
2529 uint32_t freq = 0x2u;
2530 bool emuTestLocked =
false;
2532 if (mode == emuBiasMode_1KHz)
2537 if (EMU_TESTLOCK == 0x1u)
2539 emuTestLocked =
true;
2540 EMU_TESTLOCK = 0xADE8u;
2543 if (mode == emuBiasMode_Continuous)
2545 EMU_BIASCONF &= ~0x74u;
2549 EMU_BIASCONF |= 0x74u;
2552 EMU_BIASTESTCTRL |= 0x8u;
2553 CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u)
2554 | ((freq & 0x3u) << 10u);
2555 EMU_BIASTESTCTRL &= ~0x8u;
Clock management unit (CMU) API.
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
#define CMU_OSCENCMD_LFXODIS
bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit)
Configure DCDC regulator.
__STATIC_INLINE void CMU_Lock(void)
Lock the CMU in order to protect some of its registers against unintended modification.
bool EMU_DCDCPowerOff(void)
Power off the DCDC regulator.
#define _EMU_CTRL_EM4CTRL_MASK
Emlib peripheral API "assert" implementation.
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
Get chip major/minor revision.
#define _ROMTABLE_PID3_REVMINORLSB_MASK
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
static __INLINE void SystemCoreClockUpdate(void)
Update CMSIS SystemCoreClock variable.
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage)
Set DCDC output voltage.
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
#define _EMU_CTRL_EM4CTRL_SHIFT
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
General purpose utilities.
#define CMU_OSCENCMD_LFXOEN
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
#define CMU_OSCENCMD_HFRCOEN
void EMU_Restore(void)
Restore CMU HF clock select state, oscillator enable and voltage scaling (if available) after EMU_Ent...
void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrent_mA)
Optimize DCDC slice count based on the estimated average load current in EM0.
#define CMU_STATUS_USHFRCOENS
#define _ROMTABLE_PID2_REVMINORMSB_MASK
void EMU_RamPowerDown(uint32_t start, uint32_t end)
Power down RAM memory blocks.
uint32_t SystemHFClockGet(void)
Get the current HFCLK frequency.
#define CMU_STATUS_AUXHFRCOENS
void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
Set DCDC Low-noise RCO band.
void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet)
Set DCDC LN regulator conduction mode.
#define CMU_STATUS_HFXOENS
#define CMU_OSCENCMD_USHFRCOEN
void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
#define CMU_OSCENCMD_LFRCOEN
#define CMU_OSCENCMD_HFXOEN
#define CMU_STATUS_HFRCOENS
Energy management unit (EMU) peripheral API.
#define CMU_OSCENCMD_HFRCODIS
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
Set DCDC regulator operating mode.
#define CMU_LOCK_LOCKKEY_LOCKED
#define CMU_STATUS_LFXOENS
#define SL_MIN(a, b)
Macro for getting minimum value. No sideeffects, a and b are evaluated once only. ...
#define SL_MAX(a, b)
Macro for getting maximum value. No sideeffects, a and b are evaluated once only. ...
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
#define _ROMTABLE_PID0_REVMAJOR_MASK
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
Set HFRCO band and the tuning value based on the value in the calibration table made during productio...
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
#define CMU_STATUS_LFRCOENS
__STATIC_INLINE void CMU_Unlock(void)
Unlock the CMU so that writing to locked registers again is possible.
#define CMU_OSCENCMD_AUXHFRCOEN
#define CMU_OSCENCMD_LFRCODIS
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.