EFM32 Happy Gecko Software Documentation  efm32hg-doc-5.1.2
em_emu.h
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1 /***************************************************************************/
33 #ifndef EM_EMU_H
34 #define EM_EMU_H
35 
36 #include "em_device.h"
37 #if defined( EMU_PRESENT )
38 
39 #include <stdbool.h>
40 #include "em_bus.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 /***************************************************************************/
51 /***************************************************************************/
56 /*******************************************************************************
57  ******************************** ENUMS ************************************
58  ******************************************************************************/
59 
60 #if defined( _EMU_EM4CONF_OSC_MASK )
61 
62 typedef enum
63 {
65  emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
67  emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
69  emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
70 } EMU_EM4Osc_TypeDef;
71 #endif
72 
73 #if defined( _EMU_BUCTRL_PROBE_MASK )
74 
75 typedef enum
76 {
78  emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
80  emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
82  emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN,
84  emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT
85 } EMU_Probe_TypeDef;
86 #endif
87 
88 #if defined( _EMU_PWRCONF_PWRRES_MASK )
89 
90 typedef enum
91 {
93  emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
95  emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
97  emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
99  emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
100 } EMU_Resistor_TypeDef;
101 #endif
102 
103 #if defined( BU_PRESENT )
104 
105 typedef enum
106 {
108  emuPower_None = EMU_BUINACT_PWRCON_NONE,
111  emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
114  emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
116  emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
117 } EMU_Power_TypeDef;
118 #endif
119 
121 typedef enum
122 {
124  emuBODMode_Active,
126  emuBODMode_Inactive,
127 } EMU_BODMode_TypeDef;
128 
129 #if defined( _EMU_EM4CTRL_EM4STATE_MASK )
130 
131 typedef enum
132 {
134  emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
136  emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,
137 } EMU_EM4State_TypeDef;
138 #endif
139 
140 
141 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
142 typedef enum
143 {
145  emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
147  emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
150  emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
151 } EMU_EM4PinRetention_TypeDef;
152 #endif
153 
155 typedef enum
156 {
158  emuPowerConfig_DcdcToDvdd,
159 } EMU_PowerConfig_TypeDef;
160 
161 
162 #if defined( _EMU_DCDCCTRL_MASK )
163 
164 typedef enum
165 {
167  emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
169  emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
170 #if defined(_EMU_DCDCLPEM01CFG_MASK)
171 
172  emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER,
173 #endif
174 } EMU_DcdcMode_TypeDef;
175 #endif
176 
177 #if defined( _EMU_DCDCCTRL_MASK )
178 
179 typedef enum
180 {
183  emuDcdcConductionMode_ContinuousLN,
186  emuDcdcConductionMode_DiscontinuousLN,
187 } EMU_DcdcConductionMode_TypeDef;
188 #endif
189 
190 #if defined( _EMU_PWRCTRL_MASK )
191 
192 typedef enum
193 {
195  emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
197  emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
198 } EMU_DcdcAnaPeripheralPower_TypeDef;
199 #endif
200 
201 #if defined( _EMU_DCDCMISCCTRL_MASK )
202 
203 typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
204 
206 #define emuDcdcLnHighEfficiency -1
207 
209 #define emuDcdcLnFastTransient 160
210 #endif
211 
212 
213 #if defined( _EMU_DCDCCTRL_MASK )
214 
215 typedef enum
216 {
218  emuDcdcLnRcoBand_3MHz = 0,
220  emuDcdcLnRcoBand_4MHz = 1,
222  emuDcdcLnRcoBand_5MHz = 2,
224  emuDcdcLnRcoBand_6MHz = 3,
226  emuDcdcLnRcoBand_7MHz = 4,
228  emuDcdcLnRcoBand_8MHz = 5,
230  emuDcdcLnRcoBand_9MHz = 6,
232  emuDcdcLnRcoBand_10MHz = 7,
233 } EMU_DcdcLnRcoBand_TypeDef;
234 
236 /* Deprecated. */
237 #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz
238 #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz
239 #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz
240 #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz
241 #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz
242 #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz
243 #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz
244 #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz
245 
246 #endif
247 
248 
249 #if defined( _EMU_DCDCCTRL_MASK )
250 
251 typedef enum
252 {
254  emuDcdcLnCompCtrl_1u0F,
256  emuDcdcLnCompCtrl_4u7F,
257 } EMU_DcdcLnCompCtrl_TypeDef;
258 #endif
259 
260 
261 #if defined( EMU_STATUS_VMONRDY )
262 
263 typedef enum
264 {
265  emuVmonChannel_AVDD,
266  emuVmonChannel_ALTAVDD,
267  emuVmonChannel_DVDD,
268  emuVmonChannel_IOVDD0
269 } EMU_VmonChannel_TypeDef;
270 #endif /* EMU_STATUS_VMONRDY */
271 
272 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
273 
274 typedef enum
275 {
276  emuBiasMode_1KHz,
277  emuBiasMode_4KHz,
278  emuBiasMode_Continuous
279 } EMU_BiasMode_TypeDef;
280 #endif
281 
282 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
283 
284 typedef enum
285 {
287  emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
293  emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0,
294 } EMU_VScaleEM01_TypeDef;
295 #endif
296 
297 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
298 
299 typedef enum
300 {
302  emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
306  emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
307 } EMU_VScaleEM23_TypeDef;
308 #endif
309 
310 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
311 
312 typedef enum
313 {
315  emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
319  emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
320 } EMU_VScaleEM4H_TypeDef;
321 #endif
322 
323 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
324 
325 typedef enum
326 {
327  emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */
328  emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */
329  emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */
330  emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */
331  emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */
332  emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */
333  emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */
334  emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */
335  emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */
336  emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */
337  emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */
338 #if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
339  emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */
340  emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */
341 #endif
342  emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */
343 
344  emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
345  | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
346  | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
347  | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
348  | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */
349  emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
350  | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
351  | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
352  | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
353  | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
354 #if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
355  | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
356  | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
357 #endif
358  | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK
359  | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */
360  emuPeripheralRetention_ALL = emuPeripheralRetention_D1
361  | emuPeripheralRetention_D2, /* Select all peripherals with retention control */
362 } EMU_PeripheralRetention_TypeDef;
363 #endif
364 
365 /*******************************************************************************
366  ******************************* STRUCTS ***********************************
367  ******************************************************************************/
368 
369 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
370 
373 typedef struct
374 {
375  bool vScaleEM01LowPowerVoltageEnable;
376 } EMU_EM01Init_TypeDef;
377 #endif
378 
379 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
380 
381 #define EMU_EM01INIT_DEFAULT \
382 { \
383  false \
384 }
385 #endif
386 
388 typedef struct
389 {
390  bool em23VregFullEn;
391 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
392  EMU_VScaleEM23_TypeDef vScaleEM23Voltage;
393 #endif
394 } EMU_EM23Init_TypeDef;
395 
397 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
398 #define EMU_EM23INIT_DEFAULT \
399 { \
400  false, /* Reduced voltage regulator drive strength in EM2/3 */ \
401  emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \
402 }
403 #else
404 #define EMU_EM23INIT_DEFAULT \
405 { \
406  false, /* Reduced voltage regulator drive strength in EM2/3 */ \
407 }
408 #endif
409 
410 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
411 
412 typedef struct
413 {
414 #if defined( _EMU_EM4CONF_MASK )
415  /* Init parameters for platforms with EMU->EM4CONF register (Series 0) */
416  bool lockConfig;
417  bool buBodRstDis;
418  EMU_EM4Osc_TypeDef osc;
419  bool buRtcWakeup;
420  bool vreg;
421 #elif defined( _EMU_EM4CTRL_MASK )
422  /* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */
423  bool retainLfxo;
424  bool retainLfrco;
425  bool retainUlfrco;
426  EMU_EM4State_TypeDef em4State;
427  EMU_EM4PinRetention_TypeDef pinRetentionMode;
428 #endif
429 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
430  EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;
431 #endif
432 } EMU_EM4Init_TypeDef;
433 #endif
434 
435 #if defined( _EMU_EM4CONF_MASK )
436 
437 #define EMU_EM4INIT_DEFAULT \
438 { \
439  false, /* Dont't lock configuration after it's been set */ \
440  false, /* No reset will be asserted due to BOD in EM4 */ \
441  emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \
442  true, /* Wake up on EM4 BURTC interrupt */ \
443  true, /* Enable VREG */ \
444 }
445 
446 #elif defined( _EMU_CTRL_EM4HVSCALE_MASK )
447 
448 #define EMU_EM4INIT_DEFAULT \
449 { \
450  false, /* Retain LFXO configuration upon EM4 entry */ \
451  false, /* Retain LFRCO configuration upon EM4 entry */ \
452  false, /* Retain ULFRCO configuration upon EM4 entry */ \
453  emuEM4Shutoff, /* Use EM4 shutoff state */ \
454  emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
455  emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \
456 }
457 
458 #elif defined( _EMU_EM4CTRL_MASK )
459 
460 #define EMU_EM4INIT_DEFAULT \
461 { \
462  false, /* Retain LFXO configuration upon EM4 entry */ \
463  false, /* Retain LFRCO configuration upon EM4 entry */ \
464  false, /* Retain ULFRCO configuration upon EM4 entry */ \
465  emuEM4Shutoff, /* Use EM4 shutoff state */ \
466  emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
467 }
468 #endif
469 
470 #if defined( BU_PRESENT )
471 
472 typedef struct
473 {
474  /* Backup Power Domain power configuration */
475 
477  EMU_Probe_TypeDef probe;
479  bool bodCal;
481  bool statusPinEnable;
482 
483  /* Backup Power Domain connection configuration */
485  EMU_Resistor_TypeDef resistor;
487  bool voutStrong;
489  bool voutMed;
491  bool voutWeak;
493  EMU_Power_TypeDef inactivePower;
495  EMU_Power_TypeDef activePower;
497  bool enable;
498 } EMU_BUPDInit_TypeDef;
499 
501 #define EMU_BUPDINIT_DEFAULT \
502 { \
503  emuProbe_Disable, /* Do not enable voltage probe */ \
504  false, /* Disable BOD calibration mode */ \
505  false, /* Disable BU_STAT pin for backup mode indication */ \
506  \
507  emuRes_Res0, /* RES0 series resistance between main and backup power */ \
508  false, /* Don't enable strong switch */ \
509  false, /* Don't enable medium switch */ \
510  false, /* Don't enable weak switch */ \
511  \
512  emuPower_None, /* No connection between main and backup power (inactive mode) */ \
513  emuPower_None, /* No connection between main and backup power (active mode) */ \
514  true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \
515 }
516 #endif
517 
518 #if defined( _EMU_DCDCCTRL_MASK )
519 
520 typedef struct
521 {
522  EMU_PowerConfig_TypeDef powerConfig;
524  EMU_DcdcMode_TypeDef dcdcMode;
525  uint16_t mVout;
526  uint16_t em01LoadCurrent_mA;
530  uint16_t em234LoadCurrent_uA;
534  uint16_t maxCurrent_mA;
537  EMU_DcdcAnaPeripheralPower_TypeDef
538  anaPeripheralPower;
539  EMU_DcdcLnReverseCurrentControl_TypeDef
540  reverseCurrentControl;
545  EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl;
546 } EMU_DCDCInit_TypeDef;
547 
549 #if defined( _EFM_DEVICE )
550 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
551 #define EMU_DCDCINIT_DEFAULT \
552 { \
553  emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
554  emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
555  1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
556  5, /* Nominal EM0/1 load current of less than 5mA */ \
557  10, /* Nominal EM2/3/4 load current less than 10uA */ \
558  200, /* Maximum average current of 200mA
559  (assume strong battery or other power source) */ \
560  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
561  emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
562  emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \
563 }
564 #else
565 #define EMU_DCDCINIT_DEFAULT \
566 { \
567  emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
568  emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \
569  1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
570  5, /* Nominal EM0/1 load current of less than 5mA */ \
571  10, /* Nominal EM2/3/4 load current less than 10uA */ \
572  200, /* Maximum average current of 200mA
573  (assume strong battery or other power source) */ \
574  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
575  emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
576  emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
577 }
578 #endif
579 
580 #else /* EFR32 device */
581 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
582 #define EMU_DCDCINIT_DEFAULT \
583 { \
584  emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
585  emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
586  1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
587  15, /* Nominal EM0/1 load current of less than 15mA */ \
588  10, /* Nominal EM2/3/4 load current less than 10uA */ \
589  200, /* Maximum average current of 200mA
590  (assume strong battery or other power source) */ \
591  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
592  160, /* Maximum reverse current of 160mA */ \
593  emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \
594 }
595 #else
596 #define EMU_DCDCINIT_DEFAULT \
597 { \
598  emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
599  emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
600  1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
601  15, /* Nominal EM0/1 load current of less than 15mA */ \
602  10, /* Nominal EM2/3/4 load current less than 10uA */ \
603  200, /* Maximum average current of 200mA
604  (assume strong battery or other power source) */ \
605  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
606  160, /* Maximum reverse current of 160mA */ \
607  emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
608 }
609 #endif
610 #endif
611 #endif
612 
613 #if defined( EMU_STATUS_VMONRDY )
614 
615 typedef struct
616 {
617  EMU_VmonChannel_TypeDef channel;
618  int threshold;
619  bool riseWakeup;
620  bool fallWakeup;
621  bool enable;
622  bool retDisable;
623 } EMU_VmonInit_TypeDef;
624 
626 #define EMU_VMONINIT_DEFAULT \
627 { \
628  emuVmonChannel_AVDD, /* AVDD VMON channel */ \
629  3200, /* 3.2 V threshold */ \
630  false, /* Don't wake from EM4H on rising edge */ \
631  false, /* Don't wake from EM4H on falling edge */ \
632  true, /* Enable VMON channel */ \
633  false /* Don't disable IO0 retention */ \
634 }
635 
637 typedef struct
638 {
639  EMU_VmonChannel_TypeDef channel;
640  int riseThreshold;
641  int fallThreshold;
642  bool riseWakeup;
643  bool fallWakeup;
644  bool enable;
645 } EMU_VmonHystInit_TypeDef;
646 
648 #define EMU_VMONHYSTINIT_DEFAULT \
649 { \
650  emuVmonChannel_AVDD, /* AVDD VMON channel */ \
651  3200, /* 3.2 V rise threshold */ \
652  3200, /* 3.2 V fall threshold */ \
653  false, /* Don't wake from EM4H on rising edge */ \
654  false, /* Don't wake from EM4H on falling edge */ \
655  true /* Enable VMON channel */ \
656 }
657 #endif /* EMU_STATUS_VMONRDY */
658 
659 /*******************************************************************************
660  ***************************** PROTOTYPES **********************************
661  ******************************************************************************/
662 
663 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
664 void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init);
665 #endif
666 void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init);
667 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
668 void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
669 #endif
670 void EMU_EnterEM2(bool restore);
671 void EMU_EnterEM3(bool restore);
672 void EMU_Restore(void);
673 void EMU_EnterEM4(void);
674 #if defined( _EMU_EM4CTRL_MASK )
675 void EMU_EnterEM4H(void);
676 void EMU_EnterEM4S(void);
677 #endif
678 void EMU_MemPwrDown(uint32_t blocks);
679 void EMU_RamPowerDown(uint32_t start, uint32_t end);
680 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
681 void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable);
682 #endif
683 void EMU_UpdateOscConfig(void);
684 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
685 void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
686 void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
687 #endif
688 #if defined( BU_PRESENT )
689 void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
690 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
691 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
692 #endif
693 #if defined( _EMU_DCDCCTRL_MASK )
694 bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit);
695 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
696 void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet);
697 bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
698 void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent);
699 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
700 bool EMU_DCDCPowerOff(void);
701 #endif
702 #if defined( EMU_STATUS_VMONRDY )
703 void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit);
704 void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit);
705 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
706 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
707 #endif
708 
709 /***************************************************************************/
713 __STATIC_INLINE void EMU_EnterEM1(void)
714 {
715  /* Enter sleep mode */
716  SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
717  __WFI();
718 }
719 
720 
721 #if defined( _EMU_STATUS_VSCALE_MASK )
722 /***************************************************************************/
726 __STATIC_INLINE void EMU_VScaleWait(void)
727 {
728  while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT));
729 }
730 #endif
731 
732 #if defined( _EMU_STATUS_VSCALE_MASK )
733 /***************************************************************************/
740 __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void)
741 {
742  EMU_VScaleWait();
743  return (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
744  >> _EMU_STATUS_VSCALE_SHIFT);
745 }
746 #endif
747 
748 #if defined( _EMU_STATUS_VMONRDY_MASK )
749 /***************************************************************************/
757 __STATIC_INLINE bool EMU_VmonStatusGet(void)
758 {
759  return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT);
760 }
761 #endif /* _EMU_STATUS_VMONRDY_MASK */
762 
763 #if defined( _EMU_IF_MASK )
764 /***************************************************************************/
772 __STATIC_INLINE void EMU_IntClear(uint32_t flags)
773 {
774  EMU->IFC = flags;
775 }
776 
777 
778 /***************************************************************************/
786 __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
787 {
788  EMU->IEN &= ~flags;
789 }
790 
791 
792 /***************************************************************************/
805 __STATIC_INLINE void EMU_IntEnable(uint32_t flags)
806 {
807  EMU->IEN |= flags;
808 }
809 
810 
811 /***************************************************************************/
822 __STATIC_INLINE uint32_t EMU_IntGet(void)
823 {
824  return EMU->IF;
825 }
826 
827 
828 /***************************************************************************/
842 __STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
843 {
844  uint32_t ien;
845 
846  ien = EMU->IEN;
847  return EMU->IF & ien;
848 }
849 
850 
851 /***************************************************************************/
859 __STATIC_INLINE void EMU_IntSet(uint32_t flags)
860 {
861  EMU->IFS = flags;
862 }
863 #endif /* _EMU_IF_MASK */
864 
865 
866 #if defined( _EMU_EM4CONF_LOCKCONF_MASK )
867 /***************************************************************************/
873 __STATIC_INLINE void EMU_EM4Lock(bool enable)
874 {
875  BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
876 }
877 #endif
878 
879 #if defined( _EMU_STATUS_BURDY_MASK )
880 /***************************************************************************/
884 __STATIC_INLINE void EMU_BUReady(void)
885 {
886  while(!(EMU->STATUS & EMU_STATUS_BURDY))
887  ;
888 }
889 #endif
890 
891 #if defined( _EMU_ROUTE_BUVINPEN_MASK )
892 /***************************************************************************/
898 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
899 {
900  BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
901 }
902 #endif
903 
904 /***************************************************************************/
916 __STATIC_INLINE void EMU_Lock(void)
917 {
918  EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK;
919 }
920 
921 
922 /***************************************************************************/
926 __STATIC_INLINE void EMU_Unlock(void)
927 {
928  EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
929 }
930 
931 
932 #if defined( _EMU_PWRLOCK_MASK )
933 /***************************************************************************/
938 __STATIC_INLINE void EMU_PowerLock(void)
939 {
940  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
941 }
942 
943 
944 /***************************************************************************/
949 __STATIC_INLINE void EMU_PowerUnlock(void)
950 {
951  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
952 }
953 #endif
954 
955 
956 /***************************************************************************/
960 __STATIC_INLINE void EMU_EM2Block(void)
961 {
962  BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
963 }
964 
965 /***************************************************************************/
969 __STATIC_INLINE void EMU_EM2UnBlock(void)
970 {
971  BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
972 }
973 
974 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
975 /***************************************************************************/
983 __STATIC_INLINE void EMU_UnlatchPinRetention(void)
984 {
985  EMU->CMD = EMU_CMD_EM4UNLATCH;
986 }
987 #endif
988 
989 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
990 void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
991 #endif
992 
996 #ifdef __cplusplus
997 }
998 #endif
999 
1000 #endif /* defined( EMU_PRESENT ) */
1001 #endif /* EM_EMU_H */
EMU_DCDCInit
bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit)
Configure DCDC regulator.
Definition: em_emu.c:1869
EMU_DCDCPowerOff
bool EMU_DCDCPowerOff(void)
Power off the DCDC regulator.
Definition: em_emu.c:2288
EMU_EnterEM4
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
Definition: em_emu.c:705
em_bus.h
RAM and peripheral bit-field set and clear API.
EMU_MemPwrDown
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
Definition: em_emu.c:825
EMU_EnterEM3
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
Definition: em_emu.c:597
EMU_EnterEM2
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
Definition: em_emu.c:480
EMU_DCDCOutputVoltageSet
bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage)
Set DCDC output voltage.
Definition: em_emu.c:2020
em_device.h
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
BUS_RegBitRead
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
Definition: em_bus.h:187
EMU_PowerConfig_TypeDef
EMU_PowerConfig_TypeDef
Definition: em_emu.h:155
EMU_Unlock
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
Definition: em_emu.h:926
EMU_Lock
__STATIC_INLINE void EMU_Lock(void)
Lock the EMU in order to protect its registers against unintended modification.
Definition: em_emu.h:916
EMU_Restore
void EMU_Restore(void)
Restore CMU HF clock select state, oscillator enable and voltage scaling (if available) after EMU_Ent...
Definition: em_emu.c:692
EMU_DCDCOptimizeSlice
void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrent_mA)
Optimize DCDC slice count based on the estimated average load current in EM0.
Definition: em_emu.c:2184
EMU_BODMode_TypeDef
EMU_BODMode_TypeDef
Definition: em_emu.h:121
EMU_RamPowerDown
void EMU_RamPowerDown(uint32_t start, uint32_t end)
Power down RAM memory blocks.
Definition: em_emu.c:870
EMU_EnterEM1
__STATIC_INLINE void EMU_EnterEM1(void)
Enter energy mode 1 (EM1).
Definition: em_emu.h:713
EMU_DCDCLnRcoBandSet
void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
Set DCDC Low-noise RCO band.
Definition: em_emu.c:2260
EMU_DCDCConductionModeSet
void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet)
Set DCDC LN regulator conduction mode.
Definition: em_emu.c:1813
emuPowerConfig_DcdcToDvdd
Definition: em_emu.h:158
EMU_LOCK_LOCKKEY_UNLOCK
#define EMU_LOCK_LOCKKEY_UNLOCK
Definition: efm32hg_emu.h:93
EMU_EM2UnBlock
__STATIC_INLINE void EMU_EM2UnBlock(void)
Unblock entering EM2 or higher number energy modes.
Definition: em_emu.h:969
EMU_EM23Init
void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
Definition: em_emu.c:1078
EMU_LOCK_LOCKKEY_LOCK
#define EMU_LOCK_LOCKKEY_LOCK
Definition: efm32hg_emu.h:90
EMU_DCDCModeSet
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
Set DCDC regulator operating mode.
Definition: em_emu.c:1760
EMU_EM23Init_TypeDef::em23VregFullEn
bool em23VregFullEn
Definition: em_emu.h:390
emuBODMode_Active
Definition: em_emu.h:124
EMU
#define EMU
Definition: efm32hg322f64.h:323
BUS_RegBitWrite
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
emuBODMode_Inactive
Definition: em_emu.h:126
EMU_UpdateOscConfig
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
Definition: em_emu.c:958
_EMU_CTRL_EM2BLOCK_SHIFT
#define _EMU_CTRL_EM2BLOCK_SHIFT
Definition: efm32hg_emu.h:70
EMU_EM2Block
__STATIC_INLINE void EMU_EM2Block(void)
Block entering EM2 or higher number energy modes.
Definition: em_emu.h:960
EMU_EM23Init_TypeDef
Definition: em_emu.h:388