35 #if defined(EMLIB_USER_CONFIG)
36 #include "emlib_config.h"
267 #if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL)
271 #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3
274 #if !defined(CORE_ATOMIC_METHOD)
278 #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK
281 #if !defined(CORE_INTERRUPT_ENTRY)
287 #define CORE_INTERRUPT_ENTRY()
290 #if !defined(CORE_INTERRUPT_EXIT)
293 #define CORE_INTERRUPT_EXIT()
297 #if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \
298 && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI)
299 #error "em_core: Undefined ATOMIC IRQ handling strategy."
372 if (__get_PRIMASK() & 1) {
392 #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
396 #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
416 #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
420 #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
439 #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
447 #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
465 #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
466 __set_BASEPRI(irqState);
471 #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
488 #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
492 __set_BASEPRI(basepri);
495 if (__get_PRIMASK() & 1) {
499 #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
574 #if (CORE_NVIC_REG_WORDS == 1)
575 nvicMask.
a[0] &= enable->
a[0];
576 nvicMask.
a[0] = ~nvicMask.
a[0] & enable->
a[0];
578 if (nvicMask.
a[0] != 0) {
580 #elif (CORE_NVIC_REG_WORDS == 2)
581 nvicMask.
a[0] &= enable->
a[0];
582 nvicMask.
a[1] &= enable->
a[1];
583 nvicMask.
a[0] = ~nvicMask.
a[0] & enable->
a[0];
584 nvicMask.
a[1] = ~nvicMask.
a[1] & enable->
a[1];
586 if ((nvicMask.
a[0] != 0) || (nvicMask.
a[1] != 0)) {
588 #elif (CORE_NVIC_REG_WORDS == 3)
589 nvicMask.
a[0] &= enable->
a[0];
590 nvicMask.
a[1] &= enable->
a[1];
591 nvicMask.
a[2] &= enable->
a[2];
592 nvicMask.
a[0] = ~nvicMask.
a[0] & enable->
a[0];
593 nvicMask.
a[1] = ~nvicMask.
a[1] & enable->
a[1];
594 nvicMask.
a[2] = ~nvicMask.
a[2] & enable->
a[2];
596 if ((nvicMask.
a[0] != 0) || (nvicMask.
a[1] != 0) || (nvicMask.
a[2] != 0)) {
620 mask->
a[irqN >> 5] |= 1 << (irqN & 0x1F);
636 mask->
a[irqN >> 5] &= ~(1 << (irqN & 0x1F));
649 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0;
664 uint32_t irqPri, activeIrq;
666 #if (__CORTEX_M >= 3)
669 EFM_ASSERT((irqN >= MemoryManagement_IRQn) && (irqN <
EXT_IRQ_COUNT));
674 if (__get_PRIMASK() & 1) {
682 irqPri = NVIC_GetPriority(irqN);
683 #if (__CORTEX_M >= 3)
684 basepri = __get_BASEPRI();
693 activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos;
695 && (irqPri >= NVIC_GetPriority((
IRQn_Type)(activeIrq - 16)))) {
711 #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_PRIMASK)
712 return (__get_PRIMASK() & 1) == 1;
714 #elif (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI)
715 return ((__get_PRIMASK() & 1) == 1)
754 #if (CORE_NVIC_REG_WORDS == 1)
755 return (mask->
a[0] & nvicMask.
a[0]) == 0;
757 #elif (CORE_NVIC_REG_WORDS == 2)
758 return ((mask->
a[0] & nvicMask.
a[0]) == 0)
759 && ((mask->
a[1] & nvicMask.
a[1]) == 0);
761 #elif (CORE_NVIC_REG_WORDS == 3)
762 return ((mask->
a[0] & nvicMask.
a[0]) == 0)
763 && ((mask->
a[1] & nvicMask.
a[1]) == 0)
764 && ((mask->
a[2] & nvicMask.
a[2]) == 0);
784 return (mask->
a[irqN >> 5] & (1 << (irqN & 0x1F))) == 0;
803 return (
void*)(((uint32_t*)SCB->VTOR)[irqN+16]);
822 ((uint32_t*)SCB->VTOR)[irqN+16] = (uint32_t)handler;
858 uint32_t *targetTable,
860 void *defaultHandler,
861 bool overwriteActive)
870 #if defined(SCB_VTOR_TBLBASE_Msk)
871 EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk
872 | SCB_VTOR_TBLBASE_Msk)) == 0);
874 EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0);
879 EFM_ASSERT(((uint32_t)targetTable
880 & ((1 << (32 - __CLZ((targetSize * 4) - 1))) - 1)) == 0);
882 for (i=0; i<targetSize; i++) {
883 if (overwriteActive) {
885 targetTable[i] = sourceTable[i];
887 targetTable[i] = (uint32_t)defaultHandler;
891 if (targetTable[i] == 0) {
892 targetTable[i] = sourceTable[i];
895 if (targetTable[i] == 0) {
896 targetTable[i] = (uint32_t)defaultHandler;
901 SCB->VTOR = (uint32_t)targetTable;
bool CORE_NvicIRQDisabled(IRQn_Type irqN)
Check if a NVIC interrupt is disabled.
void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)
Utility function to set the handler for a specific interrupt.
void CORE_CriticalDisableIrq(void)
Disable interrupts.
Emlib peripheral API "assert" implementation.
uint32_t a[CORE_NVIC_REG_WORDS]
void CORE_YieldAtomic(void)
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
void CORE_NvicDisableMask(const CORE_nvicMask_t *disable)
Disable NVIC interrupts.
bool CORE_InIrqContext(void)
Check if current cpu operation mode is handler mode.
bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask)
Get NVIC disable state for a given mask.
void CORE_ExitAtomic(CORE_irqState_t irqState)
Exit an ATOMIC section.
#define CORE_CRITICAL_SECTION(yourcode)
void CORE_YieldCritical(void)
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
#define SL_WEAK
Macro for defining a weak symbol.
void CORE_CriticalEnableIrq(void)
Enable interrupts.
#define CORE_ATOMIC_BASE_PRIORITY_LEVEL
Core interrupt handling API.
CORE_irqState_t CORE_EnterCritical(void)
Enter a CRITICAL section.
void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask)
Get current NVIC enable mask state.
void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)
Enter a NVIC mask section.
bool CORE_IrqIsBlocked(IRQn_Type irqN)
Check if a specific interrupt is disabled or blocked.
bool CORE_IrqIsDisabled(void)
Check if interrupts are disabled.
void CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)
Initialize an interrupt vector table by copying table entries from a source to a target table...
void * CORE_GetNvicRamTableHandler(IRQn_Type irqN)
Utility function to get the handler for a specific interrupt.
void CORE_AtomicEnableIrq(void)
Enable interrupts.
void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)
Utility function to set an IRQn bit in a NVIC enable/disable mask.
void CORE_NvicEnableMask(const CORE_nvicMask_t *enable)
Set current NVIC interrupt enable mask.
void CORE_ExitCritical(CORE_irqState_t irqState)
Exit a CRITICAL section.
void CORE_AtomicDisableIrq(void)
Disable interrupts.
CORE_irqState_t CORE_EnterAtomic(void)
Enter an ATOMIC section.