34 #if defined( MSC_COUNT ) && ( MSC_COUNT > 0 )
37 #if defined( _MSC_TIMEBASE_MASK )
44 #if defined(__ICCARM__)
47 #pragma diag_suppress=Ta022
50 #if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY)
51 #error "Running Flash write/erase operations from Flash is not supported on EFM32G."
54 #if defined( MSC_WRITECTRL_WDOUBLE )
55 #define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2)
57 #define WORDS_PER_DATA_PHASE (1)
60 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
62 #define ERRATA_FIX_FLASH_E201_EN
68 } MSC_WriteStrategy_Typedef;
71 MSC_WriteWordI(uint32_t *address,
74 MSC_WriteStrategy_Typedef writeStrategy);
77 MSC_LoadWriteData(uint32_t* data,
79 MSC_WriteStrategy_Typedef writeStrategy);
82 MSC_LoadVerifyAddress(uint32_t* address);
84 #if !defined(EM_MSC_RUN_FROM_FLASH)
106 void mscRfAssertEFM(
const char *file,
int line)
119 #if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER)
120 #define EFM_ASSERT(expr) ((expr) ? ((void)0) : mscRfAssertEFM(__FILE__, __LINE__))
122 #define EFM_ASSERT(expr) ((void)(expr))
159 #if defined( _MSC_TIMEBASE_MASK )
160 uint32_t freq, cycles;
163 #if defined( _EMU_STATUS_VSCALE_MASK )
165 EFM_ASSERT(!(
EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
166 EFM_ASSERT((
EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
181 #if defined( _MSC_TIMEBASE_MASK )
190 freq = (freq * 11) / 10;
191 cycles = (freq / 1000000) + 1;
194 MSC->TIMEBASE = (
MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK
195 | _MSC_TIMEBASE_PERIOD_MASK))
196 | MSC_TIMEBASE_PERIOD_1US
197 | (cycles << _MSC_TIMEBASE_BASE_SHIFT);
202 freq = (freq * 5 * 11) / 10;
203 cycles = (freq / 1000000) + 1;
206 MSC->TIMEBASE = (
MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK
207 | _MSC_TIMEBASE_PERIOD_MASK))
208 | MSC_TIMEBASE_PERIOD_5US
209 | (cycles << _MSC_TIMEBASE_BASE_SHIFT);
236 uint32_t mscReadCtrl;
238 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
262 mscReadCtrl =
MSC->READCTRL & ~(0
263 #if defined( MSC_READCTRL_SCBTP )
266 #if defined( MSC_READCTRL_USEHPROT )
267 | MSC_READCTRL_USEHPROT
269 #if defined( MSC_READCTRL_PREFETCH )
270 | MSC_READCTRL_PREFETCH
272 #if defined( MSC_READCTRL_ICCDIS )
273 | MSC_READCTRL_ICCDIS
275 #if defined( MSC_READCTRL_AIDIS )
278 #if defined( MSC_READCTRL_IFCDIS )
279 | MSC_READCTRL_IFCDIS
283 #if defined( MSC_READCTRL_SCBTP )
284 | (execConfig->
scbtEn ? MSC_READCTRL_SCBTP : 0)
286 #
if defined( MSC_READCTRL_USEHPROT )
287 | (execConfig->
useHprot ? MSC_READCTRL_USEHPROT : 0)
289 #
if defined( MSC_READCTRL_PREFETCH )
290 | (execConfig->
prefetchEn ? MSC_READCTRL_PREFETCH : 0)
292 #
if defined( MSC_READCTRL_ICCDIS )
293 | (execConfig->
iccDis ? MSC_READCTRL_ICCDIS : 0)
295 #
if defined( MSC_READCTRL_AIDIS )
296 | (execConfig->
aiDis ? MSC_READCTRL_AIDIS : 0)
298 #
if defined( MSC_READCTRL_IFCDIS )
299 | (execConfig->
ifcDis ? MSC_READCTRL_IFCDIS : 0)
303 MSC->READCTRL = mscReadCtrl;
347 MSC->ADDRB = (uint32_t)address;
350 status =
MSC->STATUS;
388 MSC_WriteStrategy_Typedef writeStrategy)
392 bool useWDouble =
false;
394 #if !defined( _EFM32_GECKO_FAMILY )
398 #if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
400 if (!(
MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE))
402 #if defined(_SILICON_LABS_32B_SERIES_0)
419 MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
421 MSC->WDATA = *data++;
443 MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE;
452 if (writeStrategy == mscWriteIntSafe)
457 while(wordIndex < numWords)
461 MSC->WDATA = *data++;
469 #if defined(_SILICON_LABS_32B_SERIES_0)
470 MSC->WDATA = *data++;
472 MSC->WDATA = *data++;
476 #elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
480 MSC->WDATA = *data++;
483 && (wordIndex < numWords));
500 #if defined( _EFM32_GECKO_FAMILY )
510 #if defined( _EFM32_GECKO_FAMILY )
521 irqState = __get_PRIMASK();
525 while(wordIndex < numWords)
559 #if defined(_SILICON_LABS_32B_SERIES_0)
568 #elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
571 MSC->WDATA = *data++;
574 && (wordIndex < numWords));
601 #if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
603 MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
629 MSC_WriteStrategy_Typedef writeStrategy)
638 EFM_ASSERT(((uint32_t) address & 0x3) == 0);
641 EFM_ASSERT((numBytes & 0x3) == 0);
643 #if defined( _EMU_STATUS_VSCALE_MASK )
645 EFM_ASSERT(!(
EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
646 EFM_ASSERT((
EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
653 numWords = numBytes >> 2;
654 EFM_ASSERT(numWords > 0);
659 for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; )
663 retval = MSC_LoadVerifyAddress(address + wordCount);
673 if (pageWords > numWords - wordCount)
675 pageWords = numWords - wordCount;
678 retval = MSC_LoadWriteData(pData, pageWords, writeStrategy);
683 wordCount += pageWords;
687 #if defined( ERRATA_FIX_FLASH_E201_EN )
694 pData = (uint32_t *) data;
695 if (*address != *pData)
697 retval = MSC_LoadVerifyAddress(address);
700 retval = MSC_LoadWriteData(pData, 1, writeStrategy);
708 #if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
709 #if ( WORDS_PER_DATA_PHASE == 2 )
711 MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
754 #if defined( _EMU_STATUS_VSCALE_MASK )
756 EFM_ASSERT(!(
EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
757 EFM_ASSERT((
EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
764 MSC->ADDRB = (uint32_t)startAddress;
843 return MSC_WriteWordI(address, data, numBytes, mscWriteIntSafe);
848 #if !defined( _EFM32_GECKO_FAMILY )
887 return MSC_WriteWordI(address, data, numBytes, mscWriteFast);
894 #if defined( _MSC_MASSLOCK_MASK )
912 MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK;
915 MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0;
920 #if ((FLASH_SIZE >= (512 * 1024)) && defined( _MSC_WRITECMD_ERASEMAIN1_MASK ))
922 MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1;
929 MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK;
Clock management unit (CMU) API.
#define MSC_STATUS_LOCKED
Emlib peripheral API "assert" implementation.
#define MSC_READCTRL_MODE_WS0
uint32_t SystemCoreClock
System System Clock Frequency (Core Clock).
uint32_t SystemCoreClockGet(void)
Get the current core clock frequency.
void MSC_Init(void)
Enables the flash controller for writing.
void MSC_Deinit(void)
Disables the flash controller for writing.
#define MSC_RAMFUNC_DEFINITION_END
Expands to SL_RAMFUNC_DEFINITION_END if EM_MSC_RUN_FROM_FLASH is undefined and to nothing if EM_MSC_R...
#define MSC_WRITECMD_LADDRIM
#define MSC_PROGRAM_TIMEOUT
The timeout used while waiting for the flash to become ready after a write. This number indicates the...
#define MSC_WRITECMD_WRITEONCE
#define MSC_READCTRL_MODE_WS1
void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig)
Set MSC code execution configuration.
Flash controller (MSC) peripheral API.
#define MSC_STATUS_WDATAREADY
#define MSC_WRITECTRL_WREN
#define MSC_STATUS_WORDTIMEOUT
#define MSC_RAMFUNC_DECLARATOR
Expands to SL_RAMFUNC_DECLARATOR if EM_MSC_RUN_FROM_FLASH is undefined and to nothing if EM_MSC_RUN_F...
#define MSC_STATUS_INVADDR
#define MSC_WRITECMD_WRITETRIG
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes)
Writes data to flash memory. This function is interrupt safe, but slower than MSC_WriteWordFast(), which writes to flash with interrupts disabled. Write data must be aligned to words and contain a number of bytes that is divisable by four.
#define _MSC_READCTRL_MODE_MASK
#define MSC_RAMFUNC_DEFINITION_BEGIN
Expands to SL_RAMFUNC_DEFINITION_BEGIN if EM_MSC_RUN_FROM_FLASH is undefined and to nothing if EM_MSC...
#define MSC_READCTRL_MODE_WS1SCBTP
#define MSC_WRITECMD_ERASEPAGE
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
#define MSC_READCTRL_MODE_WS0SCBTP
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress)
Erases a page in flash memory.