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efm32g_msc.h
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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typedef
struct
42
{
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__IOM uint32_t
CTRL
;
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__IOM uint32_t
READCTRL
;
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__IOM uint32_t
WRITECTRL
;
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__IOM uint32_t
WRITECMD
;
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__IOM uint32_t
ADDRB
;
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uint32_t RESERVED0[1];
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__IOM uint32_t
WDATA
;
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__IM uint32_t
STATUS
;
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uint32_t RESERVED1[3];
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__IM uint32_t
IF
;
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__IOM uint32_t
IFS
;
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__IOM uint32_t
IFC
;
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__IOM uint32_t
IEN
;
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__IOM uint32_t
LOCK
;
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}
MSC_TypeDef
;
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/**************************************************************************/
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/* Bit fields for MSC CTRL */
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#define _MSC_CTRL_RESETVALUE 0x00000001UL
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#define _MSC_CTRL_MASK 0x00000001UL
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#define MSC_CTRL_BUSFAULT (0x1UL << 0)
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#define _MSC_CTRL_BUSFAULT_SHIFT 0
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#define _MSC_CTRL_BUSFAULT_MASK 0x1UL
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#define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
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#define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
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#define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
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#define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
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#define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
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#define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
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/* Bit fields for MSC READCTRL */
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#define _MSC_READCTRL_RESETVALUE 0x00000001UL
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#define _MSC_READCTRL_MASK 0x00000007UL
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#define _MSC_READCTRL_MODE_SHIFT 0
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#define _MSC_READCTRL_MODE_MASK 0x7UL
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#define _MSC_READCTRL_MODE_WS0 0x00000000UL
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#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
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#define _MSC_READCTRL_MODE_WS1 0x00000001UL
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#define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL
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#define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL
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#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
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#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
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#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
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#define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0)
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#define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0)
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/* Bit fields for MSC WRITECTRL */
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#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
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#define _MSC_WRITECTRL_MASK 0x00000003UL
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#define MSC_WRITECTRL_WREN (0x1UL << 0)
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#define _MSC_WRITECTRL_WREN_SHIFT 0
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#define _MSC_WRITECTRL_WREN_MASK 0x1UL
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#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
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#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
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#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
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#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
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#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
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#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
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#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
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/* Bit fields for MSC WRITECMD */
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#define _MSC_WRITECMD_RESETVALUE 0x00000000UL
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#define _MSC_WRITECMD_MASK 0x0000001FUL
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#define MSC_WRITECMD_LADDRIM (0x1UL << 0)
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#define _MSC_WRITECMD_LADDRIM_SHIFT 0
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#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
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#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
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#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
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#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
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#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
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#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
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#define MSC_WRITECMD_WRITEEND (0x1UL << 2)
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#define _MSC_WRITECMD_WRITEEND_SHIFT 2
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#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
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#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
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#define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
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#define _MSC_WRITECMD_WRITEONCE_SHIFT 3
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#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
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#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
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#define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
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#define _MSC_WRITECMD_WRITETRIG_SHIFT 4
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#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
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#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
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/* Bit fields for MSC ADDRB */
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#define _MSC_ADDRB_RESETVALUE 0x00000000UL
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#define _MSC_ADDRB_MASK 0xFFFFFFFFUL
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#define _MSC_ADDRB_ADDRB_SHIFT 0
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#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
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#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
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#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
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/* Bit fields for MSC WDATA */
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#define _MSC_WDATA_RESETVALUE 0x00000000UL
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#define _MSC_WDATA_MASK 0xFFFFFFFFUL
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#define _MSC_WDATA_WDATA_SHIFT 0
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#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
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#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
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#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
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/* Bit fields for MSC STATUS */
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#define _MSC_STATUS_RESETVALUE 0x00000008UL
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#define _MSC_STATUS_MASK 0x0000003FUL
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#define MSC_STATUS_BUSY (0x1UL << 0)
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#define _MSC_STATUS_BUSY_SHIFT 0
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#define _MSC_STATUS_BUSY_MASK 0x1UL
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#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
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#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
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#define MSC_STATUS_LOCKED (0x1UL << 1)
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#define _MSC_STATUS_LOCKED_SHIFT 1
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#define _MSC_STATUS_LOCKED_MASK 0x2UL
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#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
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#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
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#define MSC_STATUS_INVADDR (0x1UL << 2)
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#define _MSC_STATUS_INVADDR_SHIFT 2
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#define _MSC_STATUS_INVADDR_MASK 0x4UL
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#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
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#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
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#define MSC_STATUS_WDATAREADY (0x1UL << 3)
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#define _MSC_STATUS_WDATAREADY_SHIFT 3
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#define _MSC_STATUS_WDATAREADY_MASK 0x8UL
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#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
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#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
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#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
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#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
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#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
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#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
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#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
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#define MSC_STATUS_ERASEABORTED (0x1UL << 5)
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#define _MSC_STATUS_ERASEABORTED_SHIFT 5
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#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
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#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
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#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
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/* Bit fields for MSC IF */
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#define _MSC_IF_RESETVALUE 0x00000000UL
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#define _MSC_IF_MASK 0x00000003UL
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#define MSC_IF_ERASE (0x1UL << 0)
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#define _MSC_IF_ERASE_SHIFT 0
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#define _MSC_IF_ERASE_MASK 0x1UL
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#define _MSC_IF_ERASE_DEFAULT 0x00000000UL
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#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
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#define MSC_IF_WRITE (0x1UL << 1)
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#define _MSC_IF_WRITE_SHIFT 1
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#define _MSC_IF_WRITE_MASK 0x2UL
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#define _MSC_IF_WRITE_DEFAULT 0x00000000UL
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#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
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/* Bit fields for MSC IFS */
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#define _MSC_IFS_RESETVALUE 0x00000000UL
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#define _MSC_IFS_MASK 0x00000003UL
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#define MSC_IFS_ERASE (0x1UL << 0)
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#define _MSC_IFS_ERASE_SHIFT 0
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#define _MSC_IFS_ERASE_MASK 0x1UL
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#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
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#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
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#define MSC_IFS_WRITE (0x1UL << 1)
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#define _MSC_IFS_WRITE_SHIFT 1
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#define _MSC_IFS_WRITE_MASK 0x2UL
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#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
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#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
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/* Bit fields for MSC IFC */
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#define _MSC_IFC_RESETVALUE 0x00000000UL
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#define _MSC_IFC_MASK 0x00000003UL
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#define MSC_IFC_ERASE (0x1UL << 0)
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#define _MSC_IFC_ERASE_SHIFT 0
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#define _MSC_IFC_ERASE_MASK 0x1UL
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#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
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#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
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#define MSC_IFC_WRITE (0x1UL << 1)
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#define _MSC_IFC_WRITE_SHIFT 1
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#define _MSC_IFC_WRITE_MASK 0x2UL
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#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
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#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
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/* Bit fields for MSC IEN */
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#define _MSC_IEN_RESETVALUE 0x00000000UL
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#define _MSC_IEN_MASK 0x00000003UL
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#define MSC_IEN_ERASE (0x1UL << 0)
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#define _MSC_IEN_ERASE_SHIFT 0
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#define _MSC_IEN_ERASE_MASK 0x1UL
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#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
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#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
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#define MSC_IEN_WRITE (0x1UL << 1)
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#define _MSC_IEN_WRITE_SHIFT 1
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#define _MSC_IEN_WRITE_MASK 0x2UL
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#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
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#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
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/* Bit fields for MSC LOCK */
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#define _MSC_LOCK_RESETVALUE 0x00000000UL
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#define _MSC_LOCK_MASK 0x0000FFFFUL
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#define _MSC_LOCK_LOCKKEY_SHIFT 0
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#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
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#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
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#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
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#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
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#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
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#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
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#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
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#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
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#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
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#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
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#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
MSC_TypeDef::LOCK
__IOM uint32_t LOCK
Definition:
efm32g_msc.h:56
MSC_TypeDef::IEN
__IOM uint32_t IEN
Definition:
efm32g_msc.h:55
MSC_TypeDef::STATUS
__IM uint32_t STATUS
Definition:
efm32g_msc.h:50
MSC_TypeDef::WDATA
__IOM uint32_t WDATA
Definition:
efm32g_msc.h:49
MSC_TypeDef::READCTRL
__IOM uint32_t READCTRL
Definition:
efm32g_msc.h:44
MSC_TypeDef::IFC
__IOM uint32_t IFC
Definition:
efm32g_msc.h:54
MSC_TypeDef::ADDRB
__IOM uint32_t ADDRB
Definition:
efm32g_msc.h:47
MSC_TypeDef::IFS
__IOM uint32_t IFS
Definition:
efm32g_msc.h:53
MSC_TypeDef::WRITECTRL
__IOM uint32_t WRITECTRL
Definition:
efm32g_msc.h:45
MSC_TypeDef
Definition:
efm32g_msc.h:41
MSC_TypeDef::CTRL
__IOM uint32_t CTRL
Definition:
efm32g_msc.h:43
MSC_TypeDef::IF
__IM uint32_t IF
Definition:
efm32g_msc.h:52
MSC_TypeDef::WRITECMD
__IOM uint32_t WRITECMD
Definition:
efm32g_msc.h:46
platform
Device
SiliconLabs
EFM32G
Include
efm32g_msc.h
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