EFM32 Gecko Software Documentation  efm32g-doc-5.1.2
efm32g_msc.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IOM uint32_t READCTRL;
45  __IOM uint32_t WRITECTRL;
46  __IOM uint32_t WRITECMD;
47  __IOM uint32_t ADDRB;
48  uint32_t RESERVED0[1];
49  __IOM uint32_t WDATA;
50  __IM uint32_t STATUS;
51  uint32_t RESERVED1[3];
52  __IM uint32_t IF;
53  __IOM uint32_t IFS;
54  __IOM uint32_t IFC;
55  __IOM uint32_t IEN;
56  __IOM uint32_t LOCK;
57 } MSC_TypeDef;
59 /**************************************************************************/
64 /* Bit fields for MSC CTRL */
65 #define _MSC_CTRL_RESETVALUE 0x00000001UL
66 #define _MSC_CTRL_MASK 0x00000001UL
67 #define MSC_CTRL_BUSFAULT (0x1UL << 0)
68 #define _MSC_CTRL_BUSFAULT_SHIFT 0
69 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL
70 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
71 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
72 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
73 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
74 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
75 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
77 /* Bit fields for MSC READCTRL */
78 #define _MSC_READCTRL_RESETVALUE 0x00000001UL
79 #define _MSC_READCTRL_MASK 0x00000007UL
80 #define _MSC_READCTRL_MODE_SHIFT 0
81 #define _MSC_READCTRL_MODE_MASK 0x7UL
82 #define _MSC_READCTRL_MODE_WS0 0x00000000UL
83 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
84 #define _MSC_READCTRL_MODE_WS1 0x00000001UL
85 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL
86 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL
87 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
88 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
89 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
90 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0)
91 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0)
93 /* Bit fields for MSC WRITECTRL */
94 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
95 #define _MSC_WRITECTRL_MASK 0x00000003UL
96 #define MSC_WRITECTRL_WREN (0x1UL << 0)
97 #define _MSC_WRITECTRL_WREN_SHIFT 0
98 #define _MSC_WRITECTRL_WREN_MASK 0x1UL
99 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
100 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
101 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
102 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
103 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
104 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
105 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
107 /* Bit fields for MSC WRITECMD */
108 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL
109 #define _MSC_WRITECMD_MASK 0x0000001FUL
110 #define MSC_WRITECMD_LADDRIM (0x1UL << 0)
111 #define _MSC_WRITECMD_LADDRIM_SHIFT 0
112 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
113 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
114 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
115 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
116 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
117 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
118 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
119 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
120 #define MSC_WRITECMD_WRITEEND (0x1UL << 2)
121 #define _MSC_WRITECMD_WRITEEND_SHIFT 2
122 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
123 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
124 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
125 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
126 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3
127 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
128 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
129 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
130 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
131 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4
132 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
133 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
134 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
136 /* Bit fields for MSC ADDRB */
137 #define _MSC_ADDRB_RESETVALUE 0x00000000UL
138 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL
139 #define _MSC_ADDRB_ADDRB_SHIFT 0
140 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
141 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
142 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
144 /* Bit fields for MSC WDATA */
145 #define _MSC_WDATA_RESETVALUE 0x00000000UL
146 #define _MSC_WDATA_MASK 0xFFFFFFFFUL
147 #define _MSC_WDATA_WDATA_SHIFT 0
148 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
149 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
150 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
152 /* Bit fields for MSC STATUS */
153 #define _MSC_STATUS_RESETVALUE 0x00000008UL
154 #define _MSC_STATUS_MASK 0x0000003FUL
155 #define MSC_STATUS_BUSY (0x1UL << 0)
156 #define _MSC_STATUS_BUSY_SHIFT 0
157 #define _MSC_STATUS_BUSY_MASK 0x1UL
158 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
159 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
160 #define MSC_STATUS_LOCKED (0x1UL << 1)
161 #define _MSC_STATUS_LOCKED_SHIFT 1
162 #define _MSC_STATUS_LOCKED_MASK 0x2UL
163 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
164 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
165 #define MSC_STATUS_INVADDR (0x1UL << 2)
166 #define _MSC_STATUS_INVADDR_SHIFT 2
167 #define _MSC_STATUS_INVADDR_MASK 0x4UL
168 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
169 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
170 #define MSC_STATUS_WDATAREADY (0x1UL << 3)
171 #define _MSC_STATUS_WDATAREADY_SHIFT 3
172 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL
173 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
174 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
175 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
176 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
177 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
178 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
179 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
180 #define MSC_STATUS_ERASEABORTED (0x1UL << 5)
181 #define _MSC_STATUS_ERASEABORTED_SHIFT 5
182 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
183 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
184 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
186 /* Bit fields for MSC IF */
187 #define _MSC_IF_RESETVALUE 0x00000000UL
188 #define _MSC_IF_MASK 0x00000003UL
189 #define MSC_IF_ERASE (0x1UL << 0)
190 #define _MSC_IF_ERASE_SHIFT 0
191 #define _MSC_IF_ERASE_MASK 0x1UL
192 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL
193 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
194 #define MSC_IF_WRITE (0x1UL << 1)
195 #define _MSC_IF_WRITE_SHIFT 1
196 #define _MSC_IF_WRITE_MASK 0x2UL
197 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL
198 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
200 /* Bit fields for MSC IFS */
201 #define _MSC_IFS_RESETVALUE 0x00000000UL
202 #define _MSC_IFS_MASK 0x00000003UL
203 #define MSC_IFS_ERASE (0x1UL << 0)
204 #define _MSC_IFS_ERASE_SHIFT 0
205 #define _MSC_IFS_ERASE_MASK 0x1UL
206 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
207 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
208 #define MSC_IFS_WRITE (0x1UL << 1)
209 #define _MSC_IFS_WRITE_SHIFT 1
210 #define _MSC_IFS_WRITE_MASK 0x2UL
211 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
212 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
214 /* Bit fields for MSC IFC */
215 #define _MSC_IFC_RESETVALUE 0x00000000UL
216 #define _MSC_IFC_MASK 0x00000003UL
217 #define MSC_IFC_ERASE (0x1UL << 0)
218 #define _MSC_IFC_ERASE_SHIFT 0
219 #define _MSC_IFC_ERASE_MASK 0x1UL
220 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
221 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
222 #define MSC_IFC_WRITE (0x1UL << 1)
223 #define _MSC_IFC_WRITE_SHIFT 1
224 #define _MSC_IFC_WRITE_MASK 0x2UL
225 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
226 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
228 /* Bit fields for MSC IEN */
229 #define _MSC_IEN_RESETVALUE 0x00000000UL
230 #define _MSC_IEN_MASK 0x00000003UL
231 #define MSC_IEN_ERASE (0x1UL << 0)
232 #define _MSC_IEN_ERASE_SHIFT 0
233 #define _MSC_IEN_ERASE_MASK 0x1UL
234 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
235 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
236 #define MSC_IEN_WRITE (0x1UL << 1)
237 #define _MSC_IEN_WRITE_SHIFT 1
238 #define _MSC_IEN_WRITE_MASK 0x2UL
239 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
240 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
242 /* Bit fields for MSC LOCK */
243 #define _MSC_LOCK_RESETVALUE 0x00000000UL
244 #define _MSC_LOCK_MASK 0x0000FFFFUL
245 #define _MSC_LOCK_LOCKKEY_SHIFT 0
246 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
247 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
248 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
249 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
250 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
251 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
252 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
253 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
254 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
255 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
256 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
__IOM uint32_t LOCK
Definition: efm32g_msc.h:56
__IOM uint32_t IEN
Definition: efm32g_msc.h:55
__IM uint32_t STATUS
Definition: efm32g_msc.h:50
__IOM uint32_t WDATA
Definition: efm32g_msc.h:49
__IOM uint32_t READCTRL
Definition: efm32g_msc.h:44
__IOM uint32_t IFC
Definition: efm32g_msc.h:54
__IOM uint32_t ADDRB
Definition: efm32g_msc.h:47
__IOM uint32_t IFS
Definition: efm32g_msc.h:53
__IOM uint32_t WRITECTRL
Definition: efm32g_msc.h:45
__IOM uint32_t CTRL
Definition: efm32g_msc.h:43
__IM uint32_t IF
Definition: efm32g_msc.h:52
__IOM uint32_t WRITECMD
Definition: efm32g_msc.h:46