EFM32 Gecko Software Documentation  efm32g-doc-5.1.2
em_cmu.h
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1 /***************************************************************************/
32 #ifndef EM_CMU_H
33 #define EM_CMU_H
34 
35 #include "em_device.h"
36 #if defined( CMU_PRESENT )
37 
38 #include <stdbool.h>
39 #include "em_assert.h"
40 #include "em_bus.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 /***************************************************************************/
51 /***************************************************************************/
58 /* Select register id's, for internal use. */
59 #define CMU_NOSEL_REG 0
60 #define CMU_HFCLKSEL_REG 1
61 #define CMU_LFACLKSEL_REG 2
62 #define CMU_LFBCLKSEL_REG 3
63 #define CMU_LFCCLKSEL_REG 4
64 #define CMU_LFECLKSEL_REG 5
65 #define CMU_DBGCLKSEL_REG 6
66 #define CMU_USBCCLKSEL_REG 7
67 
68 #define CMU_SEL_REG_POS 0
69 #define CMU_SEL_REG_MASK 0xf
70 
71 /* Divisor/prescaler register id's, for internal use. */
72 #define CMU_NODIV_REG 0
73 #define CMU_NOPRESC_REG 0
74 #define CMU_HFPRESC_REG 1
75 #define CMU_HFCLKDIV_REG 1
76 #define CMU_HFEXPPRESC_REG 2
77 #define CMU_HFCLKLEPRESC_REG 3
78 #define CMU_HFPERPRESC_REG 4
79 #define CMU_HFPERCLKDIV_REG 4
80 #define CMU_HFCOREPRESC_REG 5
81 #define CMU_HFCORECLKDIV_REG 5
82 #define CMU_LFAPRESC0_REG 6
83 #define CMU_LFBPRESC0_REG 7
84 #define CMU_LFEPRESC0_REG 8
85 
86 #define CMU_PRESC_REG_POS 4
87 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
88 #define CMU_PRESC_REG_MASK 0xf
89 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
90 
91 /* Enable register id's, for internal use. */
92 #define CMU_NO_EN_REG 0
93 #define CMU_CTRL_EN_REG 1
94 #define CMU_HFPERCLKDIV_EN_REG 1
95 #define CMU_HFPERCLKEN0_EN_REG 2
96 #define CMU_HFCORECLKEN0_EN_REG 3
97 #define CMU_HFBUSCLKEN0_EN_REG 5
98 #define CMU_LFACLKEN0_EN_REG 6
99 #define CMU_LFBCLKEN0_EN_REG 7
100 #define CMU_LFCCLKEN0_EN_REG 8
101 #define CMU_LFECLKEN0_EN_REG 9
102 #define CMU_PCNT_EN_REG 10
103 
104 #define CMU_EN_REG_POS 8
105 #define CMU_EN_REG_MASK 0xf
106 
107 /* Enable register bit positions, for internal use. */
108 #define CMU_EN_BIT_POS 12
109 #define CMU_EN_BIT_MASK 0x1f
110 
111 /* Clock branch bitfield positions, for internal use. */
112 #define CMU_HF_CLK_BRANCH 0
113 #define CMU_HFCORE_CLK_BRANCH 1
114 #define CMU_HFPER_CLK_BRANCH 2
115 #define CMU_HFBUS_CLK_BRANCH 4
116 #define CMU_HFEXP_CLK_BRANCH 5
117 #define CMU_DBG_CLK_BRANCH 6
118 #define CMU_AUX_CLK_BRANCH 7
119 #define CMU_RTC_CLK_BRANCH 8
120 #define CMU_RTCC_CLK_BRANCH 9
121 #define CMU_LETIMER0_CLK_BRANCH 10
122 #define CMU_LEUART0_CLK_BRANCH 11
123 #define CMU_LEUART1_CLK_BRANCH 12
124 #define CMU_LFA_CLK_BRANCH 13
125 #define CMU_LFB_CLK_BRANCH 14
126 #define CMU_LFC_CLK_BRANCH 15
127 #define CMU_LFE_CLK_BRANCH 16
128 #define CMU_USBC_CLK_BRANCH 17
129 #define CMU_USBLE_CLK_BRANCH 18
130 #define CMU_LCDPRE_CLK_BRANCH 19
131 #define CMU_LCD_CLK_BRANCH 20
132 #define CMU_LESENSE_CLK_BRANCH 21
133 #define CMU_CSEN_LF_CLK_BRANCH 22
134 
135 #define CMU_CLK_BRANCH_POS 17
136 #define CMU_CLK_BRANCH_MASK 0x1f
137 
138 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
139 /* Max clock frequency for VSCALE voltages */
140 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
141 #endif
142 
144 /*******************************************************************************
145  ******************************** ENUMS ************************************
146  ******************************************************************************/
147 
149 #define cmuClkDiv_1 1
150 #define cmuClkDiv_2 2
151 #define cmuClkDiv_4 4
152 #define cmuClkDiv_8 8
153 #define cmuClkDiv_16 16
154 #define cmuClkDiv_32 32
155 #define cmuClkDiv_64 64
156 #define cmuClkDiv_128 128
157 #define cmuClkDiv_256 256
158 #define cmuClkDiv_512 512
159 #define cmuClkDiv_1024 1024
160 #define cmuClkDiv_2048 2048
161 #define cmuClkDiv_4096 4096
162 #define cmuClkDiv_8192 8192
163 #define cmuClkDiv_16384 16384
164 #define cmuClkDiv_32768 32768
167 typedef uint32_t CMU_ClkDiv_TypeDef;
168 
169 #if defined( _SILICON_LABS_32B_SERIES_1 )
170 
171 typedef uint32_t CMU_ClkPresc_TypeDef;
172 #endif
173 
174 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
175 
176 typedef enum
177 {
178  cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,
179  cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,
180  cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
181  cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
182  cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
183 #if defined( CMU_HFRCOCTRL_BAND_28MHZ )
184  cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ,
185 #endif
186 } CMU_HFRCOBand_TypeDef;
187 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
188 
189 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
190 
191 typedef enum
192 {
193  cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ,
194  cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ,
195  cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,
196  cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,
197  cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,
198 #if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
199  cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ,
200 #endif
201 } CMU_AUXHFRCOBand_TypeDef;
202 #endif
203 
204 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
205 
206 typedef enum
207 {
209  cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
211  cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
212 } CMU_USHFRCOBand_TypeDef;
213 #endif
214 
215 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
216 
217 typedef enum
218 {
219  cmuHFRCOFreq_1M0Hz = 1000000U,
220  cmuHFRCOFreq_2M0Hz = 2000000U,
221  cmuHFRCOFreq_4M0Hz = 4000000U,
222  cmuHFRCOFreq_7M0Hz = 7000000U,
223  cmuHFRCOFreq_13M0Hz = 13000000U,
224  cmuHFRCOFreq_16M0Hz = 16000000U,
225  cmuHFRCOFreq_19M0Hz = 19000000U,
226  cmuHFRCOFreq_26M0Hz = 26000000U,
227  cmuHFRCOFreq_32M0Hz = 32000000U,
228  cmuHFRCOFreq_38M0Hz = 38000000U,
229  cmuHFRCOFreq_UserDefined = 0,
230 } CMU_HFRCOFreq_TypeDef;
231 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
232 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
233 #endif
234 
235 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
236 
237 typedef enum
238 {
239  cmuAUXHFRCOFreq_1M0Hz = 1000000U,
240  cmuAUXHFRCOFreq_2M0Hz = 2000000U,
241  cmuAUXHFRCOFreq_4M0Hz = 4000000U,
242  cmuAUXHFRCOFreq_7M0Hz = 7000000U,
243  cmuAUXHFRCOFreq_13M0Hz = 13000000U,
244  cmuAUXHFRCOFreq_16M0Hz = 16000000U,
245  cmuAUXHFRCOFreq_19M0Hz = 19000000U,
246  cmuAUXHFRCOFreq_26M0Hz = 26000000U,
247  cmuAUXHFRCOFreq_32M0Hz = 32000000U,
248  cmuAUXHFRCOFreq_38M0Hz = 38000000U,
249  cmuAUXHFRCOFreq_UserDefined = 0,
250 } CMU_AUXHFRCOFreq_TypeDef;
251 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
252 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
253 #endif
254 
255 
257 typedef enum
258 {
259  /*******************/
260  /* HF clock branch */
261  /*******************/
262 
264 #if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
265  || defined( _CMU_HFPRESC_MASK )
266  cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
267  | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
268  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
269  | (0 << CMU_EN_BIT_POS)
270  | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
271 #else
272  cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
273  | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
274  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
275  | (0 << CMU_EN_BIT_POS)
276  | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
277 #endif
278 
280  cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
281  | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
282  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
283  | (0 << CMU_EN_BIT_POS)
284  | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
285 
287  cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
288  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
289  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
290  | (0 << CMU_EN_BIT_POS)
291  | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
292 
293 #if defined( _CMU_HFEXPPRESC_MASK )
294  /**********************/
295  /* HF export sub-branch */
296  /**********************/
297 
299  cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
300  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
301  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
302  | (0 << CMU_EN_BIT_POS)
303  | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
304 #endif
305 
306 #if defined( _CMU_HFBUSCLKEN0_MASK )
307 /**********************************/
308  /* HF bus clock sub-branch */
309  /**********************************/
310 
312  cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
313  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
314  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
315  | (0 << CMU_EN_BIT_POS)
316  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
317 
318 #if defined( CMU_HFBUSCLKEN0_CRYPTO )
320  cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
321  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
322  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
323  | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
324  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
325 #endif
326 
327 #if defined( CMU_HFBUSCLKEN0_CRYPTO0 )
329  cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
330  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
331  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
332  | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS)
333  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
334 #endif
335 
336 #if defined( CMU_HFBUSCLKEN0_CRYPTO1 )
338  cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
339  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
340  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
341  | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS)
342  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
343 #endif
344 
345 #if defined( CMU_HFBUSCLKEN0_LDMA )
347  cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
348  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
349  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
350  | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
351  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
352 #endif
353 
354 #if defined( CMU_HFBUSCLKEN0_GPCRC )
356  cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
357  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
358  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
359  | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
360  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
361 #endif
362 
363 #if defined( CMU_HFBUSCLKEN0_GPIO )
365  cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
366  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
367  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
368  | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
369  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
370 #endif
371 
373  cmuClock_HFLE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
374  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
375  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
376  | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
377  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
378 
379 #if defined( CMU_HFBUSCLKEN0_PRS )
380 
381  cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
382  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
383  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
384  | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
385  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
386 #endif
387 #endif
388 
389  /**********************************/
390  /* HF peripheral clock sub-branch */
391  /**********************************/
392 
394 #if defined( _CMU_HFPRESC_MASK )
395  cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
396  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
397  | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
398  | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
399  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
400 #else
401  cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
402  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
403  | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
404  | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
405  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
406 #endif
407 
408 #if defined( CMU_HFPERCLKEN0_USART0 )
409 
410  cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
411  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
412  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
413  | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
414  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
415 #endif
416 
417 #if defined( CMU_HFPERCLKEN0_USARTRF0 )
419  cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
420  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
421  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
422  | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
423  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
424 #endif
425 
426 #if defined( CMU_HFPERCLKEN0_USARTRF1 )
428  cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
429  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
430  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
431  | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
432  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
433 #endif
434 
435 #if defined( CMU_HFPERCLKEN0_USART1 )
437  cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
438  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
439  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
440  | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
441  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
442 #endif
443 
444 #if defined( CMU_HFPERCLKEN0_USART2 )
446  cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
447  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
448  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
449  | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
450  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
451 #endif
452 
453 #if defined( CMU_HFPERCLKEN0_USART3 )
455  cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
456  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
457  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
458  | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
459  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
460 #endif
461 
462 #if defined( CMU_HFPERCLKEN0_USART4 )
464  cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
465  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
466  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
467  | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
468  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
469 #endif
470 
471 #if defined( CMU_HFPERCLKEN0_USART5 )
473  cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
474  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
475  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
476  | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
477  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
478 #endif
479 
480 
481 #if defined( CMU_HFPERCLKEN0_UART0 )
483  cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
484  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
485  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
486  | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
487  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
488 #endif
489 
490 #if defined( CMU_HFPERCLKEN0_UART1 )
492  cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
493  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
494  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
495  | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
496  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
497 #endif
498 
499 #if defined( CMU_HFPERCLKEN0_TIMER0 )
501  cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
502  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
503  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
504  | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
505  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
506 #endif
507 
508 #if defined( CMU_HFPERCLKEN0_TIMER1 )
510  cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
511  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
512  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
513  | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
514  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
515 #endif
516 
517 #if defined( CMU_HFPERCLKEN0_TIMER2 )
519  cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
520  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
521  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
522  | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
523  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
524 #endif
525 
526 #if defined( CMU_HFPERCLKEN0_TIMER3 )
528  cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
529  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
530  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
531  | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
532  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
533 #endif
534 
535 #if defined( CMU_HFPERCLKEN0_WTIMER0 )
537  cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
538  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
539  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
540  | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
541  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
542 #endif
543 
544 #if defined( CMU_HFPERCLKEN0_WTIMER1 )
546  cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
547  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
548  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
549  | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
550  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
551 #endif
552 
553 #if defined( CMU_HFPERCLKEN0_CRYOTIMER )
555  cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
556  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
557  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
558  | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
559  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
560 #endif
561 
562 #if defined( CMU_HFPERCLKEN0_ACMP0 )
564  cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
565  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
566  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
567  | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
568  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
569 #endif
570 
571 #if defined( CMU_HFPERCLKEN0_ACMP1 )
573  cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
574  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
575  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
576  | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
577  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
578 #endif
579 
580 #if defined( CMU_HFPERCLKEN0_PRS )
582  cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
583  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
584  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
585  | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
586  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
587 #endif
588 
589 #if defined( CMU_HFPERCLKEN0_DAC0 )
591  cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
592  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
593  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
594  | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
595  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
596 #endif
597 
598 #if defined( CMU_HFPERCLKEN0_VDAC0 )
600  cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
601  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
602  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
603  | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
604  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
605 #endif
606 
607 #if defined( CMU_HFPERCLKEN0_IDAC0 )
609  cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
610  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
611  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
612  | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
613  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
614 #endif
615 
616 #if defined( CMU_HFPERCLKEN0_GPIO )
618  cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
619  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
620  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
621  | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
622  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
623 #endif
624 
625 #if defined( CMU_HFPERCLKEN0_VCMP )
627  cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
628  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
629  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
630  | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
631  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
632 #endif
633 
634 #if defined( CMU_HFPERCLKEN0_ADC0 )
636  cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
637  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
638  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
639  | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
640  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
641 #endif
642 
643 #if defined( CMU_HFPERCLKEN0_I2C0 )
645  cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
646  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
647  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
648  | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
649  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
650 #endif
651 
652 #if defined( CMU_HFPERCLKEN0_I2C1 )
654  cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
655  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
656  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
657  | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
658  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
659 #endif
660 
661 #if defined( CMU_HFPERCLKEN0_I2C2 )
663  cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
664  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
665  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
666  | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
667  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
668 #endif
669 
670 #if defined( CMU_HFPERCLKEN0_CSEN )
672  cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
673  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
674  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
675  | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
676  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
677 #endif
678 
679 #if defined( CMU_HFPERCLKEN0_TRNG0 )
681  cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
682  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
683  | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
684  | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
685  | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
686 #endif
687 
688  /**********************/
689  /* HF core sub-branch */
690  /**********************/
691 
693  cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
694  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
695  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
696  | (0 << CMU_EN_BIT_POS)
697  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
698 
699 #if defined( CMU_HFCORECLKEN0_AES )
700 
701  cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
702  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
703  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
704  | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
705  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
706 #endif
707 
708 #if defined( CMU_HFCORECLKEN0_DMA )
710  cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
711  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
712  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
713  | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
714  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
715 #endif
716 
717 #if defined( CMU_HFCORECLKEN0_LE )
719  cmuClock_HFLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
720  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
721  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
722  | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
723  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
724 #endif
725 
726 #if defined( CMU_HFCORECLKEN0_EBI )
728  cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
729  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
730  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
731  | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
732  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
733 #endif
734 
735 #if defined( CMU_HFCORECLKEN0_USBC )
737  cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
738  | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
739  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
740  | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
741  | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
742 
743 #endif
744 
745 #if defined( CMU_HFCORECLKEN0_USB )
747  cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
748  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
749  | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
750  | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
751  | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
752 #endif
753 
754  /***************/
755  /* LF A branch */
756  /***************/
757 
759  cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
760  | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
761  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
762  | (0 << CMU_EN_BIT_POS)
763  | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
764 
765 #if defined( CMU_LFACLKEN0_RTC )
766 
767  cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
768  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
769  | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
770  | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
771  | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
772 #endif
773 
774 #if defined( CMU_LFACLKEN0_LETIMER0 )
776  cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
777  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
778  | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
779  | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
780  | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
781 #endif
782 
783 #if defined( CMU_LFACLKEN0_LCD )
785  cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
786  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
787  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
788  | (0 << CMU_EN_BIT_POS)
789  | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
790 
793  cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
794  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
795  | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
796  | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
797  | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
798 #endif
799 
800 #if defined( CMU_PCNTCTRL_PCNT0CLKEN )
801 
802  cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
803  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
804  | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
805  | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
806  | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
807 #endif
808 
809 #if defined( CMU_PCNTCTRL_PCNT1CLKEN )
811  cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
812  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
813  | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
814  | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
815  | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
816 #endif
817 
818 #if defined( CMU_PCNTCTRL_PCNT2CLKEN )
820  cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
821  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
822  | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
823  | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
824  | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
825 #endif
826 #if defined( CMU_LFACLKEN0_LESENSE )
828  cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
829  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
830  | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
831  | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
832  | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
833 #endif
834 
835  /***************/
836  /* LF B branch */
837  /***************/
838 
840  cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
841  | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
842  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
843  | (0 << CMU_EN_BIT_POS)
844  | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
845 
846 #if defined( CMU_LFBCLKEN0_LEUART0 )
847 
848  cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
849  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
850  | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
851  | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
852  | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
853 #endif
854 
855 #if defined( CMU_LFBCLKEN0_CSEN )
857  cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
858  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
859  | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
860  | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
861  | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
862 #endif
863 
864 #if defined( CMU_LFBCLKEN0_LEUART1 )
866  cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
867  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
868  | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
869  | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
870  | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
871 #endif
872 
873 #if defined( CMU_LFBCLKEN0_SYSTICK )
875  cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
876  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
877  | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
878  | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS)
879  | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
880 #endif
881 
882 #if defined( _CMU_LFCCLKEN0_MASK )
883  /***************/
884  /* LF C branch */
885  /***************/
886 
888  cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
889  | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
890  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
891  | (0 << CMU_EN_BIT_POS)
892  | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
893 
894 #if defined( CMU_LFCCLKEN0_USBLE )
896  cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
897  | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
898  | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
899  | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
900  | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
901 #endif
902 #endif
903 
904 #if defined( _CMU_LFECLKEN0_MASK )
905  /***************/
906  /* LF E branch */
907  /***************/
908 
910  cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
911  | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
912  | (CMU_NO_EN_REG << CMU_EN_REG_POS)
913  | (0 << CMU_EN_BIT_POS)
914  | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
915 
917 #if defined ( CMU_LFECLKEN0_RTCC )
918  cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
919  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
920  | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
921  | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
922  | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
923 #endif
924 #endif
925 
926 } CMU_Clock_TypeDef;
927 
929 /* Deprecated CMU_Clock_TypeDef member */
930 #define cmuClock_CORELE cmuClock_HFLE
931 
935 typedef enum
936 {
937  cmuOsc_LFXO,
938  cmuOsc_LFRCO,
939  cmuOsc_HFXO,
940  cmuOsc_HFRCO,
941  cmuOsc_AUXHFRCO,
942 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
943  cmuOsc_USHFRCO,
944 #endif
945 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
946  cmuOsc_ULFRCO,
947 #endif
948 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
949  cmuOsc_PLFRCO,
950 #endif
951 } CMU_Osc_TypeDef;
952 
954 typedef enum
955 {
956  cmuOscMode_Crystal,
957  cmuOscMode_AcCoupled,
958  cmuOscMode_External,
959 } CMU_OscMode_TypeDef;
960 
962 typedef enum
963 {
964  cmuSelect_Error,
965  cmuSelect_Disabled,
966  cmuSelect_LFXO,
967  cmuSelect_LFRCO,
968  cmuSelect_HFXO,
969  cmuSelect_HFRCO,
970  cmuSelect_HFCLKLE,
971  cmuSelect_AUXHFRCO,
972  cmuSelect_HFCLK,
974 #if defined( CMU_STATUS_USHFRCOENS )
975  cmuSelect_USHFRCO,
976 #endif
977 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
978  cmuSelect_USHFRCODIV2,
979 #endif
980 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
981  cmuSelect_ULFRCO,
982 #endif
983 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
984  cmuSelect_PLFRCO,
985 #endif
986 } CMU_Select_TypeDef;
987 
988 #if defined( CMU_HFCORECLKEN0_LE )
989 
990 /* Deprecated CMU_Select_TypeDef member */
991 #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
992 
993 #endif
994 
995 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
996 
997 typedef enum
998 {
999  cmuHFXOTuningMode_Auto = 0,
1000  cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART,
1001  cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART
1002  | CMU_CMD_HFXOSHUNTOPTSTART,
1003 } CMU_HFXOTuningMode_TypeDef;
1004 #endif
1005 
1006 #if defined( _CMU_CTRL_LFXOBOOST_MASK )
1007 
1008 typedef enum
1009 {
1010  cmuLfxoBoost70 = 0x0,
1011  cmuLfxoBoost100 = 0x2,
1012 #if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
1013  cmuLfxoBoost70Reduced = 0x1,
1014  cmuLfxoBoost100Reduced = 0x3,
1015 #endif
1016 } CMU_LFXOBoost_TypeDef;
1017 #endif
1018 
1019 /*******************************************************************************
1020  ******************************* STRUCTS ***********************************
1021  ******************************************************************************/
1022 
1025 typedef struct
1026 {
1027 #if defined( _CMU_LFXOCTRL_MASK )
1028  uint8_t ctune;
1029  uint8_t gain;
1030 #else
1031  CMU_LFXOBoost_TypeDef boost;
1032 #endif
1033  uint8_t timeout;
1034  CMU_OscMode_TypeDef mode;
1035 } CMU_LFXOInit_TypeDef;
1036 
1037 #if defined( _CMU_LFXOCTRL_MASK )
1038 
1040 #define CMU_LFXOINIT_DEFAULT \
1041  { \
1042  _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
1043  _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
1044  _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \
1045  cmuOscMode_Crystal, /* Crystal oscillator */ \
1046  }
1047 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
1048  { \
1049  0, /* No CTUNE value needed */ \
1050  0, /* No LFXO startup gain */ \
1051  _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
1052  cmuOscMode_External, /* External digital clock */ \
1053  }
1054 #else
1055 
1056 #define CMU_LFXOINIT_DEFAULT \
1057  { \
1058  cmuLfxoBoost70, \
1059  _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
1060  cmuOscMode_Crystal, \
1061  }
1062 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
1063  { \
1064  cmuLfxoBoost70, \
1065  _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
1066  cmuOscMode_External, \
1067  }
1068 #endif
1069 
1072 typedef struct
1073 {
1074 #if defined( _CMU_HFXOCTRL_MASK )
1075  bool lowPowerMode;
1076  bool autoStartEm01;
1077  bool autoSelEm01;
1078  bool autoStartSelOnRacWakeup;
1079  uint16_t ctuneStartup;
1080  uint16_t ctuneSteadyState;
1081  uint8_t regIshSteadyState;
1082  uint8_t xoCoreBiasTrimStartup;
1083  uint8_t xoCoreBiasTrimSteadyState;
1084  uint8_t thresholdPeakDetect;
1085  uint8_t timeoutShuntOptimization;
1086  uint8_t timeoutPeakDetect;
1087  uint8_t timeoutSteady;
1088  uint8_t timeoutStartup;
1089 #else
1090  uint8_t boost;
1091  uint8_t timeout;
1092  bool glitchDetector;
1093 #endif
1094  CMU_OscMode_TypeDef mode;
1095 } CMU_HFXOInit_TypeDef;
1096 
1097 #if defined( _CMU_HFXOCTRL_MASK )
1098 
1102 #if defined( _EFR_DEVICE )
1103 #define CMU_HFXOINIT_DEFAULT \
1104 { \
1105  false, /* Low-noise mode for EFR32 */ \
1106  false, /* @deprecated no longer in use */ \
1107  false, /* @deprecated no longer in use */ \
1108  false, /* @deprecated no longer in use */ \
1109  _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
1110  _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
1111  _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1112  0x20, /* Matching errata fix in CHIP_Init() */ \
1113  0x7, /* Recommended steady-state XO core bias current */ \
1114  0x6, /* Recommended peak detection threshold */ \
1115  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1116  0xA, /* Recommended peak detection timeout */ \
1117  0x4, /* Recommended steady timeout */ \
1118  _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
1119  cmuOscMode_Crystal, \
1120 }
1121 #else /* EFM32 device */
1122 #define CMU_HFXOINIT_DEFAULT \
1123 { \
1124  true, /* Low-power mode for EFM32 */ \
1125  false, /* @deprecated no longer in use */ \
1126  false, /* @deprecated no longer in use */ \
1127  false, /* @deprecated no longer in use */ \
1128  _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
1129  _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
1130  _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1131  0x20, /* Matching errata fix in CHIP_Init() */ \
1132  0x7, /* Recommended steady-state osc core bias current */ \
1133  0x6, /* Recommended peak detection threshold */ \
1134  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1135  0xA, /* Recommended peak detection timeout */ \
1136  0x4, /* Recommended steady timeout */ \
1137  _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
1138  cmuOscMode_Crystal, \
1139 }
1140 #endif /* _EFR_DEVICE */
1141 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
1142 { \
1143  true, /* Low-power mode */ \
1144  false, /* @deprecated no longer in use */ \
1145  false, /* @deprecated no longer in use */ \
1146  false, /* @deprecated no longer in use */ \
1147  0, /* Startup CTUNE=0 recommended for external clock */ \
1148  0, /* Steady CTUNE=0 recommended for external clock */ \
1149  _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1150  0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
1151  0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
1152  0x6, /* Recommended peak detection threshold */ \
1153  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1154  0x0, /* Peak-detect not recommended for external clock usage */ \
1155  _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
1156  _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
1157  cmuOscMode_External, \
1158 }
1159 #else /* _CMU_HFXOCTRL_MASK */
1160 
1163 #define CMU_HFXOINIT_DEFAULT \
1164 { \
1165  _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
1166  _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16k startup delay */ \
1167  false, /* Disable glitch detector */ \
1168  cmuOscMode_Crystal, /* Crystal oscillator */ \
1169 }
1170 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
1171 { \
1172  0, /* Minimal HFXO boost, 50% */ \
1173  _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
1174  false, /* Disable glitch detector */ \
1175  cmuOscMode_External, /* External digital clock */ \
1176 }
1177 #endif /* _CMU_HFXOCTRL_MASK */
1178 
1179 
1180 /*******************************************************************************
1181  ***************************** PROTOTYPES **********************************
1182  ******************************************************************************/
1183 
1184 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
1185 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
1186 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
1187 
1188 #elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
1189 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
1190 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
1191 #endif
1192 
1193 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
1194 
1195 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
1196 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
1197  CMU_Osc_TypeDef upSel);
1198 #endif
1199 
1200 uint32_t CMU_CalibrateCountGet(void);
1201 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
1202 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
1203 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
1204 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
1205 
1206 #if defined( _SILICON_LABS_32B_SERIES_1 )
1207 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);
1208 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
1209 #endif
1210 
1211 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
1212 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
1213 void CMU_FreezeEnable(bool enable);
1214 
1215 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
1216 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
1217 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
1218 
1219 #elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
1220 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
1221 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
1222 #endif
1223 
1224 uint32_t CMU_HFRCOStartupDelayGet(void);
1225 void CMU_HFRCOStartupDelaySet(uint32_t delay);
1226 
1227 #if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
1228 void CMU_HFXOAutostartEnable(uint32_t userSel,
1229  bool enEM0EM1Start,
1230  bool enEM0EM1StartSel);
1231 #endif
1232 
1233 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
1234 
1235 
1236 uint32_t CMU_LCDClkFDIVGet(void);
1237 void CMU_LCDClkFDIVSet(uint32_t div);
1238 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
1239 
1240 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
1241 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
1242 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
1243 
1244 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
1245 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
1246 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
1247  CMU_HFXOTuningMode_TypeDef mode,
1248  bool wait);
1249 #endif
1250 
1251 bool CMU_PCNTClockExternalGet(unsigned int instance);
1252 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
1253 
1254 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
1255 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
1256 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
1257 #endif
1258 
1259 
1260 #if defined( CMU_CALCTRL_CONT )
1261 /***************************************************************************/
1268 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
1269 {
1270  BUS_RegBitWrite(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
1271 }
1272 #endif
1273 
1274 
1275 /***************************************************************************/
1282 __STATIC_INLINE void CMU_CalibrateStart(void)
1283 {
1284  CMU->CMD = CMU_CMD_CALSTART;
1285 }
1286 
1287 
1288 #if defined( CMU_CMD_CALSTOP )
1289 /***************************************************************************/
1293 __STATIC_INLINE void CMU_CalibrateStop(void)
1294 {
1295  CMU->CMD = CMU_CMD_CALSTOP;
1296 }
1297 #endif
1298 
1299 
1300 /***************************************************************************/
1311 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
1312 {
1313  uint32_t log2;
1314 
1315  /* Fixed 2^n prescalers take argument of 32768 or less. */
1316  EFM_ASSERT((div > 0U) && (div <= 32768U));
1317 
1318  /* Count leading zeroes and "reverse" result */
1319  log2 = (31U - __CLZ(div));
1320 
1321  return log2;
1322 }
1323 
1324 
1325 /***************************************************************************/
1332 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
1333 {
1334  CMU->IFC = flags;
1335 }
1336 
1337 
1338 /***************************************************************************/
1345 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
1346 {
1347  CMU->IEN &= ~flags;
1348 }
1349 
1350 
1351 /***************************************************************************/
1363 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
1364 {
1365  CMU->IEN |= flags;
1366 }
1367 
1368 
1369 /***************************************************************************/
1376 __STATIC_INLINE uint32_t CMU_IntGet(void)
1377 {
1378  return CMU->IF;
1379 }
1380 
1381 
1382 /***************************************************************************/
1398 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
1399 {
1400  uint32_t ien;
1401 
1402  ien = CMU->IEN;
1403  return CMU->IF & ien;
1404 }
1405 
1406 
1407 /**************************************************************************/
1414 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
1415 {
1416  CMU->IFS = flags;
1417 }
1418 
1419 
1420 /***************************************************************************/
1433 __STATIC_INLINE void CMU_Lock(void)
1434 {
1435  CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
1436 }
1437 
1438 
1439 /***************************************************************************/
1449 __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
1450 {
1451  return 1 << log2;
1452 }
1453 
1454 
1455 #if defined( _SILICON_LABS_32B_SERIES_1 )
1456 /***************************************************************************/
1467 __STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
1468 {
1469  uint32_t log2;
1470 
1471  /* Integer prescalers take argument less than 32768. */
1472  EFM_ASSERT(presc < 32768U);
1473 
1474  /* Count leading zeroes and "reverse" result */
1475  log2 = (31U - __CLZ(presc + 1));
1476 
1477  /* Check that presc is a 2^n number */
1478  EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1));
1479 
1480  return log2;
1481 }
1482 #endif
1483 
1484 
1485 /***************************************************************************/
1489 __STATIC_INLINE void CMU_Unlock(void)
1490 {
1491  CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
1492 }
1493 
1494 
1495 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
1496 /***************************************************************************/
1506 __STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
1507 {
1508  return CMU_HFRCOBandGet();
1509 }
1510 
1511 
1512 /***************************************************************************/
1522 __STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
1523 {
1524  CMU_HFRCOBandSet(setFreq);
1525 }
1526 #endif
1527 
1528 
1529 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
1530 /***************************************************************************/
1540 __STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
1541 {
1542  return CMU_AUXHFRCOBandGet();
1543 }
1544 
1545 
1546 /***************************************************************************/
1556 __STATIC_INLINE void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
1557 {
1558  CMU_AUXHFRCOBandSet(setFreq);
1559 }
1560 #endif
1561 
1565 #ifdef __cplusplus
1566 }
1567 #endif
1568 
1569 #endif /* defined( CMU_PRESENT ) */
1570 #endif /* EM_CMU_H */
CMU_LFXOInit_TypeDef
Definition: em_cmu.h:1025
CMU_ClockSelectSet
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
Definition: em_cmu.c:2521
cmuSelect_HFCLK
Definition: em_cmu.h:972
_CMU_LFACLKEN0_RTC_SHIFT
#define _CMU_LFACLKEN0_RTC_SHIFT
Definition: efm32g_cmu.h:786
cmuSelect_AUXHFRCO
Definition: em_cmu.h:971
cmuClock_I2C0
Definition: em_cmu.h:645
cmuSelect_HFXO
Definition: em_cmu.h:968
CMU_PCNTClockExternalSet
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
Definition: em_cmu.c:4061
CMU_Lock
__STATIC_INLINE void CMU_Lock(void)
Lock the CMU in order to protect some of its registers against unintended modification.
Definition: em_cmu.h:1433
cmuOscMode_External
Definition: em_cmu.h:958
_CMU_HFRCOCTRL_BAND_1MHZ
#define _CMU_HFRCOCTRL_BAND_1MHZ
Definition: efm32g_cmu.h:263
_CMU_HFPERCLKEN0_ACMP0_SHIFT
#define _CMU_HFPERCLKEN0_ACMP0_SHIFT
Definition: efm32g_cmu.h:705
em_assert.h
Emlib peripheral API "assert" implementation.
CMU_HFPERCLKEN0_ACMP0
#define CMU_HFPERCLKEN0_ACMP0
Definition: efm32g_cmu.h:704
_CMU_HFPERCLKEN0_VCMP_SHIFT
#define _CMU_HFPERCLKEN0_VCMP_SHIFT
Definition: efm32g_cmu.h:730
CMU_HFPERCLKEN0_UART0
#define CMU_HFPERCLKEN0_UART0
Definition: efm32g_cmu.h:684
cmuClock_DMA
Definition: em_cmu.h:710
CMU_Calibrate
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
Definition: em_cmu.c:904
_CMU_LFBCLKEN0_LEUART0_SHIFT
#define _CMU_LFBCLKEN0_LEUART0_SHIFT
Definition: efm32g_cmu.h:805
em_bus.h
RAM and peripheral bit-field set and clear API.
CMU_LFXOInit_TypeDef::boost
CMU_LFXOBoost_TypeDef boost
Definition: em_cmu.h:1031
CMU_IntGet
__STATIC_INLINE uint32_t CMU_IntGet(void)
Get pending CMU interrupts.
Definition: em_cmu.h:1376
cmuClock_LEUART0
Definition: em_cmu.h:848
cmuClock_PRS
Definition: em_cmu.h:582
cmuSelect_HFCLKLE
Definition: em_cmu.h:970
_CMU_HFPERCLKEN0_PRS_SHIFT
#define _CMU_HFPERCLKEN0_PRS_SHIFT
Definition: efm32g_cmu.h:715
CMU_HFPERCLKEN0_VCMP
#define CMU_HFPERCLKEN0_VCMP
Definition: efm32g_cmu.h:729
CMU_Select_TypeDef
CMU_Select_TypeDef
Definition: em_cmu.h:962
CMU_LFXOInit_TypeDef::timeout
uint8_t timeout
Definition: em_cmu.h:1033
cmuClock_VCMP
Definition: em_cmu.h:627
cmuClock_TIMER0
Definition: em_cmu.h:501
_CMU_HFPERCLKEN0_TIMER1_SHIFT
#define _CMU_HFPERCLKEN0_TIMER1_SHIFT
Definition: efm32g_cmu.h:695
CMU_HFPERCLKEN0_USART2
#define CMU_HFPERCLKEN0_USART2
Definition: efm32g_cmu.h:679
cmuClock_USART2
Definition: em_cmu.h:446
CMU_HFXOInit_TypeDef
Definition: em_cmu.h:1072
CMU_LOCK_LOCKKEY_UNLOCK
#define CMU_LOCK_LOCKKEY_UNLOCK
Definition: efm32g_cmu.h:1037
CMU_IntSet
__STATIC_INLINE void CMU_IntSet(uint32_t flags)
Set one or more pending CMU interrupts.
Definition: em_cmu.h:1414
cmuSelect_LFRCO
Definition: em_cmu.h:967
cmuOscMode_AcCoupled
Definition: em_cmu.h:957
CMU_HFPERCLKEN0_DAC0
#define CMU_HFPERCLKEN0_DAC0
Definition: efm32g_cmu.h:719
_CMU_HFPERCLKEN0_USART1_SHIFT
#define _CMU_HFPERCLKEN0_USART1_SHIFT
Definition: efm32g_cmu.h:675
cmuClock_PCNT1
Definition: em_cmu.h:811
em_device.h
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
cmuClock_EBI
Definition: em_cmu.h:728
cmuClock_TIMER2
Definition: em_cmu.h:519
cmuClock_GPIO
Definition: em_cmu.h:618
CMU_IntGetEnabled
__STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
Get enabled and pending CMU interrupt flags.
Definition: em_cmu.h:1398
CMU_FreezeEnable
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
Definition: em_cmu.c:3000
CMU_HFPERCLKEN0_TIMER2
#define CMU_HFPERCLKEN0_TIMER2
Definition: efm32g_cmu.h:699
CMU_HFXOInit
void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
Set HFXO control registers.
Definition: em_cmu.c:3379
_CMU_HFRCOCTRL_BAND_7MHZ
#define _CMU_HFRCOCTRL_BAND_7MHZ
Definition: efm32g_cmu.h:264
CMU_ClkDiv_TypeDef
uint32_t CMU_ClkDiv_TypeDef
Definition: em_cmu.h:167
cmuClock_ACMP1
Definition: em_cmu.h:573
_CMU_HFPERCLKEN0_ADC0_SHIFT
#define _CMU_HFPERCLKEN0_ADC0_SHIFT
Definition: efm32g_cmu.h:735
CMU_HFCORECLKEN0_EBI
#define CMU_HFCORECLKEN0_EBI
Definition: efm32g_cmu.h:660
CMU_HFRCOStartupDelayGet
uint32_t CMU_HFRCOStartupDelayGet(void)
Get the HFRCO startup delay.
Definition: em_cmu.c:3282
CMU_PCNTCTRL_PCNT2CLKEN
#define CMU_PCNTCTRL_PCNT2CLKEN
Definition: efm32g_cmu.h:952
CMU_LFXOBoost_TypeDef
CMU_LFXOBoost_TypeDef
Definition: em_cmu.h:1008
cmuClock_LETIMER0
Definition: em_cmu.h:776
_CMU_HFRCOCTRL_BAND_28MHZ
#define _CMU_HFRCOCTRL_BAND_28MHZ
Definition: efm32g_cmu.h:269
cmuClock_LFA
Definition: em_cmu.h:759
_CMU_HFRCOCTRL_BAND_14MHZ
#define _CMU_HFRCOCTRL_BAND_14MHZ
Definition: efm32g_cmu.h:267
CMU_Log2ToDiv
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
Definition: em_cmu.h:1449
_CMU_LFBCLKEN0_LEUART1_SHIFT
#define _CMU_LFBCLKEN0_LEUART1_SHIFT
Definition: efm32g_cmu.h:810
cmuSelect_LFXO
Definition: em_cmu.h:966
_CMU_HFCORECLKEN0_AES_SHIFT
#define _CMU_HFCORECLKEN0_AES_SHIFT
Definition: efm32g_cmu.h:646
CMU_CalibrateStart
__STATIC_INLINE void CMU_CalibrateStart(void)
Starts calibration.
Definition: em_cmu.h:1282
CMU_HFPERCLKEN0_ADC0
#define CMU_HFPERCLKEN0_ADC0
Definition: efm32g_cmu.h:734
cmuHFRCOBand_7MHz
Definition: em_cmu.h:179
CMU_OscillatorTuningSet
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
Definition: em_cmu.c:3830
CMU_LFACLKEN0_LCD
#define CMU_LFACLKEN0_LCD
Definition: efm32g_cmu.h:795
cmuHFRCOBand_21MHz
Definition: em_cmu.h:182
CMU_IntDisable
__STATIC_INLINE void CMU_IntDisable(uint32_t flags)
Disable one or more CMU interrupts.
Definition: em_cmu.h:1345
cmuClock_UART0
Definition: em_cmu.h:483
_CMU_LFACLKEN0_LETIMER0_SHIFT
#define _CMU_LFACLKEN0_LETIMER0_SHIFT
Definition: efm32g_cmu.h:791
cmuClock_USART0
Definition: em_cmu.h:410
CMU_HFCORECLKEN0_LE
#define CMU_HFCORECLKEN0_LE
Definition: efm32g_cmu.h:655
cmuHFRCOBand_11MHz
Definition: em_cmu.h:180
cmuOscMode_Crystal
Definition: em_cmu.h:956
_CMU_HFPERCLKEN0_USART0_SHIFT
#define _CMU_HFPERCLKEN0_USART0_SHIFT
Definition: efm32g_cmu.h:670
cmuSelect_HFRCO
Definition: em_cmu.h:969
cmuClock_ACMP0
Definition: em_cmu.h:564
CMU_HFRCOBandGet
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
Get HFRCO band in use.
Definition: em_cmu.c:3032
cmuHFRCOBand_28MHz
Definition: em_cmu.h:184
_CMU_HFCORECLKEN0_LE_SHIFT
#define _CMU_HFCORECLKEN0_LE_SHIFT
Definition: efm32g_cmu.h:656
CMU_HFPERCLKEN0_GPIO
#define CMU_HFPERCLKEN0_GPIO
Definition: efm32g_cmu.h:724
_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT
#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT
Definition: efm32g_cmu.h:953
CMU_HFPERCLKEN0_ACMP1
#define CMU_HFPERCLKEN0_ACMP1
Definition: efm32g_cmu.h:709
cmuClock_TIMER1
Definition: em_cmu.h:510
_CMU_HFPERCLKEN0_DAC0_SHIFT
#define _CMU_HFPERCLKEN0_DAC0_SHIFT
Definition: efm32g_cmu.h:720
CMU_LCDClkFDIVGet
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
Definition: em_cmu.c:3479
CMU_DivToLog2
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
Definition: em_cmu.h:1311
CMU_Clock_TypeDef
CMU_Clock_TypeDef
Definition: em_cmu.h:257
_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT
#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT
Definition: efm32g_cmu.h:939
_CMU_HFPERCLKEN0_TIMER0_SHIFT
#define _CMU_HFPERCLKEN0_TIMER0_SHIFT
Definition: efm32g_cmu.h:690
CMU_CalibrateCountGet
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
Definition: em_cmu.c:1072
CMU_LFXOInit_TypeDef::mode
CMU_OscMode_TypeDef mode
Definition: em_cmu.h:1034
CMU_ClockEnable
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
Definition: em_cmu.c:1453
CMU_HFXOInit_TypeDef::timeout
uint8_t timeout
Definition: em_cmu.h:1091
CMU_HFPERCLKEN0_TIMER1
#define CMU_HFPERCLKEN0_TIMER1
Definition: efm32g_cmu.h:694
CMU_HFRCOBand_TypeDef
CMU_HFRCOBand_TypeDef
Definition: em_cmu.h:176
CMU_LCDClkFDIVSet
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
Definition: em_cmu.c:3502
_CMU_HFPERCLKEN0_TIMER2_SHIFT
#define _CMU_HFPERCLKEN0_TIMER2_SHIFT
Definition: efm32g_cmu.h:700
cmuOsc_LFRCO
Definition: em_cmu.h:938
CMU_HFPERCLKEN0_USART1
#define CMU_HFPERCLKEN0_USART1
Definition: efm32g_cmu.h:674
cmuClock_CORE
Definition: em_cmu.h:693
CMU_HFRCOStartupDelaySet
void CMU_HFRCOStartupDelaySet(uint32_t delay)
Set the HFRCO startup delay.
Definition: em_cmu.c:3299
cmuClock_LCD
Definition: em_cmu.h:793
_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT
#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT
Definition: efm32g_cmu.h:249
cmuClock_PCNT2
Definition: em_cmu.h:820
cmuClock_DAC0
Definition: em_cmu.h:591
cmuClock_DBG
Definition: em_cmu.h:280
CMU_HFPERCLKEN0_TIMER0
#define CMU_HFPERCLKEN0_TIMER0
Definition: efm32g_cmu.h:689
_CMU_HFPERCLKEN0_I2C0_SHIFT
#define _CMU_HFPERCLKEN0_I2C0_SHIFT
Definition: efm32g_cmu.h:740
CMU_OscMode_TypeDef
CMU_OscMode_TypeDef
Definition: em_cmu.h:954
cmuClock_HF
Definition: em_cmu.h:272
cmuOsc_HFRCO
Definition: em_cmu.h:940
CMU_OscillatorEnable
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
Definition: em_cmu.c:3594
_CMU_HFRCOCTRL_BAND_21MHZ
#define _CMU_HFRCOCTRL_BAND_21MHZ
Definition: efm32g_cmu.h:268
cmuOsc_HFXO
Definition: em_cmu.h:939
cmuSelect_Disabled
Definition: em_cmu.h:965
CMU_LOCK_LOCKKEY_LOCK
#define CMU_LOCK_LOCKKEY_LOCK
Definition: efm32g_cmu.h:1034
CMU_CMD_CALSTART
#define CMU_CMD_CALSTART
Definition: efm32g_cmu.h:393
cmuSelect_Error
Definition: em_cmu.h:964
_CMU_HFPERCLKEN0_USART2_SHIFT
#define _CMU_HFPERCLKEN0_USART2_SHIFT
Definition: efm32g_cmu.h:680
CMU
#define CMU
Definition: efm32g890f128.h:339
CMU_HFXOInit_TypeDef::glitchDetector
bool glitchDetector
Definition: em_cmu.h:1092
cmuHFRCOBand_14MHz
Definition: em_cmu.h:181
cmuClock_HFPER
Definition: em_cmu.h:401
_CMU_HFPERCLKEN0_ACMP1_SHIFT
#define _CMU_HFPERCLKEN0_ACMP1_SHIFT
Definition: efm32g_cmu.h:710
CMU_Osc_TypeDef
CMU_Osc_TypeDef
Definition: em_cmu.h:935
cmuClock_LCDpre
Definition: em_cmu.h:785
CMU_HFPERCLKEN0_PRS
#define CMU_HFPERCLKEN0_PRS
Definition: efm32g_cmu.h:714
cmuClock_LFB
Definition: em_cmu.h:840
CMU_LFBCLKEN0_LEUART1
#define CMU_LFBCLKEN0_LEUART1
Definition: efm32g_cmu.h:809
_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT
#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT
Definition: efm32g_cmu.h:925
_CMU_HFPERCLKEN0_UART0_SHIFT
#define _CMU_HFPERCLKEN0_UART0_SHIFT
Definition: efm32g_cmu.h:685
cmuOsc_AUXHFRCO
Definition: em_cmu.h:941
cmuClock_AES
Definition: em_cmu.h:701
CMU_HFXOInit_TypeDef::boost
uint8_t boost
Definition: em_cmu.h:1090
_CMU_HFPERCLKEN0_GPIO_SHIFT
#define _CMU_HFPERCLKEN0_GPIO_SHIFT
Definition: efm32g_cmu.h:725
cmuClock_USART1
Definition: em_cmu.h:437
CMU_IntClear
__STATIC_INLINE void CMU_IntClear(uint32_t flags)
Clear one or more pending CMU interrupts.
Definition: em_cmu.h:1332
BUS_RegBitWrite
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
cmuClock_PCNT0
Definition: em_cmu.h:802
CMU_OscillatorTuningGet
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
Definition: em_cmu.c:3772
cmuOsc_LFXO
Definition: em_cmu.h:937
CMU_LFXOInit
void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)
Set LFXO control registers.
Definition: em_cmu.c:3534
CMU_IntEnable
__STATIC_INLINE void CMU_IntEnable(uint32_t flags)
Enable one or more CMU interrupts.
Definition: em_cmu.h:1363
_CMU_LFACLKEN0_LCD_SHIFT
#define _CMU_LFACLKEN0_LCD_SHIFT
Definition: efm32g_cmu.h:796
CMU_HFRCOBandSet
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
Set HFRCO band and the tuning value based on the value in the calibration table made during productio...
Definition: em_cmu.c:3049
CMU_PCNTClockExternalGet
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
Definition: em_cmu.c:4019
_CMU_HFCORECLKEN0_DMA_SHIFT
#define _CMU_HFCORECLKEN0_DMA_SHIFT
Definition: efm32g_cmu.h:651
CMU_ClockFreqGet
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
Definition: em_cmu.c:1550
cmuClock_ADC0
Definition: em_cmu.h:636
CMU_HFXOInit_TypeDef::mode
CMU_OscMode_TypeDef mode
Definition: em_cmu.h:1094
CMU_HFCORECLKEN0_DMA
#define CMU_HFCORECLKEN0_DMA
Definition: efm32g_cmu.h:650
cmuHFRCOBand_1MHz
Definition: em_cmu.h:178
_CMU_HFCORECLKEN0_EBI_SHIFT
#define _CMU_HFCORECLKEN0_EBI_SHIFT
Definition: efm32g_cmu.h:661
CMU_Unlock
__STATIC_INLINE void CMU_Unlock(void)
Unlock the CMU so that writing to locked registers again is possible.
Definition: em_cmu.h:1489
CMU_PCNTCTRL_PCNT1CLKEN
#define CMU_PCNTCTRL_PCNT1CLKEN
Definition: efm32g_cmu.h:938
cmuClock_AUX
Definition: em_cmu.h:287
_CMU_HFRCOCTRL_BAND_11MHZ
#define _CMU_HFRCOCTRL_BAND_11MHZ
Definition: efm32g_cmu.h:265
cmuClock_HFLE
Definition: em_cmu.h:719
CMU_ClockDivSet
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
Definition: em_cmu.c:1244
cmuClock_RTC
Definition: em_cmu.h:767
CMU_HFPERCLKEN0_I2C0
#define CMU_HFPERCLKEN0_I2C0
Definition: efm32g_cmu.h:739
cmuClock_LEUART1
Definition: em_cmu.h:866
CMU_ClockDivGet
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
Definition: em_cmu.c:1112
CMU_ClockSelectGet
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.
Definition: em_cmu.c:2146
CMU_LFACLKEN0_LETIMER0
#define CMU_LFACLKEN0_LETIMER0
Definition: efm32g_cmu.h:790