efm32g/html/efm32g890f128_8h_source.html

 /**************************************************************************/

 #ifndef EFM32G890F128_H

 #define EFM32G890F128_H


 #ifdef __cplusplus

 extern "C" {

 #endif


 /**************************************************************************/

 /**************************************************************************/

 typedef enum IRQn

 {

 /******  Cortex-M3 Processor Exceptions Numbers ********************************************/

   NonMaskableInt_IRQn   = -14,

   HardFault_IRQn        = -13,

   MemoryManagement_IRQn = -12,

   BusFault_IRQn         = -11,

   UsageFault_IRQn       = -10,

   SVCall_IRQn           = -5,

   DebugMonitor_IRQn     = -4,

   PendSV_IRQn           = -2,

   SysTick_IRQn          = -1,

 /******  EFM32G Peripheral Interrupt Numbers ***********************************************/

   DMA_IRQn              = 0,

   GPIO_EVEN_IRQn        = 1,

   TIMER0_IRQn           = 2,

   USART0_RX_IRQn        = 3,

   USART0_TX_IRQn        = 4,

   ACMP0_IRQn            = 5,

   ADC0_IRQn             = 6,

   DAC0_IRQn             = 7,

   I2C0_IRQn             = 8,

   GPIO_ODD_IRQn         = 9,

   TIMER1_IRQn           = 10,

   TIMER2_IRQn           = 11,

   USART1_RX_IRQn        = 12,

   USART1_TX_IRQn        = 13,

   USART2_RX_IRQn        = 14,

   USART2_TX_IRQn        = 15,

   UART0_RX_IRQn         = 16,

   UART0_TX_IRQn         = 17,

   LEUART0_IRQn          = 18,

   LEUART1_IRQn          = 19,

   LETIMER0_IRQn         = 20,

   PCNT0_IRQn            = 21,

   PCNT1_IRQn            = 22,

   PCNT2_IRQn            = 23,

   RTC_IRQn              = 24,

   CMU_IRQn              = 25,

   VCMP_IRQn             = 26,

   LCD_IRQn              = 27,

   MSC_IRQn              = 28,

   AES_IRQn              = 29,

 } IRQn_Type;


 /**************************************************************************/

 #define __MPU_PRESENT             1

 #define __VTOR_PRESENT            1

 #define __NVIC_PRIO_BITS          3

 #define __Vendor_SysTickConfig    0

 /**************************************************************************/

 #define _EFM32_GECKO_FAMILY                     1

 #define _EFM_DEVICE

 #define _SILICON_LABS_32B_SERIES_0

 #define _SILICON_LABS_32B_SERIES                0

 #define _SILICON_LABS_GECKO_INTERNAL_SDID       71

 #define _SILICON_LABS_GECKO_INTERNAL_SDID_71

 #define _SILICON_LABS_32B_PLATFORM_1

 #define _SILICON_LABS_32B_PLATFORM              1

 /* If part number is not defined as compiler option, define it */

 #if !defined(EFM32G890F128)

 #define EFM32G890F128    1

 #endif


 #define PART_NUMBER          "EFM32G890F128"

 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)

 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL)

 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)

 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)

 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL)

 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)

 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL)

 #define AES_MEM_BITS         ((uint32_t) 0x10UL)

 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL)

 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)

 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL)

 #define PER_MEM_BITS         ((uint32_t) 0x20UL)

 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL)

 #define RAM_MEM_SIZE         ((uint32_t) 0x8000UL)

 #define RAM_MEM_END          ((uint32_t) 0x20007FFFUL)

 #define RAM_MEM_BITS         ((uint32_t) 0x15UL)

 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL)

 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x4000UL)

 #define RAM_CODE_MEM_END     ((uint32_t) 0x10003FFFUL)

 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x14UL)

 #define EBI_MEM_BASE         ((uint32_t) 0x80000000UL)

 #define EBI_MEM_SIZE         ((uint32_t) 0x10000000UL)

 #define EBI_MEM_END          ((uint32_t) 0x8FFFFFFFUL)

 #define EBI_MEM_BITS         ((uint32_t) 0x28UL)

 #define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL)

 #define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL)

 #define FLASH_BASE           (0x00000000UL)

 #define FLASH_SIZE           (0x00020000UL)

 #define FLASH_PAGE_SIZE      512

 #define SRAM_BASE            (0x20000000UL)

 #define SRAM_SIZE            (0x00004000UL)

 #define __CM3_REV            0x200

 #define PRS_CHAN_COUNT       8

 #define DMA_CHAN_COUNT       8

 #define EXT_IRQ_COUNT        31

 #define AFCHAN_MAX           79

 #define AFCHANLOC_MAX        4


 #define AFACHAN_MAX          37


 /* Part number capabilities */


 #define TIMER_PRESENT

 #define TIMER_COUNT         3

 #define USART_PRESENT

 #define USART_COUNT         3

 #define UART_PRESENT

 #define UART_COUNT          1

 #define LEUART_PRESENT

 #define LEUART_COUNT        2

 #define LETIMER_PRESENT

 #define LETIMER_COUNT       1

 #define PCNT_PRESENT

 #define PCNT_COUNT          3

 #define ACMP_PRESENT

 #define ACMP_COUNT          2

 #define DAC_PRESENT

 #define DAC_COUNT           1

 #define ADC_PRESENT

 #define ADC_COUNT           1

 #define I2C_PRESENT

 #define I2C_COUNT           1

 #define AES_PRESENT

 #define AES_COUNT           1

 #define DMA_PRESENT

 #define DMA_COUNT           1

 #define LE_PRESENT

 #define LE_COUNT            1

 #define MSC_PRESENT

 #define MSC_COUNT           1

 #define EMU_PRESENT

 #define EMU_COUNT           1

 #define RMU_PRESENT

 #define RMU_COUNT           1

 #define CMU_PRESENT

 #define CMU_COUNT           1

 #define EBI_PRESENT

 #define EBI_COUNT           1

 #define RTC_PRESENT

 #define RTC_COUNT           1

 #define PRS_PRESENT

 #define PRS_COUNT           1

 #define GPIO_PRESENT

 #define GPIO_COUNT          1

 #define VCMP_PRESENT

 #define VCMP_COUNT          1

 #define LCD_PRESENT

 #define LCD_COUNT           1

 #define HFXTAL_PRESENT

 #define HFXTAL_COUNT        1

 #define LFXTAL_PRESENT

 #define LFXTAL_COUNT        1

 #define WDOG_PRESENT

 #define WDOG_COUNT          1

 #define DBG_PRESENT

 #define DBG_COUNT           1

 #define BOOTLOADER_PRESENT

 #define BOOTLOADER_COUNT    1

 #define ANALOG_PRESENT

 #define ANALOG_COUNT        1


 #include "core_cm3.h"      /* Cortex-M3 processor and core peripherals */

 #include "system_efm32g.h" /* System Header */


 /**************************************************************************/

 #include "efm32g_aes.h"

 #include "efm32g_dma_ch.h"

 #include "efm32g_dma.h"

 #include "efm32g_msc.h"

 #include "efm32g_emu.h"

 #include "efm32g_rmu.h"

 #include "efm32g_cmu.h"

 #include "efm32g_ebi.h"

 #include "efm32g_timer_cc.h"

 #include "efm32g_timer.h"

 #include "efm32g_usart.h"

 #include "efm32g_leuart.h"

 #include "efm32g_rtc.h"

 #include "efm32g_letimer.h"

 #include "efm32g_pcnt.h"

 #include "efm32g_acmp.h"

 #include "efm32g_prs_ch.h"

 #include "efm32g_prs.h"

 #include "efm32g_dac.h"

 #include "efm32g_gpio_p.h"

 #include "efm32g_gpio.h"

 #include "efm32g_vcmp.h"

 #include "efm32g_adc.h"

 #include "efm32g_i2c.h"

 #include "efm32g_lcd.h"

 #include "efm32g_wdog.h"

 #include "efm32g_dma_descriptor.h"

 #include "efm32g_devinfo.h"

 #include "efm32g_romtable.h"

 #include "efm32g_calibrate.h"


 /**************************************************************************/

 #define AES_BASE          (0x400E0000UL)

 #define DMA_BASE          (0x400C2000UL)

 #define MSC_BASE          (0x400C0000UL)

 #define EMU_BASE          (0x400C6000UL)

 #define RMU_BASE          (0x400CA000UL)

 #define CMU_BASE          (0x400C8000UL)

 #define EBI_BASE          (0x40008000UL)

 #define TIMER0_BASE       (0x40010000UL)

 #define TIMER1_BASE       (0x40010400UL)

 #define TIMER2_BASE       (0x40010800UL)

 #define USART0_BASE       (0x4000C000UL)

 #define USART1_BASE       (0x4000C400UL)

 #define USART2_BASE       (0x4000C800UL)

 #define UART0_BASE        (0x4000E000UL)

 #define LEUART0_BASE      (0x40084000UL)

 #define LEUART1_BASE      (0x40084400UL)

 #define RTC_BASE          (0x40080000UL)

 #define LETIMER0_BASE     (0x40082000UL)

 #define PCNT0_BASE        (0x40086000UL)

 #define PCNT1_BASE        (0x40086400UL)

 #define PCNT2_BASE        (0x40086800UL)

 #define ACMP0_BASE        (0x40001000UL)

 #define ACMP1_BASE        (0x40001400UL)

 #define PRS_BASE          (0x400CC000UL)

 #define DAC0_BASE         (0x40004000UL)

 #define GPIO_BASE         (0x40006000UL)

 #define VCMP_BASE         (0x40000000UL)

 #define ADC0_BASE         (0x40002000UL)

 #define I2C0_BASE         (0x4000A000UL)

 #define LCD_BASE          (0x4008A000UL)

 #define WDOG_BASE         (0x40088000UL)

 #define CALIBRATE_BASE    (0x0FE08000UL)

 #define DEVINFO_BASE      (0x0FE081B0UL)

 #define ROMTABLE_BASE     (0xE00FFFD0UL)

 #define LOCKBITS_BASE     (0x0FE04000UL)

 #define USERDATA_BASE     (0x0FE00000UL)

 /**************************************************************************/

 #define AES          ((AES_TypeDef *) AES_BASE)

 #define DMA          ((DMA_TypeDef *) DMA_BASE)

 #define MSC          ((MSC_TypeDef *) MSC_BASE)

 #define EMU          ((EMU_TypeDef *) EMU_BASE)

 #define RMU          ((RMU_TypeDef *) RMU_BASE)

 #define CMU          ((CMU_TypeDef *) CMU_BASE)

 #define EBI          ((EBI_TypeDef *) EBI_BASE)

 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)

 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)

 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)

 #define USART0       ((USART_TypeDef *) USART0_BASE)

 #define USART1       ((USART_TypeDef *) USART1_BASE)

 #define USART2       ((USART_TypeDef *) USART2_BASE)

 #define UART0        ((USART_TypeDef *) UART0_BASE)

 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)

 #define LEUART1      ((LEUART_TypeDef *) LEUART1_BASE)

 #define RTC          ((RTC_TypeDef *) RTC_BASE)

 #define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)

 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)

 #define PCNT1        ((PCNT_TypeDef *) PCNT1_BASE)

 #define PCNT2        ((PCNT_TypeDef *) PCNT2_BASE)

 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)

 #define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)

 #define PRS          ((PRS_TypeDef *) PRS_BASE)

 #define DAC0         ((DAC_TypeDef *) DAC0_BASE)

 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)

 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)

 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)

 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)

 #define LCD          ((LCD_TypeDef *) LCD_BASE)

 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)

 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE)

 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)

 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)

 /**************************************************************************/

 #include "efm32g_prs_signals.h"

 #include "efm32g_dmareq.h"

 #include "efm32g_dmactrl.h"

 #include "efm32g_uart.h"


 /**************************************************************************/

 #define MSC_UNLOCK_CODE      0x1B71

 #define EMU_UNLOCK_CODE      0xADE8

 #define CMU_UNLOCK_CODE      0x580E

 #define TIMER_UNLOCK_CODE    0xCE80

 #define GPIO_UNLOCK_CODE     0xA534

 /**************************************************************************/

 #include "efm32g_af_ports.h"

 #include "efm32g_af_pins.h"


 /**************************************************************************/

 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \

   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));


 #ifdef __cplusplus

 }

 #endif

 #endif /* EFM32G890F128_H */

efm32g_adc.h
EFM32G_ADC register and bit field definitions.

efm32g_wdog.h
EFM32G_WDOG register and bit field definitions.

USART0_RX_IRQn
Definition: efm32g890f128.h:69

efm32g_i2c.h
EFM32G_I2C register and bit field definitions.

GPIO_EVEN_IRQn
Definition: efm32g890f128.h:67

PCNT0_IRQn
Definition: efm32g890f128.h:87

efm32g_devinfo.h
EFM32G_DEVINFO register and bit field definitions.

efm32g_gpio.h
EFM32G_GPIO register and bit field definitions.

efm32g_letimer.h
EFM32G_LETIMER register and bit field definitions.

TIMER0_IRQn
Definition: efm32g890f128.h:68

efm32g_calibrate.h
EFM32G_CALIBRATE register and bit field definitions.

efm32g_cmu.h
EFM32G_CMU register and bit field definitions.

MSC_IRQn
Definition: efm32g890f128.h:94

DMA_IRQn
Definition: efm32g890f128.h:66

PendSV_IRQn
Definition: efm32g890f128.h:62

TIMER1_IRQn
Definition: efm32g890f128.h:76

PCNT1_IRQn
Definition: efm32g890f128.h:88

IRQn_Type
enum IRQn IRQn_Type

BusFault_IRQn
Definition: efm32g890f128.h:58

LCD_IRQn
Definition: efm32g890f128.h:93

efm32g_pcnt.h
EFM32G_PCNT register and bit field definitions.

PCNT2_IRQn
Definition: efm32g890f128.h:89

UART0_RX_IRQn
Definition: efm32g890f128.h:82

efm32g_leuart.h
EFM32G_LEUART register and bit field definitions.

efm32g_rtc.h
EFM32G_RTC register and bit field definitions.

efm32g_usart.h
EFM32G_USART register and bit field definitions.

efm32g_dma.h
EFM32G_DMA register and bit field definitions.

efm32g_uart.h
EFM32G_UART register and bit field definitions.

LEUART1_IRQn
Definition: efm32g890f128.h:85

efm32g_rmu.h
EFM32G_RMU register and bit field definitions.

TIMER2_IRQn
Definition: efm32g890f128.h:77

efm32g_romtable.h
EFM32G_ROMTABLE register and bit field definitions.

UsageFault_IRQn
Definition: efm32g890f128.h:59

efm32g_timer.h
EFM32G_TIMER register and bit field definitions.

RTC_IRQn
Definition: efm32g890f128.h:90

USART2_RX_IRQn
Definition: efm32g890f128.h:80

efm32g_dma_descriptor.h
EFM32G_DMA_DESCRIPTOR register and bit field definitions.

efm32g_dmactrl.h
EFM32G_DMACTRL register and bit field definitions.

efm32g_af_pins.h
EFM32G_AF_PINS register and bit field definitions.

AES_IRQn
Definition: efm32g890f128.h:95

USART1_RX_IRQn
Definition: efm32g890f128.h:78

efm32g_msc.h
EFM32G_MSC register and bit field definitions.

HardFault_IRQn
Definition: efm32g890f128.h:56

efm32g_vcmp.h
EFM32G_VCMP register and bit field definitions.

CMU_IRQn
Definition: efm32g890f128.h:91

efm32g_prs_ch.h
EFM32G_PRS_CH register and bit field definitions.

efm32g_dma_ch.h
EFM32G_DMA_CH register and bit field definitions.

system_efm32g.h
CMSIS Cortex-M3 System Layer for EFM32G devices.

efm32g_prs.h
EFM32G_PRS register and bit field definitions.

ADC0_IRQn
Definition: efm32g890f128.h:72

efm32g_timer_cc.h
EFM32G_TIMER_CC register and bit field definitions.

SVCall_IRQn
Definition: efm32g890f128.h:60

UART0_TX_IRQn
Definition: efm32g890f128.h:83

SysTick_IRQn
Definition: efm32g890f128.h:63

USART1_TX_IRQn
Definition: efm32g890f128.h:79

ACMP0_IRQn
Definition: efm32g890f128.h:71

efm32g_dac.h
EFM32G_DAC register and bit field definitions.

efm32g_lcd.h
EFM32G_LCD register and bit field definitions.

USART0_TX_IRQn
Definition: efm32g890f128.h:70

USART2_TX_IRQn
Definition: efm32g890f128.h:81

MemoryManagement_IRQn
Definition: efm32g890f128.h:57

efm32g_gpio_p.h
EFM32G_GPIO_P register and bit field definitions.

I2C0_IRQn
Definition: efm32g890f128.h:74

VCMP_IRQn
Definition: efm32g890f128.h:92

LEUART0_IRQn
Definition: efm32g890f128.h:84

efm32g_aes.h
EFM32G_AES register and bit field definitions.

efm32g_ebi.h
EFM32G_EBI register and bit field definitions.

IRQn
IRQn
Definition: efm32g890f128.h:52

LETIMER0_IRQn
Definition: efm32g890f128.h:86

NonMaskableInt_IRQn
Definition: efm32g890f128.h:55

DAC0_IRQn
Definition: efm32g890f128.h:73

GPIO_ODD_IRQn
Definition: efm32g890f128.h:75

DebugMonitor_IRQn
Definition: efm32g890f128.h:61

efm32g_emu.h
EFM32G_EMU register and bit field definitions.

efm32g_dmareq.h
EFM32G_DMAREQ register and bit field definitions.

efm32g_acmp.h
EFM32G_ACMP register and bit field definitions.