EZR32 Wonder Gecko Software Documentation
ezr32wg-doc-5.1.2
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CMSIS Cortex-M Peripheral Access Layer Header File for EZR32WG330F256R69.
Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file ezr32wg330f256r69.h.
#include "core_cm4.h"
#include "system_ezr32wg.h"
#include "ezr32wg_dma_ch.h"
#include "ezr32wg_dma.h"
#include "ezr32wg_aes.h"
#include "ezr32wg_usb_hc.h"
#include "ezr32wg_usb_diep.h"
#include "ezr32wg_usb_doep.h"
#include "ezr32wg_usb.h"
#include "ezr32wg_msc.h"
#include "ezr32wg_emu.h"
#include "ezr32wg_rmu.h"
#include "ezr32wg_cmu.h"
#include "ezr32wg_lesense_st.h"
#include "ezr32wg_lesense_buf.h"
#include "ezr32wg_lesense_ch.h"
#include "ezr32wg_lesense.h"
#include "ezr32wg_fpueh.h"
#include "ezr32wg_usart.h"
#include "ezr32wg_timer_cc.h"
#include "ezr32wg_timer.h"
#include "ezr32wg_acmp.h"
#include "ezr32wg_leuart.h"
#include "ezr32wg_rtc.h"
#include "ezr32wg_letimer.h"
#include "ezr32wg_pcnt.h"
#include "ezr32wg_i2c.h"
#include "ezr32wg_gpio_p.h"
#include "ezr32wg_gpio.h"
#include "ezr32wg_vcmp.h"
#include "ezr32wg_prs_ch.h"
#include "ezr32wg_prs.h"
#include "ezr32wg_adc.h"
#include "ezr32wg_dac.h"
#include "ezr32wg_burtc_ret.h"
#include "ezr32wg_burtc.h"
#include "ezr32wg_wdog.h"
#include "ezr32wg_etm.h"
#include "ezr32wg_dma_descriptor.h"
#include "ezr32wg_devinfo.h"
#include "ezr32wg_romtable.h"
#include "ezr32wg_calibrate.h"
#include "ezr32wg_prs_signals.h"
#include "ezr32wg_dmareq.h"
#include "ezr32wg_dmactrl.h"
#include "ezr32wg_usartrf.h"
#include "ezr32wg_uart.h"
#include "ezr32wg_af_ports.h"
#include "ezr32wg_af_pins.h"
Go to the source code of this file.
Macros | |
#define | __CM4_REV 0x001 |
#define | __FPU_PRESENT 1 |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 3 |
#define | __Vendor_SysTickConfig 0 |
#define | __VTOR_PRESENT 1 |
#define | _EFM32_WONDER_FAMILY 1 |
#define | _EFM_DEVICE |
#define | _EZR32_WONDER_FAMILY 1 |
#define | _EZR_DEVICE |
#define | _SILICON_LABS_32B_PLATFORM 1 |
#define | _SILICON_LABS_32B_PLATFORM_1 |
#define | _SILICON_LABS_32B_SERIES 0 |
#define | _SILICON_LABS_32B_SERIES_0 |
#define | _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ |
#define | _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ |
#define | ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) |
#define | ACMP0_BASE (0x40001000UL) |
#define | ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) |
#define | ACMP1_BASE (0x40001400UL) |
#define | ACMP_COUNT 2 |
#define | ACMP_PRESENT |
#define | ADC0 ((ADC_TypeDef *) ADC0_BASE) |
#define | ADC0_BASE (0x40002000UL) |
#define | ADC_COUNT 1 |
#define | ADC_PRESENT |
#define | AES ((AES_TypeDef *) AES_BASE) |
#define | AES_BASE (0x400E0000UL) |
#define | AES_COUNT 1 |
#define | AES_MEM_BASE ((uint32_t) 0x400E0000UL) |
#define | AES_MEM_BITS ((uint32_t) 0x10UL) |
#define | AES_MEM_END ((uint32_t) 0x400E03FFUL) |
#define | AES_MEM_SIZE ((uint32_t) 0x400UL) |
#define | AES_PRESENT |
#define | AFACHAN_MAX 50 |
#define | AFCHAN_MAX 84 |
#define | AFCHANLOC_MAX 7 |
#define | ANALOG_COUNT 1 |
#define | ANALOG_PRESENT |
#define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
#define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
#define | BOOTLOADER_COUNT 1 |
#define | BOOTLOADER_PRESENT |
#define | BU_COUNT 1 |
#define | BU_PRESENT |
#define | BURTC ((BURTC_TypeDef *) BURTC_BASE) |
#define | BURTC_BASE (0x40081000UL) |
#define | BURTC_COUNT 1 |
#define | BURTC_PRESENT |
#define | BURTC_UNLOCK_CODE 0xAEE8 |
#define | CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) |
#define | CALIBRATE_BASE (0x0FE08000UL) |
#define | CMU ((CMU_TypeDef *) CMU_BASE) |
#define | CMU_BASE (0x400C8000UL) |
#define | CMU_COUNT 1 |
#define | CMU_PRESENT |
#define | CMU_UNLOCK_CODE 0x580E |
#define | DAC0 ((DAC_TypeDef *) DAC0_BASE) |
#define | DAC0_BASE (0x40004000UL) |
#define | DAC_COUNT 1 |
#define | DAC_PRESENT |
#define | DBG_COUNT 1 |
#define | DBG_PRESENT |
#define | DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) |
#define | DEVINFO_BASE (0x0FE081A8UL) |
#define | DMA ((DMA_TypeDef *) DMA_BASE) |
#define | DMA_BASE (0x400C2000UL) |
#define | DMA_CHAN_COUNT 12 |
#define | DMA_COUNT 1 |
#define | DMA_PRESENT |
#define | EMU ((EMU_TypeDef *) EMU_BASE) |
#define | EMU_BASE (0x400C6000UL) |
#define | EMU_COUNT 1 |
#define | EMU_PRESENT |
#define | EMU_UNLOCK_CODE 0xADE8 |
#define | ETM ((ETM_TypeDef *) ETM_BASE) |
#define | ETM_BASE (0xE0041000UL) |
#define | ETM_COUNT 1 |
#define | ETM_PRESENT |
#define | EXT_IRQ_COUNT 39 |
#define | FLASH_BASE (0x00000000UL) |
#define | FLASH_MEM_BASE ((uint32_t) 0x0UL) |
#define | FLASH_MEM_BITS ((uint32_t) 0x28UL) |
#define | FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) |
#define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | FLASH_PAGE_SIZE 2048 |
#define | FLASH_SIZE (0x00040000UL) |
#define | FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) |
#define | FPUEH_BASE (0x400C1C00UL) |
#define | FPUEH_COUNT 1 |
#define | FPUEH_PRESENT |
#define | GPIO ((GPIO_TypeDef *) GPIO_BASE) |
#define | GPIO_BASE (0x40006000UL) |
#define | GPIO_COUNT 1 |
#define | GPIO_PRESENT |
#define | GPIO_UNLOCK_CODE 0xA534 |
#define | HFXTAL_COUNT 1 |
#define | HFXTAL_PRESENT |
#define | I2C0 ((I2C_TypeDef *) I2C0_BASE) |
#define | I2C0_BASE (0x4000A000UL) |
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define | I2C1_BASE (0x4000A400UL) |
#define | I2C_COUNT 2 |
#define | I2C_PRESENT |
#define | LE_COUNT 1 |
#define | LE_PRESENT |
#define | LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) |
#define | LESENSE_BASE (0x4008C000UL) |
#define | LESENSE_COUNT 1 |
#define | LESENSE_PRESENT |
#define | LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) |
#define | LETIMER0_BASE (0x40082000UL) |
#define | LETIMER_COUNT 1 |
#define | LETIMER_PRESENT |
#define | LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) |
#define | LEUART0_BASE (0x40084000UL) |
#define | LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) |
#define | LEUART1_BASE (0x40084400UL) |
#define | LEUART_COUNT 2 |
#define | LEUART_PRESENT |
#define | LFXTAL_COUNT 1 |
#define | LFXTAL_PRESENT |
#define | LOCKBITS_BASE (0x0FE04000UL) |
#define | MSC ((MSC_TypeDef *) MSC_BASE) |
#define | MSC_BASE (0x400C0000UL) |
#define | MSC_COUNT 1 |
#define | MSC_PRESENT |
#define | MSC_UNLOCK_CODE 0x1B71 |
#define | OPAMP_COUNT 1 |
#define | OPAMP_PRESENT |
#define | PART_NUMBER "EZR32WG330F256R69" |
#define | PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) |
#define | PCNT0_BASE (0x40086000UL) |
#define | PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) |
#define | PCNT1_BASE (0x40086400UL) |
#define | PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) |
#define | PCNT2_BASE (0x40086800UL) |
#define | PCNT_COUNT 3 |
#define | PCNT_PRESENT |
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
#define | PER_MEM_BITS ((uint32_t) 0x20UL) |
#define | PER_MEM_END ((uint32_t) 0x400DFFFFUL) |
#define | PER_MEM_SIZE ((uint32_t) 0xE0000UL) |
#define | PRS ((PRS_TypeDef *) PRS_BASE) |
#define | PRS_BASE (0x400CC000UL) |
#define | PRS_CHAN_COUNT 12 |
#define | PRS_COUNT 1 |
#define | PRS_PRESENT |
#define | RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
#define | RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) |
#define | RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) |
#define | RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM_MEM_BITS ((uint32_t) 0x18UL) |
#define | RAM_MEM_END ((uint32_t) 0x2003FFFFUL) |
#define | RAM_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | RF_COUNT 1 |
#define | RF_GPIO0_PIN 15 |
#define | RF_GPIO0_PORT 0 |
#define | RF_GPIO1_PIN 14 |
#define | RF_GPIO1_PORT 4 |
#define | RF_INT_PIN 13 |
#define | RF_INT_PORT 4 |
#define | RF_PRESENT |
#define | RF_SDN_PIN 8 |
#define | RF_SDN_PORT 4 |
#define | RF_USARTRF_CLK_PIN 12 |
#define | RF_USARTRF_CLK_PORT 4 |
#define | RF_USARTRF_CS_PIN 9 |
#define | RF_USARTRF_CS_PORT 4 |
#define | RF_USARTRF_LOCATION 0 |
#define | RF_USARTRF_MISO_PIN 11 |
#define | RF_USARTRF_MISO_PORT 4 |
#define | RF_USARTRF_MOSI_PIN 10 |
#define | RF_USARTRF_MOSI_PORT 4 |
#define | RMU ((RMU_TypeDef *) RMU_BASE) |
#define | RMU_BASE (0x400CA000UL) |
#define | RMU_COUNT 1 |
#define | RMU_PRESENT |
#define | ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) |
#define | ROMTABLE_BASE (0xE00FFFD0UL) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | RTC_BASE (0x40080000UL) |
#define | RTC_COUNT 1 |
#define | RTC_PRESENT |
#define | SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register. More... | |
#define | SRAM_BASE (0x20000000UL) |
#define | SRAM_SIZE (0x00008000UL) |
#define | TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) |
#define | TIMER0_BASE (0x40010000UL) |
#define | TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) |
#define | TIMER1_BASE (0x40010400UL) |
#define | TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) |
#define | TIMER2_BASE (0x40010800UL) |
#define | TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) |
#define | TIMER3_BASE (0x40010C00UL) |
#define | TIMER_COUNT 4 |
#define | TIMER_PRESENT |
#define | TIMER_UNLOCK_CODE 0xCE80 |
#define | UART0 ((USART_TypeDef *) UART0_BASE) |
#define | UART0_BASE (0x4000E000UL) |
#define | UART1 ((USART_TypeDef *) UART1_BASE) |
#define | UART1_BASE (0x4000E400UL) |
#define | UART_COUNT 2 |
#define | UART_PRESENT |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | USART1_BASE (0x4000C400UL) |
#define | USART2 ((USART_TypeDef *) USART2_BASE) |
#define | USART2_BASE (0x4000C800UL) |
#define | USART_COUNT 2 |
#define | USART_PRESENT |
#define | USARTRF0 ((USART_TypeDef *) USARTRF0_BASE) |
#define | USARTRF0_BASE (0x4000C000UL) |
#define | USARTRF_COUNT 1 |
#define | USARTRF_PRESENT |
#define | USB ((USB_TypeDef *) USB_BASE) |
#define | USB_BASE (0x400C4000UL) |
#define | USB_COUNT 1 |
#define | USB_PRESENT |
#define | USBC_COUNT 1 |
#define | USBC_MEM_BASE ((uint32_t) 0x40100000UL) |
#define | USBC_MEM_BITS ((uint32_t) 0x18UL) |
#define | USBC_MEM_END ((uint32_t) 0x4013FFFFUL) |
#define | USBC_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | USBC_PRESENT |
#define | USERDATA_BASE (0x0FE00000UL) |
#define | VCMP ((VCMP_TypeDef *) VCMP_BASE) |
#define | VCMP_BASE (0x40000000UL) |
#define | VCMP_COUNT 1 |
#define | VCMP_PRESENT |
#define | WDOG ((WDOG_TypeDef *) WDOG_BASE) |
#define | WDOG_BASE (0x40088000UL) |
#define | WDOG_COUNT 1 |
#define | WDOG_PRESENT |
Typedefs | |
typedef enum IRQn | IRQn_Type |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, USARTRF0_RX_IRQn = 3, USARTRF0_TX_IRQn = 4, USB_IRQn = 5, ACMP0_IRQn = 6, ADC0_IRQn = 7, DAC0_IRQn = 8, I2C0_IRQn = 9, I2C1_IRQn = 10, GPIO_ODD_IRQn = 11, TIMER1_IRQn = 12, TIMER2_IRQn = 13, TIMER3_IRQn = 14, USART1_RX_IRQn = 15, USART1_TX_IRQn = 16, LESENSE_IRQn = 17, USART2_RX_IRQn = 18, USART2_TX_IRQn = 19, UART0_RX_IRQn = 20, UART0_TX_IRQn = 21, UART1_RX_IRQn = 22, UART1_TX_IRQn = 23, LEUART0_IRQn = 24, LEUART1_IRQn = 25, LETIMER0_IRQn = 26, PCNT0_IRQn = 27, PCNT1_IRQn = 28, PCNT2_IRQn = 29, RTC_IRQn = 30, BURTC_IRQn = 31, CMU_IRQn = 32, VCMP_IRQn = 33, MSC_IRQn = 35, AES_IRQn = 36, EMU_IRQn = 38, FPUEH_IRQn = 39 } |