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ezr32wg_msc.h
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1
/**************************************************************************/
32
/**************************************************************************/
36
/**************************************************************************/
41
typedef
struct
42
{
43
__IOM uint32_t
CTRL
;
44
__IOM uint32_t
READCTRL
;
45
__IOM uint32_t
WRITECTRL
;
46
__IOM uint32_t
WRITECMD
;
47
__IOM uint32_t
ADDRB
;
49
uint32_t RESERVED0[1];
50
__IOM uint32_t
WDATA
;
51
__IM uint32_t
STATUS
;
53
uint32_t RESERVED1[3];
54
__IM uint32_t
IF
;
55
__IOM uint32_t
IFS
;
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__IOM uint32_t
IFC
;
57
__IOM uint32_t
IEN
;
58
__IOM uint32_t
LOCK
;
59
__IOM uint32_t
CMD
;
60
__IM uint32_t
CACHEHITS
;
61
__IM uint32_t
CACHEMISSES
;
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uint32_t RESERVED2[1];
63
__IOM uint32_t
TIMEBASE
;
64
__IOM uint32_t
MASSLOCK
;
65
}
MSC_TypeDef
;
67
/**************************************************************************/
72
/* Bit fields for MSC CTRL */
73
#define _MSC_CTRL_RESETVALUE 0x00000001UL
74
#define _MSC_CTRL_MASK 0x00000001UL
75
#define MSC_CTRL_BUSFAULT (0x1UL << 0)
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#define _MSC_CTRL_BUSFAULT_SHIFT 0
77
#define _MSC_CTRL_BUSFAULT_MASK 0x1UL
78
#define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
79
#define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
80
#define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
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#define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
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#define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
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#define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
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/* Bit fields for MSC READCTRL */
86
#define _MSC_READCTRL_RESETVALUE 0x00000001UL
87
#define _MSC_READCTRL_MASK 0x000300FFUL
88
#define _MSC_READCTRL_MODE_SHIFT 0
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#define _MSC_READCTRL_MODE_MASK 0x7UL
90
#define _MSC_READCTRL_MODE_WS0 0x00000000UL
91
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
92
#define _MSC_READCTRL_MODE_WS1 0x00000001UL
93
#define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL
94
#define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL
95
#define _MSC_READCTRL_MODE_WS2 0x00000004UL
96
#define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL
97
#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
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#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
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#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
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#define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0)
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#define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0)
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#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0)
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#define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0)
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#define MSC_READCTRL_IFCDIS (0x1UL << 3)
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#define _MSC_READCTRL_IFCDIS_SHIFT 3
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#define _MSC_READCTRL_IFCDIS_MASK 0x8UL
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#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL
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#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3)
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#define MSC_READCTRL_AIDIS (0x1UL << 4)
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#define _MSC_READCTRL_AIDIS_SHIFT 4
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#define _MSC_READCTRL_AIDIS_MASK 0x10UL
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#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL
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#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4)
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#define MSC_READCTRL_ICCDIS (0x1UL << 5)
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#define _MSC_READCTRL_ICCDIS_SHIFT 5
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#define _MSC_READCTRL_ICCDIS_MASK 0x20UL
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#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL
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#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5)
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#define MSC_READCTRL_EBICDIS (0x1UL << 6)
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#define _MSC_READCTRL_EBICDIS_SHIFT 6
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#define _MSC_READCTRL_EBICDIS_MASK 0x40UL
122
#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL
123
#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6)
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#define MSC_READCTRL_RAMCEN (0x1UL << 7)
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#define _MSC_READCTRL_RAMCEN_SHIFT 7
126
#define _MSC_READCTRL_RAMCEN_MASK 0x80UL
127
#define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL
128
#define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7)
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#define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16
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#define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL
131
#define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL
132
#define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL
133
#define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL
134
#define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL
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#define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL
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#define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16)
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#define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16)
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#define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16)
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#define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16)
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#define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16)
142
/* Bit fields for MSC WRITECTRL */
143
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
144
#define _MSC_WRITECTRL_MASK 0x00000003UL
145
#define MSC_WRITECTRL_WREN (0x1UL << 0)
146
#define _MSC_WRITECTRL_WREN_SHIFT 0
147
#define _MSC_WRITECTRL_WREN_MASK 0x1UL
148
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
149
#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
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#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
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#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
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#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
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#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
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#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
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/* Bit fields for MSC WRITECMD */
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#define _MSC_WRITECMD_RESETVALUE 0x00000000UL
158
#define _MSC_WRITECMD_MASK 0x0000113FUL
159
#define MSC_WRITECMD_LADDRIM (0x1UL << 0)
160
#define _MSC_WRITECMD_LADDRIM_SHIFT 0
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#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
162
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
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#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
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#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
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#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
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#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
168
#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
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#define MSC_WRITECMD_WRITEEND (0x1UL << 2)
170
#define _MSC_WRITECMD_WRITEEND_SHIFT 2
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#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
172
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
173
#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
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#define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
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#define _MSC_WRITECMD_WRITEONCE_SHIFT 3
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#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
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#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
178
#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
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#define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
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#define _MSC_WRITECMD_WRITETRIG_SHIFT 4
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#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
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#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
183
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
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#define MSC_WRITECMD_ERASEABORT (0x1UL << 5)
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#define _MSC_WRITECMD_ERASEABORT_SHIFT 5
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#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL
187
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL
188
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)
189
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8)
190
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8
191
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL
192
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL
193
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)
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#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12)
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#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12
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#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL
197
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL
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#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)
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/* Bit fields for MSC ADDRB */
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#define _MSC_ADDRB_RESETVALUE 0x00000000UL
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#define _MSC_ADDRB_MASK 0xFFFFFFFFUL
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#define _MSC_ADDRB_ADDRB_SHIFT 0
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#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
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#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
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#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
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/* Bit fields for MSC WDATA */
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#define _MSC_WDATA_RESETVALUE 0x00000000UL
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#define _MSC_WDATA_MASK 0xFFFFFFFFUL
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#define _MSC_WDATA_WDATA_SHIFT 0
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#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
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#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
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#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
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/* Bit fields for MSC STATUS */
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#define _MSC_STATUS_RESETVALUE 0x00000008UL
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#define _MSC_STATUS_MASK 0x0000007FUL
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#define MSC_STATUS_BUSY (0x1UL << 0)
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#define _MSC_STATUS_BUSY_SHIFT 0
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#define _MSC_STATUS_BUSY_MASK 0x1UL
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#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
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#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
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#define MSC_STATUS_LOCKED (0x1UL << 1)
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#define _MSC_STATUS_LOCKED_SHIFT 1
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#define _MSC_STATUS_LOCKED_MASK 0x2UL
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#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
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#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
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#define MSC_STATUS_INVADDR (0x1UL << 2)
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#define _MSC_STATUS_INVADDR_SHIFT 2
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#define _MSC_STATUS_INVADDR_MASK 0x4UL
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#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
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#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
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#define MSC_STATUS_WDATAREADY (0x1UL << 3)
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#define _MSC_STATUS_WDATAREADY_SHIFT 3
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#define _MSC_STATUS_WDATAREADY_MASK 0x8UL
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#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
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#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
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#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
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#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
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#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
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#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
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#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
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#define MSC_STATUS_ERASEABORTED (0x1UL << 5)
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#define _MSC_STATUS_ERASEABORTED_SHIFT 5
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#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
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#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
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#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
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#define MSC_STATUS_PCRUNNING (0x1UL << 6)
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#define _MSC_STATUS_PCRUNNING_SHIFT 6
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#define _MSC_STATUS_PCRUNNING_MASK 0x40UL
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#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL
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#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6)
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/* Bit fields for MSC IF */
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#define _MSC_IF_RESETVALUE 0x00000000UL
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#define _MSC_IF_MASK 0x0000000FUL
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#define MSC_IF_ERASE (0x1UL << 0)
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#define _MSC_IF_ERASE_SHIFT 0
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#define _MSC_IF_ERASE_MASK 0x1UL
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#define _MSC_IF_ERASE_DEFAULT 0x00000000UL
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#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
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#define MSC_IF_WRITE (0x1UL << 1)
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#define _MSC_IF_WRITE_SHIFT 1
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#define _MSC_IF_WRITE_MASK 0x2UL
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#define _MSC_IF_WRITE_DEFAULT 0x00000000UL
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#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
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#define MSC_IF_CHOF (0x1UL << 2)
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#define _MSC_IF_CHOF_SHIFT 2
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#define _MSC_IF_CHOF_MASK 0x4UL
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#define _MSC_IF_CHOF_DEFAULT 0x00000000UL
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#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2)
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#define MSC_IF_CMOF (0x1UL << 3)
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#define _MSC_IF_CMOF_SHIFT 3
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#define _MSC_IF_CMOF_MASK 0x8UL
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#define _MSC_IF_CMOF_DEFAULT 0x00000000UL
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#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3)
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/* Bit fields for MSC IFS */
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#define _MSC_IFS_RESETVALUE 0x00000000UL
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#define _MSC_IFS_MASK 0x0000000FUL
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#define MSC_IFS_ERASE (0x1UL << 0)
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#define _MSC_IFS_ERASE_SHIFT 0
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#define _MSC_IFS_ERASE_MASK 0x1UL
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#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
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#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
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#define MSC_IFS_WRITE (0x1UL << 1)
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#define _MSC_IFS_WRITE_SHIFT 1
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#define _MSC_IFS_WRITE_MASK 0x2UL
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#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
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#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
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#define MSC_IFS_CHOF (0x1UL << 2)
293
#define _MSC_IFS_CHOF_SHIFT 2
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#define _MSC_IFS_CHOF_MASK 0x4UL
295
#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL
296
#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2)
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#define MSC_IFS_CMOF (0x1UL << 3)
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#define _MSC_IFS_CMOF_SHIFT 3
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#define _MSC_IFS_CMOF_MASK 0x8UL
300
#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL
301
#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3)
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/* Bit fields for MSC IFC */
304
#define _MSC_IFC_RESETVALUE 0x00000000UL
305
#define _MSC_IFC_MASK 0x0000000FUL
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#define MSC_IFC_ERASE (0x1UL << 0)
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#define _MSC_IFC_ERASE_SHIFT 0
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#define _MSC_IFC_ERASE_MASK 0x1UL
309
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
310
#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
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#define MSC_IFC_WRITE (0x1UL << 1)
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#define _MSC_IFC_WRITE_SHIFT 1
313
#define _MSC_IFC_WRITE_MASK 0x2UL
314
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
315
#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
316
#define MSC_IFC_CHOF (0x1UL << 2)
317
#define _MSC_IFC_CHOF_SHIFT 2
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#define _MSC_IFC_CHOF_MASK 0x4UL
319
#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL
320
#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2)
321
#define MSC_IFC_CMOF (0x1UL << 3)
322
#define _MSC_IFC_CMOF_SHIFT 3
323
#define _MSC_IFC_CMOF_MASK 0x8UL
324
#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL
325
#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3)
327
/* Bit fields for MSC IEN */
328
#define _MSC_IEN_RESETVALUE 0x00000000UL
329
#define _MSC_IEN_MASK 0x0000000FUL
330
#define MSC_IEN_ERASE (0x1UL << 0)
331
#define _MSC_IEN_ERASE_SHIFT 0
332
#define _MSC_IEN_ERASE_MASK 0x1UL
333
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
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#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
335
#define MSC_IEN_WRITE (0x1UL << 1)
336
#define _MSC_IEN_WRITE_SHIFT 1
337
#define _MSC_IEN_WRITE_MASK 0x2UL
338
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
339
#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
340
#define MSC_IEN_CHOF (0x1UL << 2)
341
#define _MSC_IEN_CHOF_SHIFT 2
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#define _MSC_IEN_CHOF_MASK 0x4UL
343
#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL
344
#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2)
345
#define MSC_IEN_CMOF (0x1UL << 3)
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#define _MSC_IEN_CMOF_SHIFT 3
347
#define _MSC_IEN_CMOF_MASK 0x8UL
348
#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL
349
#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3)
351
/* Bit fields for MSC LOCK */
352
#define _MSC_LOCK_RESETVALUE 0x00000000UL
353
#define _MSC_LOCK_MASK 0x0000FFFFUL
354
#define _MSC_LOCK_LOCKKEY_SHIFT 0
355
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
356
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
357
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
358
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
359
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
360
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
361
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
362
#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
363
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
364
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
365
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
367
/* Bit fields for MSC CMD */
368
#define _MSC_CMD_RESETVALUE 0x00000000UL
369
#define _MSC_CMD_MASK 0x00000007UL
370
#define MSC_CMD_INVCACHE (0x1UL << 0)
371
#define _MSC_CMD_INVCACHE_SHIFT 0
372
#define _MSC_CMD_INVCACHE_MASK 0x1UL
373
#define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL
374
#define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0)
375
#define MSC_CMD_STARTPC (0x1UL << 1)
376
#define _MSC_CMD_STARTPC_SHIFT 1
377
#define _MSC_CMD_STARTPC_MASK 0x2UL
378
#define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL
379
#define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1)
380
#define MSC_CMD_STOPPC (0x1UL << 2)
381
#define _MSC_CMD_STOPPC_SHIFT 2
382
#define _MSC_CMD_STOPPC_MASK 0x4UL
383
#define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL
384
#define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2)
386
/* Bit fields for MSC CACHEHITS */
387
#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL
388
#define _MSC_CACHEHITS_MASK 0x000FFFFFUL
389
#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0
390
#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL
391
#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL
392
#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)
394
/* Bit fields for MSC CACHEMISSES */
395
#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL
396
#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL
397
#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0
398
#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL
399
#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL
400
#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)
402
/* Bit fields for MSC TIMEBASE */
403
#define _MSC_TIMEBASE_RESETVALUE 0x00000010UL
404
#define _MSC_TIMEBASE_MASK 0x0001003FUL
405
#define _MSC_TIMEBASE_BASE_SHIFT 0
406
#define _MSC_TIMEBASE_BASE_MASK 0x3FUL
407
#define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL
408
#define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0)
409
#define MSC_TIMEBASE_PERIOD (0x1UL << 16)
410
#define _MSC_TIMEBASE_PERIOD_SHIFT 16
411
#define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL
412
#define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL
413
#define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL
414
#define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL
415
#define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16)
416
#define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16)
417
#define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16)
419
/* Bit fields for MSC MASSLOCK */
420
#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL
421
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL
422
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0
423
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL
424
#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL
425
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL
426
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL
427
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL
428
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL
429
#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)
430
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)
431
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)
432
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)
433
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)
MSC_TypeDef::MASSLOCK
__IOM uint32_t MASSLOCK
Definition:
ezr32wg_msc.h:64
MSC_TypeDef::CACHEHITS
__IM uint32_t CACHEHITS
Definition:
ezr32wg_msc.h:60
MSC_TypeDef::LOCK
__IOM uint32_t LOCK
Definition:
ezr32wg_msc.h:58
MSC_TypeDef::IEN
__IOM uint32_t IEN
Definition:
ezr32wg_msc.h:57
MSC_TypeDef::STATUS
__IM uint32_t STATUS
Definition:
ezr32wg_msc.h:51
MSC_TypeDef::WDATA
__IOM uint32_t WDATA
Definition:
ezr32wg_msc.h:50
MSC_TypeDef::TIMEBASE
__IOM uint32_t TIMEBASE
Definition:
ezr32wg_msc.h:63
MSC_TypeDef::READCTRL
__IOM uint32_t READCTRL
Definition:
ezr32wg_msc.h:44
MSC_TypeDef::IFC
__IOM uint32_t IFC
Definition:
ezr32wg_msc.h:56
MSC_TypeDef::ADDRB
__IOM uint32_t ADDRB
Definition:
ezr32wg_msc.h:47
MSC_TypeDef::CACHEMISSES
__IM uint32_t CACHEMISSES
Definition:
ezr32wg_msc.h:61
MSC_TypeDef::IFS
__IOM uint32_t IFS
Definition:
ezr32wg_msc.h:55
MSC_TypeDef::WRITECTRL
__IOM uint32_t WRITECTRL
Definition:
ezr32wg_msc.h:45
MSC_TypeDef
Definition:
ezr32wg_msc.h:41
MSC_TypeDef::CMD
__IOM uint32_t CMD
Definition:
ezr32wg_msc.h:59
MSC_TypeDef::CTRL
__IOM uint32_t CTRL
Definition:
ezr32wg_msc.h:43
MSC_TypeDef::IF
__IM uint32_t IF
Definition:
ezr32wg_msc.h:54
MSC_TypeDef::WRITECMD
__IOM uint32_t WRITECMD
Definition:
ezr32wg_msc.h:46
platform
Device
SiliconLabs
EZR32WG
Include
ezr32wg_msc.h
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