ezr32wg/html/ezr32wg__rtc_8h_source.html

 /**************************************************************************/

 /**************************************************************************/

 /**************************************************************************/

 typedef struct

 {

   __IOM uint32_t CTRL;

   __IOM uint32_t CNT;

   __IOM uint32_t COMP0;

   __IOM uint32_t COMP1;

   __IM uint32_t  IF;

   __IOM uint32_t IFS;

   __IOM uint32_t IFC;

   __IOM uint32_t IEN;

   __IOM uint32_t FREEZE;

   __IM uint32_t  SYNCBUSY;

 } RTC_TypeDef;

 /**************************************************************************/

 /* Bit fields for RTC CTRL */

 #define _RTC_CTRL_RESETVALUE             0x00000000UL

 #define _RTC_CTRL_MASK                   0x00000007UL

 #define RTC_CTRL_EN                      (0x1UL << 0)

 #define _RTC_CTRL_EN_SHIFT               0

 #define _RTC_CTRL_EN_MASK                0x1UL

 #define _RTC_CTRL_EN_DEFAULT             0x00000000UL

 #define RTC_CTRL_EN_DEFAULT              (_RTC_CTRL_EN_DEFAULT << 0)

 #define RTC_CTRL_DEBUGRUN                (0x1UL << 1)

 #define _RTC_CTRL_DEBUGRUN_SHIFT         1

 #define _RTC_CTRL_DEBUGRUN_MASK          0x2UL

 #define _RTC_CTRL_DEBUGRUN_DEFAULT       0x00000000UL

 #define RTC_CTRL_DEBUGRUN_DEFAULT        (_RTC_CTRL_DEBUGRUN_DEFAULT << 1)

 #define RTC_CTRL_COMP0TOP                (0x1UL << 2)

 #define _RTC_CTRL_COMP0TOP_SHIFT         2

 #define _RTC_CTRL_COMP0TOP_MASK          0x4UL

 #define _RTC_CTRL_COMP0TOP_DEFAULT       0x00000000UL

 #define _RTC_CTRL_COMP0TOP_DISABLE       0x00000000UL

 #define _RTC_CTRL_COMP0TOP_ENABLE        0x00000001UL

 #define RTC_CTRL_COMP0TOP_DEFAULT        (_RTC_CTRL_COMP0TOP_DEFAULT << 2)

 #define RTC_CTRL_COMP0TOP_DISABLE        (_RTC_CTRL_COMP0TOP_DISABLE << 2)

 #define RTC_CTRL_COMP0TOP_ENABLE         (_RTC_CTRL_COMP0TOP_ENABLE << 2)

 /* Bit fields for RTC CNT */

 #define _RTC_CNT_RESETVALUE              0x00000000UL

 #define _RTC_CNT_MASK                    0x00FFFFFFUL

 #define _RTC_CNT_CNT_SHIFT               0

 #define _RTC_CNT_CNT_MASK                0xFFFFFFUL

 #define _RTC_CNT_CNT_DEFAULT             0x00000000UL

 #define RTC_CNT_CNT_DEFAULT              (_RTC_CNT_CNT_DEFAULT << 0)

 /* Bit fields for RTC COMP0 */

 #define _RTC_COMP0_RESETVALUE            0x00000000UL

 #define _RTC_COMP0_MASK                  0x00FFFFFFUL

 #define _RTC_COMP0_COMP0_SHIFT           0

 #define _RTC_COMP0_COMP0_MASK            0xFFFFFFUL

 #define _RTC_COMP0_COMP0_DEFAULT         0x00000000UL

 #define RTC_COMP0_COMP0_DEFAULT          (_RTC_COMP0_COMP0_DEFAULT << 0)

 /* Bit fields for RTC COMP1 */

 #define _RTC_COMP1_RESETVALUE            0x00000000UL

 #define _RTC_COMP1_MASK                  0x00FFFFFFUL

 #define _RTC_COMP1_COMP1_SHIFT           0

 #define _RTC_COMP1_COMP1_MASK            0xFFFFFFUL

 #define _RTC_COMP1_COMP1_DEFAULT         0x00000000UL

 #define RTC_COMP1_COMP1_DEFAULT          (_RTC_COMP1_COMP1_DEFAULT << 0)

 /* Bit fields for RTC IF */

 #define _RTC_IF_RESETVALUE               0x00000000UL

 #define _RTC_IF_MASK                     0x00000007UL

 #define RTC_IF_OF                        (0x1UL << 0)

 #define _RTC_IF_OF_SHIFT                 0

 #define _RTC_IF_OF_MASK                  0x1UL

 #define _RTC_IF_OF_DEFAULT               0x00000000UL

 #define RTC_IF_OF_DEFAULT                (_RTC_IF_OF_DEFAULT << 0)

 #define RTC_IF_COMP0                     (0x1UL << 1)

 #define _RTC_IF_COMP0_SHIFT              1

 #define _RTC_IF_COMP0_MASK               0x2UL

 #define _RTC_IF_COMP0_DEFAULT            0x00000000UL

 #define RTC_IF_COMP0_DEFAULT             (_RTC_IF_COMP0_DEFAULT << 1)

 #define RTC_IF_COMP1                     (0x1UL << 2)

 #define _RTC_IF_COMP1_SHIFT              2

 #define _RTC_IF_COMP1_MASK               0x4UL

 #define _RTC_IF_COMP1_DEFAULT            0x00000000UL

 #define RTC_IF_COMP1_DEFAULT             (_RTC_IF_COMP1_DEFAULT << 2)

 /* Bit fields for RTC IFS */

 #define _RTC_IFS_RESETVALUE              0x00000000UL

 #define _RTC_IFS_MASK                    0x00000007UL

 #define RTC_IFS_OF                       (0x1UL << 0)

 #define _RTC_IFS_OF_SHIFT                0

 #define _RTC_IFS_OF_MASK                 0x1UL

 #define _RTC_IFS_OF_DEFAULT              0x00000000UL

 #define RTC_IFS_OF_DEFAULT               (_RTC_IFS_OF_DEFAULT << 0)

 #define RTC_IFS_COMP0                    (0x1UL << 1)

 #define _RTC_IFS_COMP0_SHIFT             1

 #define _RTC_IFS_COMP0_MASK              0x2UL

 #define _RTC_IFS_COMP0_DEFAULT           0x00000000UL

 #define RTC_IFS_COMP0_DEFAULT            (_RTC_IFS_COMP0_DEFAULT << 1)

 #define RTC_IFS_COMP1                    (0x1UL << 2)

 #define _RTC_IFS_COMP1_SHIFT             2

 #define _RTC_IFS_COMP1_MASK              0x4UL

 #define _RTC_IFS_COMP1_DEFAULT           0x00000000UL

 #define RTC_IFS_COMP1_DEFAULT            (_RTC_IFS_COMP1_DEFAULT << 2)

 /* Bit fields for RTC IFC */

 #define _RTC_IFC_RESETVALUE              0x00000000UL

 #define _RTC_IFC_MASK                    0x00000007UL

 #define RTC_IFC_OF                       (0x1UL << 0)

 #define _RTC_IFC_OF_SHIFT                0

 #define _RTC_IFC_OF_MASK                 0x1UL

 #define _RTC_IFC_OF_DEFAULT              0x00000000UL

 #define RTC_IFC_OF_DEFAULT               (_RTC_IFC_OF_DEFAULT << 0)

 #define RTC_IFC_COMP0                    (0x1UL << 1)

 #define _RTC_IFC_COMP0_SHIFT             1

 #define _RTC_IFC_COMP0_MASK              0x2UL

 #define _RTC_IFC_COMP0_DEFAULT           0x00000000UL

 #define RTC_IFC_COMP0_DEFAULT            (_RTC_IFC_COMP0_DEFAULT << 1)

 #define RTC_IFC_COMP1                    (0x1UL << 2)

 #define _RTC_IFC_COMP1_SHIFT             2

 #define _RTC_IFC_COMP1_MASK              0x4UL

 #define _RTC_IFC_COMP1_DEFAULT           0x00000000UL

 #define RTC_IFC_COMP1_DEFAULT            (_RTC_IFC_COMP1_DEFAULT << 2)

 /* Bit fields for RTC IEN */

 #define _RTC_IEN_RESETVALUE              0x00000000UL

 #define _RTC_IEN_MASK                    0x00000007UL

 #define RTC_IEN_OF                       (0x1UL << 0)

 #define _RTC_IEN_OF_SHIFT                0

 #define _RTC_IEN_OF_MASK                 0x1UL

 #define _RTC_IEN_OF_DEFAULT              0x00000000UL

 #define RTC_IEN_OF_DEFAULT               (_RTC_IEN_OF_DEFAULT << 0)

 #define RTC_IEN_COMP0                    (0x1UL << 1)

 #define _RTC_IEN_COMP0_SHIFT             1

 #define _RTC_IEN_COMP0_MASK              0x2UL

 #define _RTC_IEN_COMP0_DEFAULT           0x00000000UL

 #define RTC_IEN_COMP0_DEFAULT            (_RTC_IEN_COMP0_DEFAULT << 1)

 #define RTC_IEN_COMP1                    (0x1UL << 2)

 #define _RTC_IEN_COMP1_SHIFT             2

 #define _RTC_IEN_COMP1_MASK              0x4UL

 #define _RTC_IEN_COMP1_DEFAULT           0x00000000UL

 #define RTC_IEN_COMP1_DEFAULT            (_RTC_IEN_COMP1_DEFAULT << 2)

 /* Bit fields for RTC FREEZE */

 #define _RTC_FREEZE_RESETVALUE           0x00000000UL

 #define _RTC_FREEZE_MASK                 0x00000001UL

 #define RTC_FREEZE_REGFREEZE             (0x1UL << 0)

 #define _RTC_FREEZE_REGFREEZE_SHIFT      0

 #define _RTC_FREEZE_REGFREEZE_MASK       0x1UL

 #define _RTC_FREEZE_REGFREEZE_DEFAULT    0x00000000UL

 #define _RTC_FREEZE_REGFREEZE_UPDATE     0x00000000UL

 #define _RTC_FREEZE_REGFREEZE_FREEZE     0x00000001UL

 #define RTC_FREEZE_REGFREEZE_DEFAULT     (_RTC_FREEZE_REGFREEZE_DEFAULT << 0)

 #define RTC_FREEZE_REGFREEZE_UPDATE      (_RTC_FREEZE_REGFREEZE_UPDATE << 0)

 #define RTC_FREEZE_REGFREEZE_FREEZE      (_RTC_FREEZE_REGFREEZE_FREEZE << 0)

 /* Bit fields for RTC SYNCBUSY */

 #define _RTC_SYNCBUSY_RESETVALUE         0x00000000UL

 #define _RTC_SYNCBUSY_MASK               0x00000007UL

 #define RTC_SYNCBUSY_CTRL                (0x1UL << 0)

 #define _RTC_SYNCBUSY_CTRL_SHIFT         0

 #define _RTC_SYNCBUSY_CTRL_MASK          0x1UL

 #define _RTC_SYNCBUSY_CTRL_DEFAULT       0x00000000UL

 #define RTC_SYNCBUSY_CTRL_DEFAULT        (_RTC_SYNCBUSY_CTRL_DEFAULT << 0)

 #define RTC_SYNCBUSY_COMP0               (0x1UL << 1)

 #define _RTC_SYNCBUSY_COMP0_SHIFT        1

 #define _RTC_SYNCBUSY_COMP0_MASK         0x2UL

 #define _RTC_SYNCBUSY_COMP0_DEFAULT      0x00000000UL

 #define RTC_SYNCBUSY_COMP0_DEFAULT       (_RTC_SYNCBUSY_COMP0_DEFAULT << 1)

 #define RTC_SYNCBUSY_COMP1               (0x1UL << 2)

 #define _RTC_SYNCBUSY_COMP1_SHIFT        2

 #define _RTC_SYNCBUSY_COMP1_MASK         0x4UL

 #define _RTC_SYNCBUSY_COMP1_DEFAULT      0x00000000UL

 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2)

RTC_TypeDef::IFC
__IOM uint32_t IFC
Definition: ezr32wg_rtc.h:49

RTC_TypeDef::IF
__IM uint32_t IF
Definition: ezr32wg_rtc.h:47

RTC_TypeDef::SYNCBUSY
__IM uint32_t SYNCBUSY
Definition: ezr32wg_rtc.h:53

RTC_TypeDef
Definition: ezr32wg_rtc.h:41

RTC_TypeDef::CTRL
__IOM uint32_t CTRL
Definition: ezr32wg_rtc.h:43

RTC_TypeDef::COMP0
__IOM uint32_t COMP0
Definition: ezr32wg_rtc.h:45

RTC_TypeDef::IEN
__IOM uint32_t IEN
Definition: ezr32wg_rtc.h:50

RTC_TypeDef::IFS
__IOM uint32_t IFS
Definition: ezr32wg_rtc.h:48

RTC_TypeDef::FREEZE
__IOM uint32_t FREEZE
Definition: ezr32wg_rtc.h:52

RTC_TypeDef::COMP1
__IOM uint32_t COMP1
Definition: ezr32wg_rtc.h:46

RTC_TypeDef::CNT
__IOM uint32_t CNT
Definition: ezr32wg_rtc.h:44