EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
em_rmu.c
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1 /***************************************************************************/
34 #include "em_rmu.h"
35 #if defined(RMU_COUNT) && (RMU_COUNT > 0)
36 
37 #include "em_common.h"
38 #include "em_emu.h"
39 #include "em_bus.h"
40 
41 /***************************************************************************/
46 /***************************************************************************/
57 /*******************************************************************************
58  ***************************** DEFINES *********************************
59  ******************************************************************************/
60 
63 /* Reset cause zero and "don't care" bit definitions (XMASKs).
64  A XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK
65  is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask
66  in @ref RMU_ResetCauseMasks_Typedef. */
67 
68 /* EFM32G */
69 #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL)
70 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
71 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL
72 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL
73 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL
74 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL
75 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL
76 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL
77 #define NUM_RSTCAUSES 7
78 
79 /* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */
80 #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL)
81 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
82 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL
83 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL
84 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL
85 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL
86 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL
87 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL
88 #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL
89 #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL
90 #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL
91 #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL
92 #define NUM_RSTCAUSES 11
93 
94 /* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */
95 #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL)
96 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
97 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL
98 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL
99 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL
100 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL
101 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL
102 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL
103 #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL
104 #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL
105 #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL
106 #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL
107 #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL
108 #define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL
109 #define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL
110 #define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL
111 #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL
112 #define NUM_RSTCAUSES 16
113 
114 /* EFM32xG1, EFM32xG12, EFM32xG13 */
115 #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL)
116 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
117 #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL
118 #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL
119 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL
120 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL
121 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL
122 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL
123 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL
124 #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL
125 #define NUM_RSTCAUSES 9
126 
127 #else
128 #error "RMU_RSTCAUSE XMASKs are not defined for this family."
129 #endif
130 
131 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
132 /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */
133 #define ERRATA_FIX_EMU_E208_EN
134 #endif
135 
136 /*******************************************************************************
137  ******************************* STRUCTS ***********************************
138  ******************************************************************************/
139 
141 typedef struct
142 {
144  uint32_t resetCauseMask;
146  uint32_t resetCauseZeroXMask;
147 } RMU_ResetCauseMasks_Typedef;
148 
149 
150 /*******************************************************************************
151  ******************************* TYPEDEFS **********************************
152  ******************************************************************************/
153 
155 static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =
156  {
157  { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
158 #if defined(RMU_RSTCAUSE_BODUNREGRST)
159  { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
160 #endif
161 #if defined(RMU_RSTCAUSE_BODREGRST)
162  { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
163 #endif
164 #if defined(RMU_RSTCAUSE_AVDDBOD)
165  { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
166 #endif
167 #if defined(RMU_RSTCAUSE_DVDDBOD)
168  { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
169 #endif
170 #if defined(RMU_RSTCAUSE_DECBOD)
171  { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
172 #endif
173  { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
174  { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
175  { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
176  { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
177 #if defined(RMU_RSTCAUSE_EM4RST)
178  { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
179 #endif
180 #if defined(RMU_RSTCAUSE_EM4WURST)
181  { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
182 #endif
183 #if defined(RMU_RSTCAUSE_BODAVDD0)
184  { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
185 #endif
186 #if defined(RMU_RSTCAUSE_BODAVDD1)
187  { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
188 #endif
189 #if defined(BU_PRESENT)
190  { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
191  { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
192  { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
193  { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
194  { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
195 #endif
196  };
197 
198 
199 /*******************************************************************************
200  ******************************** TEST ********************************
201  ******************************************************************************/
202 #if defined(EMLIB_REGRESSION_TEST)
203 /* Test variable that replaces the RSTCAUSE cause register when testing
204  the RMU_ResetCauseGet function. */
205 extern uint32_t rstCause;
206 #endif
207 
210 /*******************************************************************************
211  ************************** GLOBAL FUNCTIONS *******************************
212  ******************************************************************************/
213 
214 /***************************************************************************/
222 void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
223 {
224  /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */
225 #if defined(_RMU_CTRL_PINRMODE_MASK)
226  uint32_t val;
227 #endif
228  uint32_t shift;
229 
230  shift = SL_CTZ((uint32_t)reset);
231 #if defined(_RMU_CTRL_PINRMODE_MASK)
232  val = (uint32_t)mode << shift;
233  RMU->CTRL = (RMU->CTRL & ~reset) | val;
234 #else
235  BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0);
236 #endif
237 }
238 
239 
240 /***************************************************************************/
249 void RMU_ResetCauseClear(void)
250 {
251  RMU->CMD = RMU_CMD_RCCLR;
252 
253 #if defined(EMU_AUXCTRL_HRCCLR)
254  {
255  uint32_t locked;
256 
257  /* Clear some reset causes not cleared with RMU CMD register */
258  /* (If EMU registers locked, they must be unlocked first) */
259  locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
260  if (locked)
261  {
262  EMU_Unlock();
263  }
264 
265  BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);
266  BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);
267 
268  if (locked)
269  {
270  EMU_Lock();
271  }
272  }
273 #endif
274 }
275 
276 
277 /***************************************************************************/
291 uint32_t RMU_ResetCauseGet(void)
292 {
293 #define LB_CLW0 (* ((volatile uint32_t *)(LOCKBITS_BASE) + 122))
294 #define LB_CLW0_PINRESETSOFT (1 << 2)
295 
296 #if !defined(EMLIB_REGRESSION_TEST)
297  uint32_t rstCause = RMU->RSTCAUSE;
298 #endif
299  uint32_t validRstCause = 0;
300  uint32_t zeroXMask;
301  uint32_t i;
302 
303  for (i = 0; i < NUM_RSTCAUSES; i++)
304  {
305  zeroXMask = resetCauseMasks[i].resetCauseZeroXMask;
306 #if defined( _SILICON_LABS_32B_SERIES_1 )
307  /* Handle soft/hard pin reset */
308  if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT))
309  {
310  /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset */
311  switch (resetCauseMasks[i].resetCauseMask)
312  {
313  case RMU_RSTCAUSE_LOCKUPRST:
314  /* Fallthrough */
315  case RMU_RSTCAUSE_SYSREQRST:
316  /* Fallthrough */
317  case RMU_RSTCAUSE_WDOGRST:
318  /* Fallthrough */
319  case RMU_RSTCAUSE_EM4RST:
320  zeroXMask |= RMU_RSTCAUSE_EXTRST;
321  break;
322  }
323  }
324 #endif
325 
326 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
327  /* Ignore BOD flags impacted by EMU_E208 */
328  if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8))
329  {
330  zeroXMask &= ~(RMU_RSTCAUSE_DECBOD
331  | RMU_RSTCAUSE_DVDDBOD
332  | RMU_RSTCAUSE_AVDDBOD);
333  }
334 #endif
335 
336  /* Check reset cause requirements. Note that a bit is "don't care" if 0 in
337  both resetCauseMask and resetCauseZeroXMask. */
338  if ((rstCause & resetCauseMasks[i].resetCauseMask)
339  && !(rstCause & zeroXMask))
340  {
341  /* Add this reset-cause to the mask of qualified reset-causes */
342  validRstCause |= resetCauseMasks[i].resetCauseMask;
343  }
344  }
345 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
346  /* Clear BOD flags impacted by EMU_E208 */
347  if (validRstCause & RMU_RSTCAUSE_EM4RST)
348  {
349  validRstCause &= ~(RMU_RSTCAUSE_DECBOD
350  | RMU_RSTCAUSE_DVDDBOD
351  | RMU_RSTCAUSE_AVDDBOD);
352  }
353 #endif
354  return validRstCause;
355 }
356 
357 
360 #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */
RMU_ResetCauseGet
uint32_t RMU_ResetCauseGet(void)
Get the cause of the last reset.
Definition: em_rmu.c:291
RMU_Reset_TypeDef
RMU_Reset_TypeDef
Definition: em_rmu.h:75
RMU_RSTCAUSE_PORST
#define RMU_RSTCAUSE_PORST
Definition: efr32mg1p_rmu.h:114
em_bus.h
RAM and peripheral bit-field set and clear API.
RMU_RSTCAUSE_AVDDBOD
#define RMU_RSTCAUSE_AVDDBOD
Definition: efr32mg1p_rmu.h:119
RMU_RSTCAUSE_EXTRST
#define RMU_RSTCAUSE_EXTRST
Definition: efr32mg1p_rmu.h:134
EMU_LOCK_LOCKKEY_LOCKED
#define EMU_LOCK_LOCKKEY_LOCKED
Definition: efr32mg1p_emu.h:164
em_common.h
General purpose utilities.
EMU_Unlock
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
Definition: em_emu.h:926
EMU_Lock
__STATIC_INLINE void EMU_Lock(void)
Lock the EMU in order to protect its registers against unintended modification.
Definition: em_emu.h:916
EMU_BASE
#define EMU_BASE
Definition: efr32mg1p233f256gm48.h:297
RMU_RSTCAUSE_DVDDBOD
#define RMU_RSTCAUSE_DVDDBOD
Definition: efr32mg1p_rmu.h:124
RMU_ResetControl
void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
Disable/enable reset for various peripherals and signal sources.
Definition: em_rmu.c:222
RMU_ResetMode_TypeDef
RMU_ResetMode_TypeDef
Definition: em_rmu.h:61
RMU_RSTCAUSE_EM4RST
#define RMU_RSTCAUSE_EM4RST
Definition: efr32mg1p_rmu.h:154
RMU_RSTCAUSE_DECBOD
#define RMU_RSTCAUSE_DECBOD
Definition: efr32mg1p_rmu.h:129
RMU_RSTCAUSE_SYSREQRST
#define RMU_RSTCAUSE_SYSREQRST
Definition: efr32mg1p_rmu.h:144
EMU
#define EMU
Definition: efr32mg1p233f256gm48.h:334
em_rmu.h
Reset Management Unit (RMU) peripheral API.
em_emu.h
Energy management unit (EMU) peripheral API.
SL_CTZ
__STATIC_INLINE uint32_t SL_CTZ(uint32_t value)
Count trailing number of zeros. Use CLZ instruction if available.
Definition: em_common.h:194
RMU_RSTCAUSE_WDOGRST
#define RMU_RSTCAUSE_WDOGRST
Definition: efr32mg1p_rmu.h:149
BUS_RegBitWrite
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
RMU
#define RMU
Definition: efr32mg1p233f256gm48.h:335
RMU_ResetCauseClear
void RMU_ResetCauseClear(void)
Clear the reset cause register.
Definition: em_rmu.c:249
RMU_CMD_RCCLR
#define RMU_CMD_RCCLR
Definition: efr32mg1p_rmu.h:163
RMU_RSTCAUSE_LOCKUPRST
#define RMU_RSTCAUSE_LOCKUPRST
Definition: efr32mg1p_rmu.h:139