EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
efr32mg1p_emu.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IM uint32_t STATUS;
45  __IOM uint32_t LOCK;
46  __IOM uint32_t RAM0CTRL;
47  __IOM uint32_t CMD;
49  uint32_t RESERVED0[1];
50  __IOM uint32_t EM4CTRL;
51  __IOM uint32_t TEMPLIMITS;
52  __IM uint32_t TEMP;
53  __IM uint32_t IF;
54  __IOM uint32_t IFS;
55  __IOM uint32_t IFC;
56  __IOM uint32_t IEN;
57  __IOM uint32_t PWRLOCK;
58  __IOM uint32_t PWRCFG;
59  __IOM uint32_t PWRCTRL;
60  __IOM uint32_t DCDCCTRL;
62  uint32_t RESERVED1[2];
63  __IOM uint32_t DCDCMISCCTRL;
64  __IOM uint32_t DCDCZDETCTRL;
65  __IOM uint32_t DCDCCLIMCTRL;
66  __IOM uint32_t DCDCLNCOMPCTRL;
67  __IOM uint32_t DCDCLNVCTRL;
68  __IOM uint32_t DCDCTIMING;
69  __IOM uint32_t DCDCLPVCTRL;
71  uint32_t RESERVED2[1];
72  __IOM uint32_t DCDCLPCTRL;
73  __IOM uint32_t DCDCLNFREQCTRL;
75  uint32_t RESERVED3[1];
76  __IM uint32_t DCDCSYNC;
78  uint32_t RESERVED4[5];
79  __IOM uint32_t VMONAVDDCTRL;
80  __IOM uint32_t VMONALTAVDDCTRL;
81  __IOM uint32_t VMONDVDDCTRL;
82  __IOM uint32_t VMONIO0CTRL;
84  uint32_t RESERVED5[49];
85  __IOM uint32_t BIASCONF;
87  uint32_t RESERVED6[10];
88  __IOM uint32_t TESTLOCK;
90  uint32_t RESERVED7[2];
91  __IOM uint32_t BIASTESTCTRL;
92 } EMU_TypeDef;
94 /**************************************************************************/
99 /* Bit fields for EMU CTRL */
100 #define _EMU_CTRL_RESETVALUE 0x00000000UL
101 #define _EMU_CTRL_MASK 0x00000002UL
102 #define EMU_CTRL_EM2BLOCK (0x1UL << 1)
103 #define _EMU_CTRL_EM2BLOCK_SHIFT 1
104 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL
105 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL
106 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
108 /* Bit fields for EMU STATUS */
109 #define _EMU_STATUS_RESETVALUE 0x00000000UL
110 #define _EMU_STATUS_MASK 0x0010011FUL
111 #define EMU_STATUS_VMONRDY (0x1UL << 0)
112 #define _EMU_STATUS_VMONRDY_SHIFT 0
113 #define _EMU_STATUS_VMONRDY_MASK 0x1UL
114 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL
115 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0)
116 #define EMU_STATUS_VMONAVDD (0x1UL << 1)
117 #define _EMU_STATUS_VMONAVDD_SHIFT 1
118 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL
119 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL
120 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1)
121 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2)
122 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2
123 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL
124 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL
125 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2)
126 #define EMU_STATUS_VMONDVDD (0x1UL << 3)
127 #define _EMU_STATUS_VMONDVDD_SHIFT 3
128 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL
129 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL
130 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3)
131 #define EMU_STATUS_VMONIO0 (0x1UL << 4)
132 #define _EMU_STATUS_VMONIO0_SHIFT 4
133 #define _EMU_STATUS_VMONIO0_MASK 0x10UL
134 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL
135 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4)
136 #define EMU_STATUS_VMONFVDD (0x1UL << 8)
137 #define _EMU_STATUS_VMONFVDD_SHIFT 8
138 #define _EMU_STATUS_VMONFVDD_MASK 0x100UL
139 #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL
140 #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8)
141 #define EMU_STATUS_EM4IORET (0x1UL << 20)
142 #define _EMU_STATUS_EM4IORET_SHIFT 20
143 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL
144 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL
145 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL
146 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL
147 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20)
148 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20)
149 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20)
151 /* Bit fields for EMU LOCK */
152 #define _EMU_LOCK_RESETVALUE 0x00000000UL
153 #define _EMU_LOCK_MASK 0x0000FFFFUL
154 #define _EMU_LOCK_LOCKKEY_SHIFT 0
155 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL
156 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
157 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL
158 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
159 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
160 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
161 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
162 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0)
163 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
164 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0)
165 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
167 /* Bit fields for EMU RAM0CTRL */
168 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL
169 #define _EMU_RAM0CTRL_MASK 0x0000000FUL
170 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0
171 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL
172 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL
173 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL
174 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL
175 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL
176 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL
177 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL
178 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0)
179 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)
180 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0)
181 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0)
182 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0)
183 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0)
185 /* Bit fields for EMU CMD */
186 #define _EMU_CMD_RESETVALUE 0x00000000UL
187 #define _EMU_CMD_MASK 0x00000001UL
188 #define EMU_CMD_EM4UNLATCH (0x1UL << 0)
189 #define _EMU_CMD_EM4UNLATCH_SHIFT 0
190 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL
191 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL
192 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)
194 /* Bit fields for EMU EM4CTRL */
195 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL
196 #define _EMU_EM4CTRL_MASK 0x0003003FUL
197 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0)
198 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0
199 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL
200 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL
201 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL
202 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL
203 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)
204 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0)
205 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0)
206 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1)
207 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1
208 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL
209 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL
210 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)
211 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2)
212 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2
213 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL
214 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL
215 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)
216 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3)
217 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3
218 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL
219 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL
220 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)
221 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4
222 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL
223 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL
224 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL
225 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL
226 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL
227 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)
228 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)
229 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)
230 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)
231 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16
232 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL
233 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL
234 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)
236 /* Bit fields for EMU TEMPLIMITS */
237 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL
238 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL
239 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0
240 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL
241 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL
242 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)
243 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8
244 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL
245 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL
246 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8)
247 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16)
248 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16
249 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL
250 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL
251 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16)
253 /* Bit fields for EMU TEMP */
254 #define _EMU_TEMP_RESETVALUE 0x00000000UL
255 #define _EMU_TEMP_MASK 0x000000FFUL
256 #define _EMU_TEMP_TEMP_SHIFT 0
257 #define _EMU_TEMP_TEMP_MASK 0xFFUL
258 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL
259 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0)
261 /* Bit fields for EMU IF */
262 #define _EMU_IF_RESETVALUE 0x00000000UL
263 #define _EMU_IF_MASK 0xE11FC0FFUL
264 #define EMU_IF_VMONAVDDFALL (0x1UL << 0)
265 #define _EMU_IF_VMONAVDDFALL_SHIFT 0
266 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL
267 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL
268 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)
269 #define EMU_IF_VMONAVDDRISE (0x1UL << 1)
270 #define _EMU_IF_VMONAVDDRISE_SHIFT 1
271 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL
272 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL
273 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)
274 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2)
275 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2
276 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL
277 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL
278 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)
279 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3)
280 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3
281 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL
282 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL
283 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)
284 #define EMU_IF_VMONDVDDFALL (0x1UL << 4)
285 #define _EMU_IF_VMONDVDDFALL_SHIFT 4
286 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL
287 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL
288 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)
289 #define EMU_IF_VMONDVDDRISE (0x1UL << 5)
290 #define _EMU_IF_VMONDVDDRISE_SHIFT 5
291 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL
292 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL
293 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)
294 #define EMU_IF_VMONIO0FALL (0x1UL << 6)
295 #define _EMU_IF_VMONIO0FALL_SHIFT 6
296 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL
297 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL
298 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6)
299 #define EMU_IF_VMONIO0RISE (0x1UL << 7)
300 #define _EMU_IF_VMONIO0RISE_SHIFT 7
301 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL
302 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL
303 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7)
304 #define EMU_IF_VMONFVDDFALL (0x1UL << 14)
305 #define _EMU_IF_VMONFVDDFALL_SHIFT 14
306 #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL
307 #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL
308 #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14)
309 #define EMU_IF_VMONFVDDRISE (0x1UL << 15)
310 #define _EMU_IF_VMONFVDDRISE_SHIFT 15
311 #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL
312 #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL
313 #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15)
314 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16)
315 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16
316 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL
317 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
318 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)
319 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17)
320 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17
321 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL
322 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
323 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)
324 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18)
325 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18
326 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL
327 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL
328 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)
329 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19)
330 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19
331 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL
332 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL
333 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)
334 #define EMU_IF_DCDCINBYPASS (0x1UL << 20)
335 #define _EMU_IF_DCDCINBYPASS_SHIFT 20
336 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL
337 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL
338 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)
339 #define EMU_IF_EM23WAKEUP (0x1UL << 24)
340 #define _EMU_IF_EM23WAKEUP_SHIFT 24
341 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL
342 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL
343 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24)
344 #define EMU_IF_TEMP (0x1UL << 29)
345 #define _EMU_IF_TEMP_SHIFT 29
346 #define _EMU_IF_TEMP_MASK 0x20000000UL
347 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL
348 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29)
349 #define EMU_IF_TEMPLOW (0x1UL << 30)
350 #define _EMU_IF_TEMPLOW_SHIFT 30
351 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL
352 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL
353 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30)
354 #define EMU_IF_TEMPHIGH (0x1UL << 31)
355 #define _EMU_IF_TEMPHIGH_SHIFT 31
356 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL
357 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL
358 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31)
360 /* Bit fields for EMU IFS */
361 #define _EMU_IFS_RESETVALUE 0x00000000UL
362 #define _EMU_IFS_MASK 0xE11FC0FFUL
363 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0)
364 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0
365 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL
366 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL
367 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)
368 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1)
369 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1
370 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL
371 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL
372 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)
373 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2)
374 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2
375 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL
376 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL
377 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)
378 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3)
379 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3
380 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL
381 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL
382 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)
383 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4)
384 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4
385 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL
386 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL
387 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)
388 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5)
389 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5
390 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL
391 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL
392 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)
393 #define EMU_IFS_VMONIO0FALL (0x1UL << 6)
394 #define _EMU_IFS_VMONIO0FALL_SHIFT 6
395 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL
396 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL
397 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)
398 #define EMU_IFS_VMONIO0RISE (0x1UL << 7)
399 #define _EMU_IFS_VMONIO0RISE_SHIFT 7
400 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL
401 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL
402 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)
403 #define EMU_IFS_VMONFVDDFALL (0x1UL << 14)
404 #define _EMU_IFS_VMONFVDDFALL_SHIFT 14
405 #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL
406 #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL
407 #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14)
408 #define EMU_IFS_VMONFVDDRISE (0x1UL << 15)
409 #define _EMU_IFS_VMONFVDDRISE_SHIFT 15
410 #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL
411 #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL
412 #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15)
413 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16)
414 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16
415 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL
416 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
417 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)
418 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17)
419 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17
420 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL
421 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
422 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)
423 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18)
424 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18
425 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL
426 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL
427 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)
428 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19)
429 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19
430 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL
431 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL
432 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)
433 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20)
434 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20
435 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL
436 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL
437 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)
438 #define EMU_IFS_EM23WAKEUP (0x1UL << 24)
439 #define _EMU_IFS_EM23WAKEUP_SHIFT 24
440 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL
441 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL
442 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)
443 #define EMU_IFS_TEMP (0x1UL << 29)
444 #define _EMU_IFS_TEMP_SHIFT 29
445 #define _EMU_IFS_TEMP_MASK 0x20000000UL
446 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL
447 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29)
448 #define EMU_IFS_TEMPLOW (0x1UL << 30)
449 #define _EMU_IFS_TEMPLOW_SHIFT 30
450 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL
451 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL
452 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30)
453 #define EMU_IFS_TEMPHIGH (0x1UL << 31)
454 #define _EMU_IFS_TEMPHIGH_SHIFT 31
455 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL
456 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL
457 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31)
459 /* Bit fields for EMU IFC */
460 #define _EMU_IFC_RESETVALUE 0x00000000UL
461 #define _EMU_IFC_MASK 0xE11FC0FFUL
462 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0)
463 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0
464 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL
465 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL
466 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)
467 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1)
468 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1
469 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL
470 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL
471 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)
472 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2)
473 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2
474 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL
475 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL
476 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)
477 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3)
478 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3
479 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL
480 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL
481 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)
482 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4)
483 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4
484 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL
485 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL
486 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)
487 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5)
488 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5
489 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL
490 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL
491 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)
492 #define EMU_IFC_VMONIO0FALL (0x1UL << 6)
493 #define _EMU_IFC_VMONIO0FALL_SHIFT 6
494 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL
495 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL
496 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)
497 #define EMU_IFC_VMONIO0RISE (0x1UL << 7)
498 #define _EMU_IFC_VMONIO0RISE_SHIFT 7
499 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL
500 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL
501 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)
502 #define EMU_IFC_VMONFVDDFALL (0x1UL << 14)
503 #define _EMU_IFC_VMONFVDDFALL_SHIFT 14
504 #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL
505 #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL
506 #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14)
507 #define EMU_IFC_VMONFVDDRISE (0x1UL << 15)
508 #define _EMU_IFC_VMONFVDDRISE_SHIFT 15
509 #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL
510 #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL
511 #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15)
512 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16)
513 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16
514 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL
515 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
516 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)
517 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17)
518 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17
519 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL
520 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
521 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)
522 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18)
523 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18
524 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL
525 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL
526 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)
527 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19)
528 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19
529 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL
530 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL
531 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)
532 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20)
533 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20
534 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL
535 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL
536 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)
537 #define EMU_IFC_EM23WAKEUP (0x1UL << 24)
538 #define _EMU_IFC_EM23WAKEUP_SHIFT 24
539 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL
540 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL
541 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)
542 #define EMU_IFC_TEMP (0x1UL << 29)
543 #define _EMU_IFC_TEMP_SHIFT 29
544 #define _EMU_IFC_TEMP_MASK 0x20000000UL
545 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL
546 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29)
547 #define EMU_IFC_TEMPLOW (0x1UL << 30)
548 #define _EMU_IFC_TEMPLOW_SHIFT 30
549 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL
550 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL
551 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30)
552 #define EMU_IFC_TEMPHIGH (0x1UL << 31)
553 #define _EMU_IFC_TEMPHIGH_SHIFT 31
554 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL
555 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL
556 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31)
558 /* Bit fields for EMU IEN */
559 #define _EMU_IEN_RESETVALUE 0x00000000UL
560 #define _EMU_IEN_MASK 0xE11FC0FFUL
561 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0)
562 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0
563 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL
564 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL
565 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)
566 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1)
567 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1
568 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL
569 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL
570 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)
571 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2)
572 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2
573 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL
574 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL
575 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)
576 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3)
577 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3
578 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL
579 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL
580 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)
581 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4)
582 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4
583 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL
584 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL
585 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)
586 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5)
587 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5
588 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL
589 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL
590 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)
591 #define EMU_IEN_VMONIO0FALL (0x1UL << 6)
592 #define _EMU_IEN_VMONIO0FALL_SHIFT 6
593 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL
594 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL
595 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)
596 #define EMU_IEN_VMONIO0RISE (0x1UL << 7)
597 #define _EMU_IEN_VMONIO0RISE_SHIFT 7
598 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL
599 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL
600 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)
601 #define EMU_IEN_VMONFVDDFALL (0x1UL << 14)
602 #define _EMU_IEN_VMONFVDDFALL_SHIFT 14
603 #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL
604 #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL
605 #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14)
606 #define EMU_IEN_VMONFVDDRISE (0x1UL << 15)
607 #define _EMU_IEN_VMONFVDDRISE_SHIFT 15
608 #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL
609 #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL
610 #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15)
611 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16)
612 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16
613 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL
614 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
615 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)
616 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17)
617 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17
618 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL
619 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
620 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)
621 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18)
622 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18
623 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL
624 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL
625 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)
626 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19)
627 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19
628 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL
629 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL
630 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)
631 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20)
632 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20
633 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL
634 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL
635 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)
636 #define EMU_IEN_EM23WAKEUP (0x1UL << 24)
637 #define _EMU_IEN_EM23WAKEUP_SHIFT 24
638 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL
639 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL
640 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)
641 #define EMU_IEN_TEMP (0x1UL << 29)
642 #define _EMU_IEN_TEMP_SHIFT 29
643 #define _EMU_IEN_TEMP_MASK 0x20000000UL
644 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL
645 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29)
646 #define EMU_IEN_TEMPLOW (0x1UL << 30)
647 #define _EMU_IEN_TEMPLOW_SHIFT 30
648 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL
649 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL
650 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30)
651 #define EMU_IEN_TEMPHIGH (0x1UL << 31)
652 #define _EMU_IEN_TEMPHIGH_SHIFT 31
653 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL
654 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL
655 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31)
657 /* Bit fields for EMU PWRLOCK */
658 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL
659 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL
660 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0
661 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL
662 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL
663 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL
664 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL
665 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL
666 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
667 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)
668 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)
669 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0)
670 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)
671 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)
673 /* Bit fields for EMU PWRCFG */
674 #define _EMU_PWRCFG_RESETVALUE 0x00000000UL
675 #define _EMU_PWRCFG_MASK 0x0000000FUL
676 #define _EMU_PWRCFG_PWRCFG_SHIFT 0
677 #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL
678 #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL
679 #define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL
680 #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL
681 #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0)
682 #define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0)
683 #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0)
685 /* Bit fields for EMU PWRCTRL */
686 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL
687 #define _EMU_PWRCTRL_MASK 0x00000020UL
688 #define EMU_PWRCTRL_ANASW (0x1UL << 5)
689 #define _EMU_PWRCTRL_ANASW_SHIFT 5
690 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL
691 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL
692 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL
693 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL
694 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5)
695 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5)
696 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5)
698 /* Bit fields for EMU DCDCCTRL */
699 #define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL
700 #define _EMU_DCDCCTRL_MASK 0x00000033UL
701 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0
702 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL
703 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL
704 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL
705 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL
706 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL
707 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL
708 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)
709 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)
710 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)
711 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)
712 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)
713 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4)
714 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4
715 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL
716 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL
717 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL
718 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL
719 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)
720 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)
721 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)
722 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5)
723 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5
724 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL
725 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL
726 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL
727 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL
728 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)
729 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)
730 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)
732 /* Bit fields for EMU DCDCMISCCTRL */
733 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL
734 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL
735 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0)
736 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0
737 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL
738 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL
739 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)
740 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8
741 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL
742 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL
743 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)
744 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12
745 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL
746 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL
747 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)
748 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16
749 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL
750 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL
751 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)
752 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20
753 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL
754 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL
755 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)
756 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24
757 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL
758 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL
759 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)
760 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28
761 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL
762 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL
763 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL
764 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL
765 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL
766 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL
767 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28)
768 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28)
769 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28)
770 #define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28)
771 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28)
773 /* Bit fields for EMU DCDCZDETCTRL */
774 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL
775 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL
776 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4
777 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL
778 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL
779 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)
780 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8
781 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL
782 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL
783 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)
785 /* Bit fields for EMU DCDCCLIMCTRL */
786 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL
787 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL
788 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8
789 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL
790 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL
791 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)
792 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13)
793 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13
794 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL
795 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL
796 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)
798 /* Bit fields for EMU DCDCLNCOMPCTRL */
799 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL
800 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL
801 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0
802 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL
803 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL
804 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)
805 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4
806 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL
807 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL
808 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)
809 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12
810 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL
811 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL
812 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)
813 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20
814 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL
815 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL
816 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)
817 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24
818 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL
819 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL
820 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)
821 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28
822 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL
823 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL
824 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)
826 /* Bit fields for EMU DCDCLNVCTRL */
827 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL
828 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL
829 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1)
830 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1
831 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL
832 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL
833 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL
834 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL
835 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)
836 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)
837 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)
838 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8
839 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL
840 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL
841 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)
843 /* Bit fields for EMU DCDCTIMING */
844 #define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL
845 #define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL
846 #define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0
847 #define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL
848 #define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL
849 #define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0)
850 #define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11)
851 #define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11
852 #define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL
853 #define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL
854 #define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11)
855 #define _EMU_DCDCTIMING_LNWAIT_SHIFT 12
856 #define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL
857 #define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL
858 #define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12)
859 #define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20
860 #define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL
861 #define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL
862 #define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20)
863 #define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29
864 #define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL
865 #define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL
866 #define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29)
868 /* Bit fields for EMU DCDCLPVCTRL */
869 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL
870 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL
871 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0)
872 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0
873 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL
874 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL
875 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL
876 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL
877 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)
878 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)
879 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)
880 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1
881 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL
882 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL
883 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)
885 /* Bit fields for EMU DCDCLPCTRL */
886 #define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL
887 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL
888 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12
889 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL
890 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL
891 #define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12)
892 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24)
893 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24
894 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL
895 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL
896 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)
897 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25
898 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL
899 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL
900 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)
902 /* Bit fields for EMU DCDCLNFREQCTRL */
903 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL
904 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL
905 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0
906 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL
907 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL
908 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)
909 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24
910 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL
911 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL
912 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)
914 /* Bit fields for EMU DCDCSYNC */
915 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL
916 #define _EMU_DCDCSYNC_MASK 0x00000001UL
917 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0)
918 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0
919 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL
920 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL
921 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)
923 /* Bit fields for EMU VMONAVDDCTRL */
924 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL
925 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL
926 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0)
927 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0
928 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL
929 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL
930 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)
931 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2)
932 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2
933 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL
934 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL
935 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)
936 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3)
937 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3
938 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL
939 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL
940 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)
941 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8
942 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL
943 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL
944 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)
945 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12
946 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL
947 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL
948 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12)
949 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16
950 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL
951 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL
952 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)
953 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20
954 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL
955 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL
956 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20)
958 /* Bit fields for EMU VMONALTAVDDCTRL */
959 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL
960 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL
961 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0)
962 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0
963 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL
964 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL
965 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)
966 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2)
967 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2
968 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL
969 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL
970 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)
971 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3)
972 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3
973 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL
974 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL
975 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)
976 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8
977 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL
978 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL
979 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)
980 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12
981 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL
982 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL
983 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12)
985 /* Bit fields for EMU VMONDVDDCTRL */
986 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL
987 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL
988 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0)
989 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0
990 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL
991 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL
992 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)
993 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2)
994 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2
995 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL
996 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL
997 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)
998 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3)
999 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3
1000 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL
1001 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL
1002 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)
1003 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8
1004 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL
1005 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL
1006 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)
1007 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12
1008 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL
1009 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL
1010 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12)
1012 /* Bit fields for EMU VMONIO0CTRL */
1013 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL
1014 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL
1015 #define EMU_VMONIO0CTRL_EN (0x1UL << 0)
1016 #define _EMU_VMONIO0CTRL_EN_SHIFT 0
1017 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL
1018 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL
1019 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)
1020 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2)
1021 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2
1022 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL
1023 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL
1024 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)
1025 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3)
1026 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3
1027 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL
1028 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL
1029 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)
1030 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4)
1031 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4
1032 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL
1033 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL
1034 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)
1035 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8
1036 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL
1037 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL
1038 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)
1039 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12
1040 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL
1041 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL
1042 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12)
1044 /* Bit fields for EMU BIASCONF */
1045 #define _EMU_BIASCONF_RESETVALUE 0x000000F8UL
1046 #define _EMU_BIASCONF_MASK 0x000000FCUL
1047 #define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2)
1048 #define _EMU_BIASCONF_NADUTYEM01_SHIFT 2
1049 #define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL
1050 #define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL
1051 #define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2)
1052 #define EMU_BIASCONF_LPEM01 (0x1UL << 3)
1053 #define _EMU_BIASCONF_LPEM01_SHIFT 3
1054 #define _EMU_BIASCONF_LPEM01_MASK 0x8UL
1055 #define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL
1056 #define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3)
1057 #define EMU_BIASCONF_GMCEM23 (0x1UL << 4)
1058 #define _EMU_BIASCONF_GMCEM23_SHIFT 4
1059 #define _EMU_BIASCONF_GMCEM23_MASK 0x10UL
1060 #define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL
1061 #define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4)
1062 #define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5)
1063 #define _EMU_BIASCONF_UADUTYEM23_SHIFT 5
1064 #define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL
1065 #define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL
1066 #define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5)
1067 #define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6)
1068 #define _EMU_BIASCONF_NADUTYEM23_SHIFT 6
1069 #define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL
1070 #define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL
1071 #define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6)
1072 #define EMU_BIASCONF_LPEM23 (0x1UL << 7)
1073 #define _EMU_BIASCONF_LPEM23_SHIFT 7
1074 #define _EMU_BIASCONF_LPEM23_MASK 0x80UL
1075 #define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL
1076 #define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7)
1078 /* Bit fields for EMU TESTLOCK */
1079 #define _EMU_TESTLOCK_RESETVALUE 0x00000000UL
1080 #define _EMU_TESTLOCK_MASK 0x0000FFFFUL
1081 #define _EMU_TESTLOCK_LOCKKEY_SHIFT 0
1082 #define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL
1083 #define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL
1084 #define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL
1085 #define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL
1086 #define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL
1087 #define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
1088 #define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0)
1089 #define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0)
1090 #define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0)
1091 #define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0)
1092 #define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0)
1094 /* Bit fields for EMU BIASTESTCTRL */
1095 #define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL
1096 #define _EMU_BIASTESTCTRL_MASK 0x00000008UL
1097 #define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3)
1098 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3
1099 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL
1100 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL
1101 #define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3)
__IOM uint32_t EM4CTRL
Definition: efr32mg1p_emu.h:50
__IOM uint32_t TESTLOCK
Definition: efr32mg1p_emu.h:88
__IOM uint32_t PWRCTRL
Definition: efr32mg1p_emu.h:59
__IOM uint32_t DCDCLPVCTRL
Definition: efr32mg1p_emu.h:69
__IM uint32_t TEMP
Definition: efr32mg1p_emu.h:52
__IOM uint32_t DCDCLNFREQCTRL
Definition: efr32mg1p_emu.h:73
__IOM uint32_t IFS
Definition: efr32mg1p_emu.h:54
__IOM uint32_t BIASCONF
Definition: efr32mg1p_emu.h:85
__IOM uint32_t DCDCLNVCTRL
Definition: efr32mg1p_emu.h:67
__IOM uint32_t IFC
Definition: efr32mg1p_emu.h:55
__IOM uint32_t DCDCCTRL
Definition: efr32mg1p_emu.h:60
__IOM uint32_t PWRCFG
Definition: efr32mg1p_emu.h:58
__IOM uint32_t IEN
Definition: efr32mg1p_emu.h:56
__IOM uint32_t VMONAVDDCTRL
Definition: efr32mg1p_emu.h:79
__IOM uint32_t DCDCTIMING
Definition: efr32mg1p_emu.h:68
__IOM uint32_t CMD
Definition: efr32mg1p_emu.h:47
__IOM uint32_t VMONIO0CTRL
Definition: efr32mg1p_emu.h:82
__IOM uint32_t TEMPLIMITS
Definition: efr32mg1p_emu.h:51
__IOM uint32_t DCDCLPCTRL
Definition: efr32mg1p_emu.h:72
__IOM uint32_t DCDCCLIMCTRL
Definition: efr32mg1p_emu.h:65
__IM uint32_t IF
Definition: efr32mg1p_emu.h:53
__IOM uint32_t CTRL
Definition: efr32mg1p_emu.h:43
__IM uint32_t DCDCSYNC
Definition: efr32mg1p_emu.h:76
__IOM uint32_t VMONALTAVDDCTRL
Definition: efr32mg1p_emu.h:80
__IOM uint32_t DCDCLNCOMPCTRL
Definition: efr32mg1p_emu.h:66
__IOM uint32_t PWRLOCK
Definition: efr32mg1p_emu.h:57
__IM uint32_t STATUS
Definition: efr32mg1p_emu.h:44
__IOM uint32_t DCDCZDETCTRL
Definition: efr32mg1p_emu.h:64
__IOM uint32_t RAM0CTRL
Definition: efr32mg1p_emu.h:46
__IOM uint32_t LOCK
Definition: efr32mg1p_emu.h:45
__IOM uint32_t BIASTESTCTRL
Definition: efr32mg1p_emu.h:91
__IOM uint32_t DCDCMISCCTRL
Definition: efr32mg1p_emu.h:63
__IOM uint32_t VMONDVDDCTRL
Definition: efr32mg1p_emu.h:81