em_emu.h

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/***************************************************************************/
#ifndef EM_EMU_H
#define EM_EMU_H

#include "em_device.h"
#if defined( EMU_PRESENT )

#include <stdbool.h>
#include "em_bus.h"

#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************************/
/***************************************************************************/
/*******************************************************************************
 ********************************   ENUMS   ************************************
 ******************************************************************************/

#if defined( _EMU_EM4CONF_OSC_MASK )

typedef enum
{
  emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
  emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
  emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
} EMU_EM4Osc_TypeDef;
#endif

#if defined( _EMU_BUCTRL_PROBE_MASK )

typedef enum
{
  emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
  emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
  emuProbe_BUIN    = EMU_BUCTRL_PROBE_BUIN,
  emuProbe_BUOUT   = EMU_BUCTRL_PROBE_BUOUT
} EMU_Probe_TypeDef;
#endif

#if defined( _EMU_PWRCONF_PWRRES_MASK )

typedef enum
{
  emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
  emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
  emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
  emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
} EMU_Resistor_TypeDef;
#endif

#if defined( BU_PRESENT )

typedef enum
{
  emuPower_None = EMU_BUINACT_PWRCON_NONE,
  emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
  emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
  emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
} EMU_Power_TypeDef;
#endif

typedef enum
{
  emuBODMode_Active,
  emuBODMode_Inactive,
} EMU_BODMode_TypeDef;

#if defined( _EMU_EM4CTRL_EM4STATE_MASK )

typedef enum
{
  emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
  emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,
} EMU_EM4State_TypeDef;
#endif


#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
typedef enum
{
  emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
  emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
  emuPinRetentionLatch   = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
} EMU_EM4PinRetention_TypeDef;
#endif

typedef enum
{
  emuPowerConfig_DcdcToDvdd,
} EMU_PowerConfig_TypeDef;


#if defined( _EMU_DCDCCTRL_MASK )

typedef enum
{
  emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
  emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
#if defined(_EMU_DCDCLPEM01CFG_MASK)

  emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER,
#endif
} EMU_DcdcMode_TypeDef;
#endif

#if defined( _EMU_DCDCCTRL_MASK )

typedef enum
{
  emuDcdcConductionMode_ContinuousLN,
  emuDcdcConductionMode_DiscontinuousLN,
} EMU_DcdcConductionMode_TypeDef;
#endif

#if defined( _EMU_PWRCTRL_MASK )

typedef enum
{
  emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
  emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
} EMU_DcdcAnaPeripheralPower_TypeDef;
#endif

#if defined( _EMU_DCDCMISCCTRL_MASK )

typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;

#define emuDcdcLnHighEfficiency       -1

#define emuDcdcLnFastTransient         160
#endif


#if defined( _EMU_DCDCCTRL_MASK )

typedef enum
{
  emuDcdcLnRcoBand_3MHz = 0,
  emuDcdcLnRcoBand_4MHz = 1,
  emuDcdcLnRcoBand_5MHz = 2,
  emuDcdcLnRcoBand_6MHz = 3,
  emuDcdcLnRcoBand_7MHz = 4,
  emuDcdcLnRcoBand_8MHz = 5,
  emuDcdcLnRcoBand_9MHz = 6,
  emuDcdcLnRcoBand_10MHz = 7,
} EMU_DcdcLnRcoBand_TypeDef;

/* Deprecated. */
#define EMU_DcdcLnRcoBand_3MHz          emuDcdcLnRcoBand_3MHz
#define EMU_DcdcLnRcoBand_4MHz          emuDcdcLnRcoBand_4MHz
#define EMU_DcdcLnRcoBand_5MHz          emuDcdcLnRcoBand_5MHz
#define EMU_DcdcLnRcoBand_6MHz          emuDcdcLnRcoBand_6MHz
#define EMU_DcdcLnRcoBand_7MHz          emuDcdcLnRcoBand_7MHz
#define EMU_DcdcLnRcoBand_8MHz          emuDcdcLnRcoBand_8MHz
#define EMU_DcdcLnRcoBand_9MHz          emuDcdcLnRcoBand_9MHz
#define EMU_DcdcLnRcoBand_10MHz         emuDcdcLnRcoBand_10MHz

#endif


#if defined( _EMU_DCDCCTRL_MASK )

typedef enum
{
  emuDcdcLnCompCtrl_1u0F,
  emuDcdcLnCompCtrl_4u7F,
} EMU_DcdcLnCompCtrl_TypeDef;
#endif


#if defined( EMU_STATUS_VMONRDY )

typedef enum
{
  emuVmonChannel_AVDD,
  emuVmonChannel_ALTAVDD,
  emuVmonChannel_DVDD,
  emuVmonChannel_IOVDD0
} EMU_VmonChannel_TypeDef;
#endif /* EMU_STATUS_VMONRDY */

#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )

typedef enum
{
  emuBiasMode_1KHz,
  emuBiasMode_4KHz,
  emuBiasMode_Continuous
} EMU_BiasMode_TypeDef;
#endif

#if defined( _EMU_CMD_EM01VSCALE0_MASK )

typedef enum
{
  emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
  emuVScaleEM01_LowPower        = _EMU_STATUS_VSCALE_VSCALE0,
} EMU_VScaleEM01_TypeDef;
#endif

#if defined( _EMU_CTRL_EM23VSCALE_MASK )

typedef enum
{
  emuVScaleEM23_FastWakeup      = _EMU_CTRL_EM23VSCALE_VSCALE2,
  emuVScaleEM23_LowPower        = _EMU_CTRL_EM23VSCALE_VSCALE0,
} EMU_VScaleEM23_TypeDef;
#endif

#if defined( _EMU_CTRL_EM4HVSCALE_MASK )

typedef enum
{
  emuVScaleEM4H_FastWakeup      = _EMU_CTRL_EM4HVSCALE_VSCALE2,
  emuVScaleEM4H_LowPower        = _EMU_CTRL_EM4HVSCALE_VSCALE0,
} EMU_VScaleEM4H_TypeDef;
#endif

#if defined(_EMU_EM23PERNORETAINCTRL_MASK)

typedef enum
{
  emuPeripheralRetention_LEUART0  = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK,       /* Select LEUART0 retention control  */
  emuPeripheralRetention_CSEN     = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK,          /* Select CSEN retention control  */
  emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,      /* Select LESENSE0 retention control  */
  emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK,      /* Select LETIMER0 retention control  */
  emuPeripheralRetention_ADC0     = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK,          /* Select ADC0 retention control  */
  emuPeripheralRetention_IDAC0    = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK,         /* Select IDAC0 retention control  */
  emuPeripheralRetention_VDAC0    = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK,          /* Select DAC0 retention control  */
  emuPeripheralRetention_I2C1     = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK,          /* Select I2C1 retention control  */
  emuPeripheralRetention_I2C0     = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,          /* Select I2C0 retention control  */
  emuPeripheralRetention_ACMP1    = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK,         /* Select ACMP1 retention control  */
  emuPeripheralRetention_ACMP0    = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK,         /* Select ACMP0 retention control  */
#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
  emuPeripheralRetention_PCNT2    = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK,         /* Select PCNT2 retention control  */
  emuPeripheralRetention_PCNT1    = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK,         /* Select PCNT1 retention control  */
#endif
  emuPeripheralRetention_PCNT0    = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK,         /* Select PCNT0 retention control  */

  emuPeripheralRetention_D1       = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */
  emuPeripheralRetention_D2       = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
                                        | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
#endif
                                        | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK
                                        | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK,    /* Select all peripherals in domain 2 */
 emuPeripheralRetention_ALL       = emuPeripheralRetention_D1
                                        | emuPeripheralRetention_D2,                /* Select all peripherals with retention control  */
} EMU_PeripheralRetention_TypeDef;
#endif

/*******************************************************************************
 *******************************   STRUCTS   ***********************************
 ******************************************************************************/

#if defined( _EMU_CMD_EM01VSCALE0_MASK )

typedef struct
{
  bool  vScaleEM01LowPowerVoltageEnable;                 
} EMU_EM01Init_TypeDef;
#endif

#if defined( _EMU_CMD_EM01VSCALE0_MASK )

#define EMU_EM01INIT_DEFAULT                                                                                    \
{                                                                                                               \
  false                                                                        \
}
#endif

typedef struct
{
  bool                          em23VregFullEn;         
#if defined( _EMU_CTRL_EM23VSCALE_MASK )
  EMU_VScaleEM23_TypeDef        vScaleEM23Voltage;      
#endif
} EMU_EM23Init_TypeDef;

#if defined( _EMU_CTRL_EM4HVSCALE_MASK )
#define EMU_EM23INIT_DEFAULT                                                                                    \
{                                                                                                               \
  false,                                                /* Reduced voltage regulator drive strength in EM2/3 */ \
  emuVScaleEM23_FastWakeup,                             /* Do not scale down in EM2/3 */                        \
}
#else
#define EMU_EM23INIT_DEFAULT                                                                                    \
{                                                                                                               \
  false,                                                /* Reduced voltage regulator drive strength in EM2/3 */ \
}
#endif

#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )

typedef struct
{
#if defined( _EMU_EM4CONF_MASK )
  /* Init parameters for platforms with EMU->EM4CONF register (Series 0) */
  bool                        lockConfig;       
  bool                        buBodRstDis;      
  EMU_EM4Osc_TypeDef          osc;              
  bool                        buRtcWakeup;      
  bool                        vreg;             
#elif defined( _EMU_EM4CTRL_MASK )
  /* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */
  bool                        retainLfxo;       
  bool                        retainLfrco;      
  bool                        retainUlfrco;     
  EMU_EM4State_TypeDef        em4State;         
  EMU_EM4PinRetention_TypeDef pinRetentionMode; 
#endif
#if defined( _EMU_CTRL_EM4HVSCALE_MASK )
  EMU_VScaleEM4H_TypeDef      vScaleEM4HVoltage;
#endif
} EMU_EM4Init_TypeDef;
#endif

#if defined( _EMU_EM4CONF_MASK )

#define EMU_EM4INIT_DEFAULT                                                                \
{                                                                                          \
  false,                              /* Dont't lock configuration after it's been set */  \
  false,                              /* No reset will be asserted due to BOD in EM4 */    \
  emuEM4Osc_ULFRCO,                   /* Use default ULFRCO oscillator  */                 \
  true,                               /* Wake up on EM4 BURTC interrupt */                 \
  true,                               /* Enable VREG */                                    \
}

#elif defined( _EMU_CTRL_EM4HVSCALE_MASK )

#define EMU_EM4INIT_DEFAULT                                                                \
{                                                                                          \
  false,                             /* Retain LFXO configuration upon EM4 entry */        \
  false,                             /* Retain LFRCO configuration upon EM4 entry */       \
  false,                             /* Retain ULFRCO configuration upon EM4 entry */      \
  emuEM4Shutoff,                     /* Use EM4 shutoff state */                           \
  emuPinRetentionDisable,            /* Do not retain pins in EM4 */                       \
  emuVScaleEM4H_FastWakeup,          /* Do not scale down in EM4H */                       \
}

#elif defined( _EMU_EM4CTRL_MASK )

#define EMU_EM4INIT_DEFAULT                                                                \
{                                                                                          \
  false,                             /* Retain LFXO configuration upon EM4 entry */        \
  false,                             /* Retain LFRCO configuration upon EM4 entry */       \
  false,                             /* Retain ULFRCO configuration upon EM4 entry */      \
  emuEM4Shutoff,                     /* Use EM4 shutoff state */                           \
  emuPinRetentionDisable,            /* Do not retain pins in EM4 */                       \
}
#endif

#if defined( BU_PRESENT )

typedef struct
{
  /* Backup Power Domain power configuration */

  EMU_Probe_TypeDef     probe;
  bool                  bodCal;
  bool                  statusPinEnable;

  /* Backup Power Domain connection configuration */
  EMU_Resistor_TypeDef  resistor;
  bool                  voutStrong;
  bool                  voutMed;
  bool                  voutWeak;
  EMU_Power_TypeDef  inactivePower;
  EMU_Power_TypeDef     activePower;
  bool                  enable;
} EMU_BUPDInit_TypeDef;

#define EMU_BUPDINIT_DEFAULT                                              \
{                                                                         \
  emuProbe_Disable, /* Do not enable voltage probe */                     \
  false,            /* Disable BOD calibration mode */                    \
  false,            /* Disable BU_STAT pin for backup mode indication */  \
                                                                          \
  emuRes_Res0,      /* RES0 series resistance between main and backup power */ \
  false,            /* Don't enable strong switch */                           \
  false,            /* Don't enable medium switch */                           \
  false,            /* Don't enable weak switch */                             \
                                                                               \
  emuPower_None,    /* No connection between main and backup power (inactive mode) */     \
  emuPower_None,    /* No connection between main and backup power (active mode) */       \
  true              /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset  */  \
}
#endif

#if defined( _EMU_DCDCCTRL_MASK )

typedef struct
{
  EMU_PowerConfig_TypeDef powerConfig;                  
  EMU_DcdcMode_TypeDef dcdcMode;                        
  uint16_t mVout;                                       
  uint16_t em01LoadCurrent_mA;                          
  uint16_t em234LoadCurrent_uA;                         
  uint16_t maxCurrent_mA;                               
  EMU_DcdcAnaPeripheralPower_TypeDef
    anaPeripheralPower;                                 
  EMU_DcdcLnReverseCurrentControl_TypeDef
    reverseCurrentControl;                              
  EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl;            
} EMU_DCDCInit_TypeDef;

#if defined( _EFM_DEVICE )
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
#define EMU_DCDCINIT_DEFAULT                                                                                    \
{                                                                                                               \
  emuPowerConfig_DcdcToDvdd,     /* DCDC to DVDD */                                                             \
  emuDcdcMode_LowNoise,          /* Low-niose mode in EM0 */                                                    \
  1800,                          /* Nominal output voltage for DVDD mode, 1.8V  */                              \
  5,                             /* Nominal EM0/1 load current of less than 5mA */                              \
  10,                            /* Nominal EM2/3/4 load current less than 10uA  */                             \
  200,                           /* Maximum average current of 200mA
                                    (assume strong battery or other power source) */                            \
  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */                         \
  emuDcdcLnHighEfficiency,       /* Use high-efficiency mode */                                                 \
  emuDcdcLnCompCtrl_1u0F,        /* 1uF DCDC capacitor */                                                       \
}
#else
#define EMU_DCDCINIT_DEFAULT                                                                                    \
{                                                                                                               \
  emuPowerConfig_DcdcToDvdd,     /* DCDC to DVDD */                                                             \
  emuDcdcMode_LowPower,          /* Low-power mode in EM0 */                                                    \
  1800,                          /* Nominal output voltage for DVDD mode, 1.8V  */                              \
  5,                             /* Nominal EM0/1 load current of less than 5mA */                              \
  10,                            /* Nominal EM2/3/4 load current less than 10uA  */                             \
  200,                           /* Maximum average current of 200mA
                                    (assume strong battery or other power source) */                            \
  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */                         \
  emuDcdcLnHighEfficiency,       /* Use high-efficiency mode */                                                 \
  emuDcdcLnCompCtrl_4u7F,        /* 4.7uF DCDC capacitor */                                                     \
}
#endif

#else /* EFR32 device */
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
#define EMU_DCDCINIT_DEFAULT                                                                                    \
{                                                                                                               \
  emuPowerConfig_DcdcToDvdd,     /* DCDC to DVDD */                                                             \
  emuDcdcMode_LowNoise,          /* Low-niose mode in EM0 */                                                    \
  1800,                          /* Nominal output voltage for DVDD mode, 1.8V  */                              \
  15,                            /* Nominal EM0/1 load current of less than 15mA */                             \
  10,                            /* Nominal EM2/3/4 load current less than 10uA  */                             \
  200,                           /* Maximum average current of 200mA
                                    (assume strong battery or other power source) */                            \
  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */                         \
  160,                           /* Maximum reverse current of 160mA */                                         \
  emuDcdcLnCompCtrl_1u0F,        /* 1uF DCDC capacitor */                                                       \
}
#else
#define EMU_DCDCINIT_DEFAULT                                                                                    \
{                                                                                                               \
  emuPowerConfig_DcdcToDvdd,     /* DCDC to DVDD */                                                             \
  emuDcdcMode_LowNoise,          /* Low-niose mode in EM0 */                                                    \
  1800,                          /* Nominal output voltage for DVDD mode, 1.8V  */                              \
  15,                            /* Nominal EM0/1 load current of less than 15mA */                             \
  10,                            /* Nominal EM2/3/4 load current less than 10uA  */                             \
  200,                           /* Maximum average current of 200mA
                                    (assume strong battery or other power source) */                            \
  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */                         \
  160,                           /* Maximum reverse current of 160mA */                                         \
  emuDcdcLnCompCtrl_4u7F,        /* 4.7uF DCDC capacitor */                                                     \
}
#endif
#endif
#endif

#if defined( EMU_STATUS_VMONRDY )

typedef struct
{
  EMU_VmonChannel_TypeDef channel;      
  int threshold;                        
  bool riseWakeup;                      
  bool fallWakeup;                      
  bool enable;                          
  bool retDisable;                      
} EMU_VmonInit_TypeDef;

#define EMU_VMONINIT_DEFAULT                                                       \
{                                                                                  \
  emuVmonChannel_AVDD,                  /* AVDD VMON channel */                    \
  3200,                                 /* 3.2 V threshold */                      \
  false,                                /* Don't wake from EM4H on rising edge */  \
  false,                                /* Don't wake from EM4H on falling edge */ \
  true,                                 /* Enable VMON channel */                  \
  false                                 /* Don't disable IO0 retention */          \
}

typedef struct
{
  EMU_VmonChannel_TypeDef channel;      
  int riseThreshold;                    
  int fallThreshold;                    
  bool riseWakeup;                      
  bool fallWakeup;                      
  bool enable;                          
} EMU_VmonHystInit_TypeDef;

#define EMU_VMONHYSTINIT_DEFAULT                                                   \
{                                                                                  \
  emuVmonChannel_AVDD,                  /* AVDD VMON channel */                    \
  3200,                                 /* 3.2 V rise threshold */                 \
  3200,                                 /* 3.2 V fall threshold */                 \
  false,                                /* Don't wake from EM4H on rising edge */  \
  false,                                /* Don't wake from EM4H on falling edge */ \
  true                                  /* Enable VMON channel */                  \
}
#endif /* EMU_STATUS_VMONRDY */

/*******************************************************************************
 *****************************   PROTOTYPES   **********************************
 ******************************************************************************/

#if defined( _EMU_CMD_EM01VSCALE0_MASK )
void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init);
#endif
void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init);
#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
#endif
void EMU_EnterEM2(bool restore);
void EMU_EnterEM3(bool restore);
void EMU_Restore(void);
void EMU_EnterEM4(void);
#if defined( _EMU_EM4CTRL_MASK )
void EMU_EnterEM4H(void);
void EMU_EnterEM4S(void);
#endif
void EMU_MemPwrDown(uint32_t blocks);
void EMU_RamPowerDown(uint32_t start, uint32_t end);
#if defined(_EMU_EM23PERNORETAINCTRL_MASK)
void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable);
#endif
void EMU_UpdateOscConfig(void);
#if defined( _EMU_CMD_EM01VSCALE0_MASK )
void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
#endif
#if defined( BU_PRESENT )
void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
#endif
#if defined( _EMU_DCDCCTRL_MASK )
bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit);
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet);
bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent);
void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
bool EMU_DCDCPowerOff(void);
#endif
#if defined( EMU_STATUS_VMONRDY )
void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit);
void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit);
void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
#endif

/***************************************************************************/
__STATIC_INLINE void EMU_EnterEM1(void)
{
  /* Enter sleep mode */
  SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
  __WFI();
}


#if defined( _EMU_STATUS_VSCALE_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_VScaleWait(void)
{
  while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT));
}
#endif

#if defined( _EMU_STATUS_VSCALE_MASK )
/***************************************************************************/
__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void)
{
  EMU_VScaleWait();
  return (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
                                  >> _EMU_STATUS_VSCALE_SHIFT);
}
#endif

#if defined( _EMU_STATUS_VMONRDY_MASK )
/***************************************************************************/
__STATIC_INLINE bool EMU_VmonStatusGet(void)
{
  return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT);
}
#endif /* _EMU_STATUS_VMONRDY_MASK */

#if defined( _EMU_IF_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_IntClear(uint32_t flags)
{
  EMU->IFC = flags;
}


/***************************************************************************/
__STATIC_INLINE void EMU_IntDisable(uint32_t flags)
{
  EMU->IEN &= ~flags;
}


/***************************************************************************/
__STATIC_INLINE void EMU_IntEnable(uint32_t flags)
{
  EMU->IEN |= flags;
}


/***************************************************************************/
__STATIC_INLINE uint32_t EMU_IntGet(void)
{
  return EMU->IF;
}


/***************************************************************************/
__STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
{
  uint32_t ien;

  ien = EMU->IEN;
  return EMU->IF & ien;
}


/***************************************************************************/
__STATIC_INLINE void EMU_IntSet(uint32_t flags)
{
  EMU->IFS = flags;
}
#endif /* _EMU_IF_MASK */


#if defined( _EMU_EM4CONF_LOCKCONF_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_EM4Lock(bool enable)
{
  BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
}
#endif

#if defined( _EMU_STATUS_BURDY_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_BUReady(void)
{
  while(!(EMU->STATUS & EMU_STATUS_BURDY))
    ;
}
#endif

#if defined( _EMU_ROUTE_BUVINPEN_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_BUPinEnable(bool enable)
{
  BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
}
#endif

/***************************************************************************/
__STATIC_INLINE void EMU_Lock(void)
{
  EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK;
}


/***************************************************************************/
__STATIC_INLINE void EMU_Unlock(void)
{
  EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
}


#if defined( _EMU_PWRLOCK_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_PowerLock(void)
{
  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
}


/***************************************************************************/
__STATIC_INLINE void EMU_PowerUnlock(void)
{
  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
}
#endif


/***************************************************************************/
__STATIC_INLINE void EMU_EM2Block(void)
{
  BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
}

/***************************************************************************/
__STATIC_INLINE void EMU_EM2UnBlock(void)
{
  BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
}

#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
/***************************************************************************/
__STATIC_INLINE void EMU_UnlatchPinRetention(void)
{
  EMU->CMD = EMU_CMD_EM4UNLATCH;
}
#endif

#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
#endif

#ifdef __cplusplus
}
#endif

#endif /* defined( EMU_PRESENT ) */
#endif /* EM_EMU_H */