EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
efr32mg1p233f256gm48.h
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1 /**************************************************************************/
34 #ifndef EFR32MG1P233F256GM48_H
35 #define EFR32MG1P233F256GM48_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**************************************************************************/
46 /**************************************************************************/
52 typedef enum IRQn
53 {
54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
58  BusFault_IRQn = -11,
60  SVCall_IRQn = -5,
62  PendSV_IRQn = -2,
63  SysTick_IRQn = -1,
65 /****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
66 
67  EMU_IRQn = 0,
68  WDOG0_IRQn = 2,
69  LDMA_IRQn = 8,
71  TIMER0_IRQn = 10,
74  ACMP0_IRQn = 13,
75  ADC0_IRQn = 14,
76  IDAC0_IRQn = 15,
77  I2C0_IRQn = 16,
79  TIMER1_IRQn = 18,
82  LEUART0_IRQn = 21,
83  PCNT0_IRQn = 22,
84  CMU_IRQn = 23,
85  MSC_IRQn = 24,
86  CRYPTO_IRQn = 25,
88  RTCC_IRQn = 29,
90  FPUEH_IRQn = 33,
91 } IRQn_Type;
92 
93 /**************************************************************************/
98 #define __MPU_PRESENT 1
99 #define __FPU_PRESENT 1
100 #define __VTOR_PRESENT 1
101 #define __NVIC_PRIO_BITS 3
102 #define __Vendor_SysTickConfig 0
106 /**************************************************************************/
112 #define _EFR32_MIGHTY_FAMILY 1
113 #define _EFR_DEVICE
114 #define _SILICON_LABS_32B_SERIES_1
115 #define _SILICON_LABS_32B_SERIES 1
116 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1
117 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1
118 #define _SILICON_LABS_GECKO_INTERNAL_SDID 80
119 #define _SILICON_LABS_GECKO_INTERNAL_SDID_80
120 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
121 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
122 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
123 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND
124 #define _SILICON_LABS_32B_PLATFORM_2
125 #define _SILICON_LABS_32B_PLATFORM 2
126 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1
127 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1
129 /* If part number is not defined as compiler option, define it */
130 #if !defined(EFR32MG1P233F256GM48)
131 #define EFR32MG1P233F256GM48 1
132 #endif
133 
135 #define PART_NUMBER "EFR32MG1P233F256GM48"
138 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL)
139 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
140 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL)
141 #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL)
142 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
143 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL)
144 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL)
145 #define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL)
146 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL)
147 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL)
148 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL)
149 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL)
150 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL)
151 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL)
152 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL)
153 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL)
154 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL)
155 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL)
156 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL)
157 #define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL)
158 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL)
159 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL)
160 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL)
161 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL)
162 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL)
163 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL)
164 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL)
165 #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL)
166 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
167 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL)
168 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL)
169 #define PER_MEM_BITS ((uint32_t) 0x00000014UL)
170 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
171 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL)
172 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL)
173 #define RAM_MEM_BITS ((uint32_t) 0x0000000FUL)
176 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
177 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
180 #define FLASH_BASE (0x00000000UL)
181 #define FLASH_SIZE (0x00040000UL)
182 #define FLASH_PAGE_SIZE 2048
183 #define SRAM_BASE (0x20000000UL)
184 #define SRAM_SIZE (0x00007C00UL)
185 #define __CM4_REV 0x001
186 #define PRS_CHAN_COUNT 12
187 #define DMA_CHAN_COUNT 8
188 #define EXT_IRQ_COUNT 34
191 #define AFCHAN_MAX 72
192 #define AFCHANLOC_MAX 32
193 
194 #define AFACHAN_MAX 61
195 
196 /* Part number capabilities */
197 
198 #define TIMER_PRESENT
199 #define TIMER_COUNT 2
200 #define USART_PRESENT
201 #define USART_COUNT 2
202 #define LEUART_PRESENT
203 #define LEUART_COUNT 1
204 #define LETIMER_PRESENT
205 #define LETIMER_COUNT 1
206 #define PCNT_PRESENT
207 #define PCNT_COUNT 1
208 #define I2C_PRESENT
209 #define I2C_COUNT 1
210 #define ADC_PRESENT
211 #define ADC_COUNT 1
212 #define ACMP_PRESENT
213 #define ACMP_COUNT 2
214 #define IDAC_PRESENT
215 #define IDAC_COUNT 1
216 #define WDOG_PRESENT
217 #define WDOG_COUNT 1
218 #define MSC_PRESENT
219 #define MSC_COUNT 1
220 #define EMU_PRESENT
221 #define EMU_COUNT 1
222 #define RMU_PRESENT
223 #define RMU_COUNT 1
224 #define CMU_PRESENT
225 #define CMU_COUNT 1
226 #define CRYPTO_PRESENT
227 #define CRYPTO_COUNT 1
228 #define GPIO_PRESENT
229 #define GPIO_COUNT 1
230 #define PRS_PRESENT
231 #define PRS_COUNT 1
232 #define LDMA_PRESENT
233 #define LDMA_COUNT 1
234 #define FPUEH_PRESENT
235 #define FPUEH_COUNT 1
236 #define GPCRC_PRESENT
237 #define GPCRC_COUNT 1
238 #define CRYOTIMER_PRESENT
239 #define CRYOTIMER_COUNT 1
240 #define RTCC_PRESENT
241 #define RTCC_COUNT 1
242 #define BOOTLOADER_PRESENT
243 #define BOOTLOADER_COUNT 1
244 
245 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
246 #include "system_efr32mg1p.h" /* System Header File */
247 
250 /**************************************************************************/
256 #include "efr32mg1p_msc.h"
257 #include "efr32mg1p_emu.h"
258 #include "efr32mg1p_rmu.h"
259 #include "efr32mg1p_cmu.h"
260 #include "efr32mg1p_crypto.h"
261 #include "efr32mg1p_gpio_p.h"
262 #include "efr32mg1p_gpio.h"
263 #include "efr32mg1p_prs_ch.h"
264 #include "efr32mg1p_prs.h"
265 #include "efr32mg1p_ldma_ch.h"
266 #include "efr32mg1p_ldma.h"
267 #include "efr32mg1p_fpueh.h"
268 #include "efr32mg1p_gpcrc.h"
269 #include "efr32mg1p_timer_cc.h"
270 #include "efr32mg1p_timer.h"
271 #include "efr32mg1p_usart.h"
272 #include "efr32mg1p_leuart.h"
273 #include "efr32mg1p_letimer.h"
274 #include "efr32mg1p_cryotimer.h"
275 #include "efr32mg1p_pcnt.h"
276 #include "efr32mg1p_i2c.h"
277 #include "efr32mg1p_adc.h"
278 #include "efr32mg1p_acmp.h"
279 #include "efr32mg1p_idac.h"
280 #include "efr32mg1p_rtcc_cc.h"
281 #include "efr32mg1p_rtcc_ret.h"
282 #include "efr32mg1p_rtcc.h"
283 #include "efr32mg1p_wdog_pch.h"
284 #include "efr32mg1p_wdog.h"
286 #include "efr32mg1p_devinfo.h"
287 #include "efr32mg1p_romtable.h"
288 
291 /**************************************************************************/
296 #define MSC_BASE (0x400E0000UL)
297 #define EMU_BASE (0x400E3000UL)
298 #define RMU_BASE (0x400E5000UL)
299 #define CMU_BASE (0x400E4000UL)
300 #define CRYPTO_BASE (0x400F0000UL)
301 #define GPIO_BASE (0x4000A000UL)
302 #define PRS_BASE (0x400E6000UL)
303 #define LDMA_BASE (0x400E2000UL)
304 #define FPUEH_BASE (0x400E1000UL)
305 #define GPCRC_BASE (0x4001C000UL)
306 #define TIMER0_BASE (0x40018000UL)
307 #define TIMER1_BASE (0x40018400UL)
308 #define USART0_BASE (0x40010000UL)
309 #define USART1_BASE (0x40010400UL)
310 #define LEUART0_BASE (0x4004A000UL)
311 #define LETIMER0_BASE (0x40046000UL)
312 #define CRYOTIMER_BASE (0x4001E000UL)
313 #define PCNT0_BASE (0x4004E000UL)
314 #define I2C0_BASE (0x4000C000UL)
315 #define ADC0_BASE (0x40002000UL)
316 #define ACMP0_BASE (0x40000000UL)
317 #define ACMP1_BASE (0x40000400UL)
318 #define IDAC0_BASE (0x40006000UL)
319 #define RTCC_BASE (0x40042000UL)
320 #define WDOG0_BASE (0x40052000UL)
321 #define DEVINFO_BASE (0x0FE081B0UL)
322 #define ROMTABLE_BASE (0xE00FFFD0UL)
323 #define LOCKBITS_BASE (0x0FE04000UL)
324 #define USERDATA_BASE (0x0FE00000UL)
328 /**************************************************************************/
333 #define MSC ((MSC_TypeDef *) MSC_BASE)
334 #define EMU ((EMU_TypeDef *) EMU_BASE)
335 #define RMU ((RMU_TypeDef *) RMU_BASE)
336 #define CMU ((CMU_TypeDef *) CMU_BASE)
337 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE)
338 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
339 #define PRS ((PRS_TypeDef *) PRS_BASE)
340 #define LDMA ((LDMA_TypeDef *) LDMA_BASE)
341 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE)
342 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE)
343 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
344 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
345 #define USART0 ((USART_TypeDef *) USART0_BASE)
346 #define USART1 ((USART_TypeDef *) USART1_BASE)
347 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
348 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
349 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE)
350 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
351 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
352 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
353 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
354 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
355 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)
356 #define RTCC ((RTCC_TypeDef *) RTCC_BASE)
357 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE)
358 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
359 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
363 /**************************************************************************/
368 #define TIMER_OFFSET 0x400
369 #define USART_OFFSET 0x400
370 #define LEUART_OFFSET 0x400
371 #define LETIMER_OFFSET 0x400
372 #define PCNT_OFFSET 0x400
373 #define I2C_OFFSET 0x400
374 #define ADC_OFFSET 0x400
375 #define ACMP_OFFSET 0x400
376 #define IDAC_OFFSET 0x400
377 #define WDOG_OFFSET 0x400
382 /**************************************************************************/
387 #include "efr32mg1p_prs_signals.h"
388 #include "efr32mg1p_dmareq.h"
389 
390 /**************************************************************************/
394 #define MSC_UNLOCK_CODE 0x1B71
395 #define EMU_UNLOCK_CODE 0xADE8
396 #define RMU_UNLOCK_CODE 0xE084
397 #define CMU_UNLOCK_CODE 0x580E
398 #define GPIO_UNLOCK_CODE 0xA534
399 #define TIMER_UNLOCK_CODE 0xCE80
400 #define RTCC_UNLOCK_CODE 0xAEE8
406 /**************************************************************************/
411 #include "efr32mg1p_af_ports.h"
412 #include "efr32mg1p_af_pins.h"
413 
416 /**************************************************************************/
429 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
430  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
431 
436 #ifdef __cplusplus
437 }
438 #endif
439 #endif /* EFR32MG1P233F256GM48_H */
EFR32MG1P_CMU register and bit field definitions.
EFR32MG1P_RTCC register and bit field definitions.
EFR32MG1P_MSC register and bit field definitions.
EFR32MG1P_DMAREQ register and bit field definitions.
CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
EFR32MG1P_PCNT register and bit field definitions.
EFR32MG1P_EMU register and bit field definitions.
EFR32MG1P_AF_PINS register and bit field definitions.
EFR32MG1P_DEVINFO register and bit field definitions.
EFR32MG1P_ADC register and bit field definitions.
EFR32MG1P_PRS register and bit field definitions.
EFR32MG1P_DMA_DESCRIPTOR register and bit field definitions.
EFR32MG1P_CRYOTIMER register and bit field definitions.
EFR32MG1P_ACMP register and bit field definitions.
EFR32MG1P_RTCC_RET register and bit field definitions.
EFR32MG1P_IDAC register and bit field definitions.
EFR32MG1P_WDOG register and bit field definitions.
EFR32MG1P_RMU register and bit field definitions.
EFR32MG1P_WDOG_PCH register and bit field definitions.
EFR32MG1P_GPIO_P register and bit field definitions.
EFR32MG1P_GPCRC register and bit field definitions.
enum IRQn IRQn_Type
EFR32MG1P_PRS_CH register and bit field definitions.
EFR32MG1P_RTCC_CC register and bit field definitions.
EFR32MG1P_GPIO register and bit field definitions.
EFR32MG1P_TIMER_CC register and bit field definitions.
EFR32MG1P_LETIMER register and bit field definitions.
EFR32MG1P_CRYPTO register and bit field definitions.
EFR32MG1P_LDMA_CH register and bit field definitions.
EFR32MG1P_TIMER register and bit field definitions.
EFR32MG1P_ROMTABLE register and bit field definitions.
EFR32MG1P_LEUART register and bit field definitions.
EFR32MG1P_I2C register and bit field definitions.
EFR32MG1P_USART register and bit field definitions.
EFR32MG1P_FPUEH register and bit field definitions.
EFR32MG1P_LDMA register and bit field definitions.