34 #if defined( DMA_PRESENT )
171 static void DMA_Prepare(
unsigned int channel,
177 unsigned int nMinus1)
204 cb->
primary = (uint8_t)primary;
212 descr->
SRCEND = (
volatile void*)src;
216 descr->
SRCEND = (
void *)((uint32_t)src + (nMinus1 << inc));
229 descr->
DSTEND = (
void *)((uint32_t)dst + (nMinus1 << inc));
233 chBit = 1 << channel;
236 DMA->CHUSEBURSTS = chBit;
240 DMA->CHUSEBURSTC = chBit;
265 #ifndef EXCLUDE_DEFAULT_DMA_IRQ_HANDLER
289 uint32_t pendingPrio;
304 pendingPrio = pending & prio;
305 for (i = 0; i < 2; i++)
315 uint32_t chmask = 1 << channel;
343 pendingPrio = pending & ~prio;
390 unsigned int nMinus1)
405 chBit = 1 << channel;
407 DMA->CHSWREQ = chBit;
454 unsigned int nMinus1)
468 DMA->CHENS = 1 << channel;
525 unsigned int primNMinus1,
528 unsigned int altNMinus1)
553 DMA->CHENS = 1 << channel;
602 EFM_ASSERT(altDescr);
603 EFM_ASSERT(count && (count <= 256));
611 descr->
SRCEND = (uint32_t *)altDescr + (count * 4) - 1;
666 chBit = 1 << channel;
678 DMA->CHSWREQ = chBit;
710 descr[channel].
USER = (uint32_t)(cfg->
cb);
715 DMA->CHPRIS = 1 << channel;
719 DMA->CHPRIC = 1 << channel;
728 DMA->IFC = (1 << channel);
810 #if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
824 void DMA_CfgLoop(
unsigned int channel, DMA_CfgLoop_TypeDef *cfg)
826 EFM_ASSERT(channel <= 1);
827 EFM_ASSERT(cfg->nMinus1 <= 1023);
833 DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
834 | (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
837 DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
838 | (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
845 #if defined( _DMA_RECT0_MASK )
855 void DMA_CfgRect(
unsigned int channel, DMA_CfgRect_TypeDef *cfg)
859 EFM_ASSERT(channel == 0);
860 EFM_ASSERT(cfg->dstStride <= 2047);
861 EFM_ASSERT(cfg->srcStride <= 2047);
862 EFM_ASSERT(cfg->height <= 1023);
865 DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
866 | (cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT)
867 | (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
916 descr->
SRCEND = (
void *)((uint32_t)(cfg->
src)
926 descr->
DSTEND = (
void *)((uint32_t)(cfg->
dst)
980 DMA->CHENS = 1<<channel;
984 DMA->CHENC = 1<<channel;
1007 return (
bool)((
DMA->CHENS >> channel) & 1);
1062 #if (DMA_CHAN_COUNT <= 4)
1063 EFM_ASSERT(!((uint32_t)(init->
controlBlock) & (128 - 1)));
1064 #elif (DMA_CHAN_COUNT <= 8) || (DMA_CHAN_COUNT <= 12)
1065 EFM_ASSERT(!((uint32_t)(init->
controlBlock) & (256 - 1)));
1067 #error "Unsupported DMA channel count (em_dma.c)."
1140 unsigned int nMinus1,
1177 descr->
SRCEND = (
volatile void*)src;
1181 descr->
SRCEND = (
void *)((uint32_t)src + (nMinus1 << inc));
1194 descr->
DSTEND = (
void *)((uint32_t)dst + (nMinus1 << inc));
1198 chBit = 1 << channel;
1201 DMA->CHUSEBURSTS = chBit;
1205 DMA->CHUSEBURSTC = chBit;
Clock management unit (CMU) API.
#define _DMA_CONFIG_CHPROT_SHIFT
DMA_DataSize_TypeDef size
#define _DMA_CTRL_SRC_INC_MASK
#define _DMA_CTRL_SRC_INC_SHIFT
DMA_ArbiterConfig_TypeDef arbRate
Emlib peripheral API "assert" implementation.
#define DMA_CTRL_CYCLE_CTRL_INVALID
DMA_DataInc_TypeDef dstInc
Callback structure that can be used to define DMA complete actions.
DMA_ArbiterConfig_TypeDef arbRate
#define _DMA_CTRL_N_MINUS_1_MASK
RAM and peripheral bit-field set and clear API.
#define _DMA_CTRL_R_POWER_SHIFT
void DMA_CfgDescrScatterGather(DMA_DESCRIPTOR_TypeDef *descr, unsigned int indx, DMA_CfgDescrSGAlt_TypeDef *cfg)
Configure an alternate DMA descriptor for use with scatter-gather DMA cycles.
void DMA_IRQHandler(void)
Interrupt handler for DMA cycle completion handling.
DMA_CB_TypeDef * cb
User definable callback handling configuration.
#define _DMA_CTRL_NEXT_USEBURST_SHIFT
DMA_DataInc_TypeDef srcInc
#define _DMA_CHREQMASKC_MASK
bool DMA_ChannelEnabled(unsigned int channel)
Check if DMA channel is enabled.
void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, const void *src, unsigned int nMinus1, bool last)
Refresh a descriptor used in a DMA ping-pong cycle.
void DMA_ChannelRequestEnable(unsigned int channel, bool enable)
Enable or disable a DMA channel request.
void DMA_Reset(void)
Reset the DMA controller.
#define _DMA_CTRL_CYCLE_CTRL_SHIFT
void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, const void *src, unsigned int nMinus1)
Activate DMA basic cycle (used for memory-peripheral transfers).
#define _DMA_CTRL_DST_INC_NONE
#define _DMA_CTRL_SRC_SIZE_SHIFT
void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, const void *primSrc, unsigned int primNMinus1, void *altDst, const void *altSrc, unsigned int altNMinus1)
Activate DMA ping-pong cycle (used for memory-peripheral transfers).
#define _DMA_CTRL_N_MINUS_1_SHIFT
#define _DMA_CTRL_SRC_INC_NONE
void DMA_Init(DMA_Init_TypeDef *init)
Initializes DMA controller.
void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg)
Configure a DMA channel.
#define _DMA_CHUSEBURSTC_MASK
DMA_DataSize_TypeDef size
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
DMA_DataInc_TypeDef srcInc
#define _DMA_CTRL_SRC_PROT_CTRL_MASK
DMA_DataInc_TypeDef dstInc
#define _DMA_CTRL_DST_INC_MASK
DMA_DESCRIPTOR_TypeDef * controlBlock
#define DMA_ERRORC_ERRORC
DMA_FuncPtr_TypeDef cbFunc
#define _DMA_CONFIG_RESETVALUE
#define _DMA_CTRL_DST_SIZE_SHIFT
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _DMA_CH_CTRL_RESETVALUE
void DMA_ActivateScatterGather(unsigned int channel, bool useBurst, DMA_DESCRIPTOR_TypeDef *altDescr, unsigned int count)
Activate DMA scatter-gather cycle (used for either memory-peripheral or memory-memory transfers)...
#define _DMA_CTRL_DST_INC_SHIFT
#define _DMA_CTRL_CYCLE_CTRL_MASK
Direct memory access (DMA) API.
void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, const void *src, unsigned int nMinus1)
Activate DMA auto-request cycle (used for memory-memory transfers).
#define _DMA_IEN_RESETVALUE
#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT
void DMA_ChannelEnable(unsigned int channel, bool enable)
Enable or disable a DMA channel.
void DMA_CfgDescr(unsigned int channel, bool primary, DMA_CfgDescr_TypeDef *cfg)
Configure DMA descriptor for auto-request, basic or ping-pong DMA cycles.