EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
em_cmu.c
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1 /***************************************************************************/
32 #include "em_cmu.h"
33 #if defined( CMU_PRESENT )
34 
35 #include <stddef.h>
36 #include <limits.h>
37 #include "em_assert.h"
38 #include "em_bus.h"
39 #include "em_emu.h"
40 #include "em_cmu.h"
41 #include "em_system.h"
42 #include "em_common.h"
43 
44 /***************************************************************************/
49 /***************************************************************************/
58 /*******************************************************************************
59  ****************************** DEFINES ************************************
60  ******************************************************************************/
61 
64 #if defined( _SILICON_LABS_32B_SERIES_1 )
65 
66 #define CMU_MAX_FREQ_0WS 26000000
67 
68 #define CMU_MAX_FREQ_1WS 40000000
69 #elif defined( _SILICON_LABS_32B_SERIES_0 )
70 
71 #define CMU_MAX_FREQ_0WS 16000000
72 
73 #define CMU_MAX_FREQ_1WS 32000000
74 #else
75 #error "Max Flash wait-state frequencies are not defined for this platform."
76 #endif
77 
79 #if defined( CMU_CTRL_HFLE )
80 
81 #if defined( _SILICON_LABS_32B_SERIES_0 ) \
82  && (defined( _EFM32_WONDER_FAMILY ) \
83  || defined( _EZR32_WONDER_FAMILY ))
84 #define CMU_MAX_FREQ_HFLE 24000000
85 
87 #elif defined( _SILICON_LABS_32B_SERIES_0 ) \
88  && (defined( _EFM32_GIANT_FAMILY ) \
89  || defined( _EFM32_LEOPARD_FAMILY ) \
90  || defined( _EZR32_LEOPARD_FAMILY ))
91 #define CMU_MAX_FREQ_HFLE maxFreqHfle()
92 #endif
93 #elif defined( CMU_CTRL_WSHFLE )
94 
95 #define CMU_MAX_FREQ_HFLE 32000000
96 #endif
97 
98 
99 /*******************************************************************************
100  ************************** LOCAL VARIABLES ********************************
101  ******************************************************************************/
102 
103 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
104 static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
105 #endif
106 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
107 #define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK)
108 #endif
109 
112 /*******************************************************************************
113  ************************** LOCAL FUNCTIONS ********************************
114  ******************************************************************************/
115 
118 #if defined( _SILICON_LABS_32B_SERIES_0 ) \
119  && (defined( _EFM32_GIANT_FAMILY ) \
120  || defined( _EFM32_LEOPARD_FAMILY ) \
121  || defined( _EZR32_LEOPARD_FAMILY ))
122 /***************************************************************************/
126 static uint32_t maxFreqHfle(void)
127 {
128  uint16_t majorMinorRev;
129 
130  switch (SYSTEM_GetFamily())
131  {
132  case systemPartFamilyEfm32Leopard:
133  case systemPartFamilyEzr32Leopard:
134  /* CHIP MAJOR bit [5:0] */
135  majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
136  >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);
137  /* CHIP MINOR bit [7:4] */
138  majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
139  >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
140  /* CHIP MINOR bit [3:0] */
141  majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
142  >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
143 
144  if (majorMinorRev >= 0x0204)
145  {
146  return 24000000;
147  }
148  else
149  {
150  return 32000000;
151  }
152 
153  case systemPartFamilyEfm32Giant:
154  return 32000000;
155 
156  default:
157  /* Invalid device family. */
158  EFM_ASSERT(false);
159  return 0;
160  }
161 }
162 #endif
163 
164 #if defined( CMU_MAX_FREQ_HFLE )
165 
166 /* Unified definitions for HFLE wait-state and prescaler fields. */
167 #if defined( CMU_CTRL_HFLE )
168 #define CMU_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK
169 #define CMU_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT
170 #define CMU_HFLE_PRESC_REG CMU->HFCORECLKDIV
171 #define CMU_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK
172 #define CMU_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT
173 #elif defined( CMU_CTRL_WSHFLE )
174 #define CMU_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK
175 #define CMU_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT
176 #define CMU_HFLE_PRESC_REG CMU->HFPRESC
177 #define CMU_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK
178 #define CMU_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
179 #endif
180 
181 /***************************************************************************/
191 static void setHfLeConfig(uint32_t hfFreq, uint32_t maxLeFreq)
192 {
193  /* Check for 1 bit fields. BUS_RegBitWrite() below are going to fail if the
194  fields are changed to more than 1 bit. */
195  EFM_ASSERT((CMU_HFLE_WS_MASK >> CMU_HFLE_WS_SHIFT) == 0x1);
196  EFM_ASSERT((CMU_HFLE_PRESC_MASK >> CMU_HFLE_PRESC_SHIFT) == 0x1);
197 
198  /* 0: set 0 wait-states and DIV2
199  1: set 1 wait-states and DIV4 */
200  unsigned int val = (hfFreq <= maxLeFreq) ? 0 : 1;
201  BUS_RegBitWrite(&CMU->CTRL, CMU_HFLE_WS_SHIFT, val);
202  BUS_RegBitWrite(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT, val);
203 }
204 
205 
206 /***************************************************************************/
213 static uint32_t getHfLeConfig(void)
214 {
215  uint32_t ws = BUS_RegBitRead(&CMU->CTRL, CMU_HFLE_WS_SHIFT);
216  uint32_t presc = BUS_RegBitRead(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT);
217 
218  /* HFLE wait-state and DIV2(0) / DIV4(1) should
219  always be set to the same value. */
220  EFM_ASSERT(ws == presc);
221  return ws;
222 }
223 #endif
224 
225 
226 /***************************************************************************/
234 static uint32_t auxClkGet(void)
235 {
236  uint32_t ret;
237 
238 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
239  ret = auxHfrcoFreq;
240 
241 #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
242  /* All series 0 families except EFM32G */
243  switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
244  {
245  case CMU_AUXHFRCOCTRL_BAND_1MHZ:
246  if ( SYSTEM_GetProdRev() >= 19 )
247  {
248  ret = 1200000;
249  }
250  else
251  {
252  ret = 1000000;
253  }
254  break;
255 
256  case CMU_AUXHFRCOCTRL_BAND_7MHZ:
257  if ( SYSTEM_GetProdRev() >= 19 )
258  {
259  ret = 6600000;
260  }
261  else
262  {
263  ret = 7000000;
264  }
265  break;
266 
267  case CMU_AUXHFRCOCTRL_BAND_11MHZ:
268  ret = 11000000;
269  break;
270 
271  case CMU_AUXHFRCOCTRL_BAND_14MHZ:
272  ret = 14000000;
273  break;
274 
275  case CMU_AUXHFRCOCTRL_BAND_21MHZ:
276  ret = 21000000;
277  break;
278 
279 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
280  case CMU_AUXHFRCOCTRL_BAND_28MHZ:
281  ret = 28000000;
282  break;
283 #endif
284 
285  default:
286  EFM_ASSERT(0);
287  ret = 0;
288  break;
289  }
290 
291 #else
292  /* Gecko has a fixed 14Mhz AUXHFRCO clock */
293  ret = 14000000;
294 
295 #endif
296 
297  return ret;
298 }
299 
300 
301 /***************************************************************************/
308 static uint32_t dbgClkGet(void)
309 {
310  uint32_t ret;
311  CMU_Select_TypeDef clk;
312 
313  /* Get selected clock source */
314  clk = CMU_ClockSelectGet(cmuClock_DBG);
315 
316  switch(clk)
317  {
318  case cmuSelect_HFCLK:
319  ret = SystemHFClockGet();
320  break;
321 
322  case cmuSelect_AUXHFRCO:
323  ret = auxClkGet();
324  break;
325 
326  default:
327  EFM_ASSERT(0);
328  ret = 0;
329  break;
330  }
331  return ret;
332 }
333 
334 
335 /***************************************************************************/
343 static void flashWaitStateControl(uint32_t coreFreq)
344 {
345  uint32_t mode;
346  bool mscLocked;
347 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
348  bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */
349 #endif
350 
351  /* Make sure the MSC is unlocked */
352  mscLocked = MSC->LOCK;
353  MSC->LOCK = MSC_UNLOCK_CODE;
354 
355  /* Get mode and SCBTP enable */
356  mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
357 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
358  switch(mode)
359  {
360  case MSC_READCTRL_MODE_WS0:
361  case MSC_READCTRL_MODE_WS1:
362 #if defined( MSC_READCTRL_MODE_WS2 )
363  case MSC_READCTRL_MODE_WS2:
364 #endif
365  scbtpEn = false;
366  break;
367 
368  default: /* WSxSCBTP */
369  scbtpEn = true;
370  break;
371  }
372 #endif
373 
374 
375  /* Set mode based on the core clock frequency and SCBTP enable */
376 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
377  if (false)
378  {
379  }
380 #if defined( MSC_READCTRL_MODE_WS2 )
381  else if (coreFreq > CMU_MAX_FREQ_1WS)
382  {
383  mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
384  }
385 #endif
386  else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
387  {
388  mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1);
389  }
390  else
391  {
392  mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0);
393  }
394 
395 #else /* If MODE and SCBTP is in separate register fields */
396 
397  if (false)
398  {
399  }
400 #if defined( MSC_READCTRL_MODE_WS2 )
401  else if (coreFreq > CMU_MAX_FREQ_1WS)
402  {
403  mode = MSC_READCTRL_MODE_WS2;
404  }
405 #endif
406  else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
407  {
408  mode = MSC_READCTRL_MODE_WS1;
409  }
410  else
411  {
412  mode = MSC_READCTRL_MODE_WS0;
413  }
414 #endif
415 
416  /* BUS_RegMaskedWrite cannot be used here as it would temporarely set the
417  mode field to WS0 */
418  MSC->READCTRL = (MSC->READCTRL &~_MSC_READCTRL_MODE_MASK) | mode;
419 
420  if (mscLocked)
421  {
422  MSC->LOCK = 0;
423  }
424 }
425 
426 
427 /***************************************************************************/
433 static void flashWaitStateMax(void)
434 {
435  flashWaitStateControl(SystemMaxCoreClockGet());
436 }
437 
438 
439 #if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)
440 /***************************************************************************/
444 static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh)
445 {
446  uint32_t regIshUpper;
447  const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
448  >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
449  /* Add 3 as specified in register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */
450  regIshUpper = SL_MIN(steadyStateRegIsh + 3, upperMax);
451  regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
452  return regIshUpper;
453 }
454 #endif
455 
456 
457 /***************************************************************************/
468 static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch)
469 {
470  uint32_t sel;
471  uint32_t ret = 0;
472 
473  switch (lfClkBranch)
474  {
475  case cmuClock_LFA:
476  case cmuClock_LFB:
477 #if defined( _CMU_LFCCLKEN0_MASK )
478  case cmuClock_LFC:
479 #endif
480 #if defined( _CMU_LFECLKSEL_MASK )
481  case cmuClock_LFE:
482 #endif
483  break;
484 
485  default:
486  EFM_ASSERT(0);
487  break;
488  }
489 
490  sel = CMU_ClockSelectGet(lfClkBranch);
491 
492  /* Get clock select field */
493  switch (lfClkBranch)
494  {
495  case cmuClock_LFA:
496 #if defined( _CMU_LFCLKSEL_MASK )
497  sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
498 #elif defined( _CMU_LFACLKSEL_MASK )
499  sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
500 #else
501  EFM_ASSERT(0);
502 #endif
503  break;
504 
505  case cmuClock_LFB:
506 #if defined( _CMU_LFCLKSEL_MASK )
507  sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
508 #elif defined( _CMU_LFBCLKSEL_MASK )
509  sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
510 #else
511  EFM_ASSERT(0);
512 #endif
513  break;
514 
515 #if defined( _CMU_LFCCLKEN0_MASK )
516  case cmuClock_LFC:
517  sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
518  break;
519 #endif
520 
521 #if defined( _CMU_LFECLKSEL_MASK )
522  case cmuClock_LFE:
523  sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
524  break;
525 #endif
526 
527  default:
528  EFM_ASSERT(0);
529  break;
530  }
531 
532  /* Get clock frequency */
533 #if defined( _CMU_LFCLKSEL_MASK )
534  switch (sel)
535  {
536  case _CMU_LFCLKSEL_LFA_LFRCO:
537  ret = SystemLFRCOClockGet();
538  break;
539 
540  case _CMU_LFCLKSEL_LFA_LFXO:
541  ret = SystemLFXOClockGet();
542  break;
543 
544 #if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
545  case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
546 #if defined( CMU_MAX_FREQ_HFLE )
547  ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1));
548 #else
549  ret = SystemCoreClockGet() / 2U;
550 #endif
551  break;
552 #endif
553 
554  case _CMU_LFCLKSEL_LFA_DISABLED:
555  ret = 0;
556 #if defined( CMU_LFCLKSEL_LFAE )
557  /* Check LF Extended bit setting for LFA or LFB ULFRCO clock */
558  if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB))
559  {
560  if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA
561  ? _CMU_LFCLKSEL_LFAE_SHIFT
562  : _CMU_LFCLKSEL_LFBE_SHIFT))
563  {
564  ret = SystemULFRCOClockGet();
565  }
566  }
567 #endif
568  break;
569 
570  default:
571  EFM_ASSERT(0);
572  ret = 0U;
573  break;
574  }
575 #endif /* _CMU_LFCLKSEL_MASK */
576 
577 #if defined( _CMU_LFACLKSEL_MASK )
578  switch (sel)
579  {
580  case _CMU_LFACLKSEL_LFA_LFRCO:
581  ret = SystemLFRCOClockGet();
582  break;
583 
584  case _CMU_LFACLKSEL_LFA_LFXO:
585  ret = SystemLFXOClockGet();
586  break;
587 
588  case _CMU_LFACLKSEL_LFA_ULFRCO:
589  ret = SystemULFRCOClockGet();
590  break;
591 
592 #if defined( CMU_LFACLKSEL_LFA_PLFRCO )
593  case _CMU_LFACLKSEL_LFA_PLFRCO:
594  ret = SystemLFRCOClockGet();
595  break;
596 #endif
597 
598 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
599  case _CMU_LFACLKSEL_LFA_HFCLKLE:
600  ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
601  == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
602  ? SystemCoreClockGet() / 4U
603  : SystemCoreClockGet() / 2U;
604  break;
605 #elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
606  case _CMU_LFBCLKSEL_LFB_HFCLKLE:
607  ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
608  == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
609  ? SystemCoreClockGet() / 4U
610  : SystemCoreClockGet() / 2U;
611  break;
612 #endif
613 
614  case _CMU_LFACLKSEL_LFA_DISABLED:
615  ret = 0;
616  break;
617  }
618 #endif
619 
620  return ret;
621 }
622 
623 
624 /***************************************************************************/
632 __STATIC_INLINE void syncReg(uint32_t mask)
633 {
634  /* Avoid deadlock if modifying the same register twice when freeze mode is */
635  /* activated. */
636  if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
637  return;
638 
639  /* Wait for any pending previous write operation to have been completed */
640  /* in low frequency domain */
641  while (CMU->SYNCBUSY & mask)
642  {
643  }
644 }
645 
646 
647 #if defined(USB_PRESENT)
648 /***************************************************************************/
655 static uint32_t usbCClkGet(void)
656 {
657  uint32_t ret;
658  CMU_Select_TypeDef clk;
659 
660  /* Get selected clock source */
661  clk = CMU_ClockSelectGet(cmuClock_USBC);
662 
663  switch(clk)
664  {
665  case cmuSelect_LFXO:
666  ret = SystemLFXOClockGet();
667  break;
668  case cmuSelect_LFRCO:
669  ret = SystemLFRCOClockGet();
670  break;
671  case cmuSelect_HFCLK:
672  ret = SystemHFClockGet();
673  break;
674  default:
675  /* Clock is not enabled */
676  ret = 0;
677  break;
678  }
679  return ret;
680 }
681 #endif
682 
683 
686 /*******************************************************************************
687  ************************** GLOBAL FUNCTIONS *******************************
688  ******************************************************************************/
689 
690 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
691 /***************************************************************************/
698 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
699 {
700  return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL
701  & _CMU_AUXHFRCOCTRL_BAND_MASK)
702  >> _CMU_AUXHFRCOCTRL_BAND_SHIFT);
703 }
704 #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
705 
706 
707 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
708 /***************************************************************************/
716 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
717 {
718  uint32_t tuning;
719 
720  /* Read tuning value from calibration table */
721  switch (band)
722  {
723  case cmuAUXHFRCOBand_1MHz:
724  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
725  >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
726  break;
727 
728  case cmuAUXHFRCOBand_7MHz:
729  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)
730  >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
731  break;
732 
733  case cmuAUXHFRCOBand_11MHz:
734  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)
735  >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
736  break;
737 
738  case cmuAUXHFRCOBand_14MHz:
739  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)
740  >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
741  break;
742 
743  case cmuAUXHFRCOBand_21MHz:
744  tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)
745  >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
746  break;
747 
748 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
749  case cmuAUXHFRCOBand_28MHz:
750  tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
751  >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
752  break;
753 #endif
754 
755  default:
756  EFM_ASSERT(0);
757  return;
758  }
759 
760  /* Set band/tuning */
761  CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
762  ~(_CMU_AUXHFRCOCTRL_BAND_MASK
763  | _CMU_AUXHFRCOCTRL_TUNING_MASK))
764  | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
765  | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
766 
767 }
768 #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
769 
770 
771 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
772 /**************************************************************************/
782 static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
783 {
784  switch (freq)
785  {
786  /* 1, 2 and 4MHz share the same calibration word */
787  case cmuAUXHFRCOFreq_1M0Hz:
788  case cmuAUXHFRCOFreq_2M0Hz:
789  case cmuAUXHFRCOFreq_4M0Hz:
790  return DEVINFO->AUXHFRCOCAL0;
791 
792  case cmuAUXHFRCOFreq_7M0Hz:
793  return DEVINFO->AUXHFRCOCAL3;
794 
795  case cmuAUXHFRCOFreq_13M0Hz:
796  return DEVINFO->AUXHFRCOCAL6;
797 
798  case cmuAUXHFRCOFreq_16M0Hz:
799  return DEVINFO->AUXHFRCOCAL7;
800 
801  case cmuAUXHFRCOFreq_19M0Hz:
802  return DEVINFO->AUXHFRCOCAL8;
803 
804  case cmuAUXHFRCOFreq_26M0Hz:
805  return DEVINFO->AUXHFRCOCAL10;
806 
807  case cmuAUXHFRCOFreq_32M0Hz:
808  return DEVINFO->AUXHFRCOCAL11;
809 
810  case cmuAUXHFRCOFreq_38M0Hz:
811  return DEVINFO->AUXHFRCOCAL12;
812 
813  default: /* cmuAUXHFRCOFreq_UserDefined */
814  return 0;
815  }
816 }
817 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
818 
819 
820 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
821 /***************************************************************************/
828 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void)
829 {
830  return auxHfrcoFreq;
831 }
832 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
833 
834 
835 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
836 /***************************************************************************/
843 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
844 {
845  uint32_t freqCal;
846 
847  /* Get DEVINFO index, set global auxHfrcoFreq */
848  freqCal = CMU_AUXHFRCODevinfoGet(setFreq);
849  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
850  auxHfrcoFreq = setFreq;
851 
852  /* Wait for any previous sync to complete, and then set calibration data
853  for the selected frequency. */
854  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));
855 
856  /* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */
857  switch(setFreq)
858  {
859  case cmuAUXHFRCOFreq_1M0Hz:
860  freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
861  | CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
862  break;
863 
864  case cmuAUXHFRCOFreq_2M0Hz:
865  freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
866  | CMU_AUXHFRCOCTRL_CLKDIV_DIV2;
867  break;
868 
869  case cmuAUXHFRCOFreq_4M0Hz:
870  freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
871  | CMU_AUXHFRCOCTRL_CLKDIV_DIV1;
872  break;
873 
874  default:
875  break;
876  }
877  CMU->AUXHFRCOCTRL = freqCal;
878 }
879 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
880 
881 
882 /***************************************************************************/
904 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef ref)
905 {
906  EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
907 
908  /* Set reference clock source */
909  switch (ref)
910  {
911  case cmuOsc_LFXO:
912  CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
913  break;
914 
915  case cmuOsc_LFRCO:
916  CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
917  break;
918 
919  case cmuOsc_HFXO:
920  CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
921  break;
922 
923  case cmuOsc_HFRCO:
924  CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
925  break;
926 
927  case cmuOsc_AUXHFRCO:
928  CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
929  break;
930 
931  default:
932  EFM_ASSERT(0);
933  return 0;
934  }
935 
936  /* Set top value */
937  CMU->CALCNT = HFCycles;
938 
939  /* Start calibration */
940  CMU->CMD = CMU_CMD_CALSTART;
941 
942 #if defined( CMU_STATUS_CALRDY )
943  /* Wait until calibration completes */
944  while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
945  {
946  }
947 #else
948  /* Wait until calibration completes */
949  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
950  {
951  }
952 #endif
953 
954  return CMU->CALCNT;
955 }
956 
957 
958 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
959 /***************************************************************************/
985 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
986  CMU_Osc_TypeDef upSel)
987 {
988  /* Keep untouched configuration settings */
989  uint32_t calCtrl = CMU->CALCTRL
990  & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);
991 
992  /* 20 bits of precision to calibration count register */
993  EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
994 
995  /* Set down counting clock source - down counter */
996  switch (downSel)
997  {
998  case cmuOsc_LFXO:
999  calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
1000  break;
1001 
1002  case cmuOsc_LFRCO:
1003  calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;
1004  break;
1005 
1006  case cmuOsc_HFXO:
1007  calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;
1008  break;
1009 
1010  case cmuOsc_HFRCO:
1011  calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;
1012  break;
1013 
1014  case cmuOsc_AUXHFRCO:
1015  calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
1016  break;
1017 
1018  default:
1019  EFM_ASSERT(0);
1020  break;
1021  }
1022 
1023  /* Set top value to be counted down by the downSel clock */
1024  CMU->CALCNT = downCycles;
1025 
1026  /* Set reference clock source - up counter */
1027  switch (upSel)
1028  {
1029  case cmuOsc_LFXO:
1030  calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
1031  break;
1032 
1033  case cmuOsc_LFRCO:
1034  calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;
1035  break;
1036 
1037  case cmuOsc_HFXO:
1038  calCtrl |= CMU_CALCTRL_UPSEL_HFXO;
1039  break;
1040 
1041  case cmuOsc_HFRCO:
1042  calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;
1043  break;
1044 
1045  case cmuOsc_AUXHFRCO:
1046  calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
1047  break;
1048 
1049  default:
1050  EFM_ASSERT(0);
1051  break;
1052  }
1053 
1054  CMU->CALCTRL = calCtrl;
1055 }
1056 #endif
1057 
1058 
1059 /***************************************************************************/
1072 uint32_t CMU_CalibrateCountGet(void)
1073 {
1074  /* Wait until calibration completes, UNLESS continuous calibration mode is */
1075  /* active */
1076 #if defined( CMU_CALCTRL_CONT )
1077  if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))
1078  {
1079 #if defined( CMU_STATUS_CALRDY )
1080  /* Wait until calibration completes */
1081  while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
1082  {
1083  }
1084 #else
1085  /* Wait until calibration completes */
1086  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
1087  {
1088  }
1089 #endif
1090  }
1091 #else
1092  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
1093  {
1094  }
1095 #endif
1096  return CMU->CALCNT;
1097 }
1098 
1099 
1100 /***************************************************************************/
1112 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
1113 {
1114 #if defined( _SILICON_LABS_32B_SERIES_1 )
1115  return 1 + (uint32_t)CMU_ClockPrescGet(clock);
1116 
1117 #elif defined( _SILICON_LABS_32B_SERIES_0 )
1118  uint32_t divReg;
1119  CMU_ClkDiv_TypeDef ret;
1120 
1121  /* Get divisor reg id */
1122  divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1123 
1124  switch (divReg)
1125  {
1126 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1127  case CMU_HFCLKDIV_REG:
1128  ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1129  >> _CMU_CTRL_HFCLKDIV_SHIFT);
1130  break;
1131 #endif
1132 
1133  case CMU_HFPERCLKDIV_REG:
1134  ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV
1135  & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1136  >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
1137  ret = CMU_Log2ToDiv(ret);
1138  break;
1139 
1140  case CMU_HFCORECLKDIV_REG:
1141  ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV
1142  & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
1143  >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
1144  ret = CMU_Log2ToDiv(ret);
1145  break;
1146 
1147  case CMU_LFAPRESC0_REG:
1148  switch (clock)
1149  {
1150  case cmuClock_RTC:
1151  ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
1152  >> _CMU_LFAPRESC0_RTC_SHIFT);
1153  ret = CMU_Log2ToDiv(ret);
1154  break;
1155 
1156 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1157  case cmuClock_LETIMER0:
1158  ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1159  >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
1160  ret = CMU_Log2ToDiv(ret);
1161  break;
1162 #endif
1163 
1164 #if defined(_CMU_LFAPRESC0_LCD_MASK)
1165  case cmuClock_LCDpre:
1166  ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1167  >> _CMU_LFAPRESC0_LCD_SHIFT)
1168  + CMU_DivToLog2(cmuClkDiv_16));
1169  ret = CMU_Log2ToDiv(ret);
1170  break;
1171 #endif
1172 
1173 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
1174  case cmuClock_LESENSE:
1175  ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1176  >> _CMU_LFAPRESC0_LESENSE_SHIFT);
1177  ret = CMU_Log2ToDiv(ret);
1178  break;
1179 #endif
1180 
1181  default:
1182  EFM_ASSERT(0);
1183  ret = cmuClkDiv_1;
1184  break;
1185  }
1186  break;
1187 
1188  case CMU_LFBPRESC0_REG:
1189  switch (clock)
1190  {
1191 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1192  case cmuClock_LEUART0:
1193  ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1194  >> _CMU_LFBPRESC0_LEUART0_SHIFT);
1195  ret = CMU_Log2ToDiv(ret);
1196  break;
1197 #endif
1198 
1199 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1200  case cmuClock_LEUART1:
1201  ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1202  >> _CMU_LFBPRESC0_LEUART1_SHIFT);
1203  ret = CMU_Log2ToDiv(ret);
1204  break;
1205 #endif
1206 
1207  default:
1208  EFM_ASSERT(0);
1209  ret = cmuClkDiv_1;
1210  break;
1211  }
1212  break;
1213 
1214  default:
1215  EFM_ASSERT(0);
1216  ret = cmuClkDiv_1;
1217  break;
1218  }
1219 
1220  return ret;
1221 #endif
1222 }
1223 
1224 
1225 /***************************************************************************/
1244 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
1245 {
1246 #if defined( _SILICON_LABS_32B_SERIES_1 )
1247  CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
1248 
1249 #elif defined( _SILICON_LABS_32B_SERIES_0 )
1250  uint32_t freq;
1251  uint32_t divReg;
1252 
1253  /* Get divisor reg id */
1254  divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1255 
1256  switch (divReg)
1257  {
1258 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1259  case CMU_HFCLKDIV_REG:
1260  EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
1261 
1262  /* Configure worst case wait states for flash access before setting divisor */
1263  flashWaitStateMax();
1264 
1265  /* Set divider */
1266  CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
1267  | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
1268 
1269  /* Update CMSIS core clock variable */
1270  /* (The function will update the global variable) */
1271  freq = SystemCoreClockGet();
1272 
1273  /* Optimize flash access wait state setting for current core clk */
1274  flashWaitStateControl(freq);
1275  break;
1276 #endif
1277 
1278  case CMU_HFPERCLKDIV_REG:
1279  EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
1280  /* Convert to correct scale */
1281  div = CMU_DivToLog2(div);
1282  CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1283  | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
1284  break;
1285 
1286  case CMU_HFCORECLKDIV_REG:
1287  EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
1288 
1289  /* Configure worst case wait states for flash access before setting divisor */
1290  flashWaitStateMax();
1291 
1292 #if defined( CMU_MAX_FREQ_HFLE )
1293  setHfLeConfig(SystemHFClockGet() / div, CMU_MAX_FREQ_HFLE);
1294 #endif
1295 
1296  /* Convert to correct scale */
1297  div = CMU_DivToLog2(div);
1298 
1299  CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
1300  & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
1301  | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
1302 
1303  /* Update CMSIS core clock variable */
1304  /* (The function will update the global variable) */
1305  freq = SystemCoreClockGet();
1306 
1307  /* Optimize flash access wait state setting for current core clk */
1308  flashWaitStateControl(freq);
1309  break;
1310 
1311  case CMU_LFAPRESC0_REG:
1312  switch (clock)
1313  {
1314  case cmuClock_RTC:
1315  EFM_ASSERT(div <= cmuClkDiv_32768);
1316 
1317  /* LF register about to be modified require sync. busy check */
1318  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1319 
1320  /* Convert to correct scale */
1321  div = CMU_DivToLog2(div);
1322 
1323  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
1324  | (div << _CMU_LFAPRESC0_RTC_SHIFT);
1325  break;
1326 
1327 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1328  case cmuClock_LETIMER0:
1329  EFM_ASSERT(div <= cmuClkDiv_32768);
1330 
1331  /* LF register about to be modified require sync. busy check */
1332  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1333 
1334  /* Convert to correct scale */
1335  div = CMU_DivToLog2(div);
1336 
1337  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
1338  | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
1339  break;
1340 #endif
1341 
1342 #if defined(LCD_PRESENT)
1343  case cmuClock_LCDpre:
1344  EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
1345 
1346  /* LF register about to be modified require sync. busy check */
1347  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1348 
1349  /* Convert to correct scale */
1350  div = CMU_DivToLog2(div);
1351 
1352  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
1353  | ((div - CMU_DivToLog2(cmuClkDiv_16))
1354  << _CMU_LFAPRESC0_LCD_SHIFT);
1355  break;
1356 #endif /* defined(LCD_PRESENT) */
1357 
1358 #if defined(LESENSE_PRESENT)
1359  case cmuClock_LESENSE:
1360  EFM_ASSERT(div <= cmuClkDiv_8);
1361 
1362  /* LF register about to be modified require sync. busy check */
1363  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1364 
1365  /* Convert to correct scale */
1366  div = CMU_DivToLog2(div);
1367 
1368  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
1369  | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
1370  break;
1371 #endif /* defined(LESENSE_PRESENT) */
1372 
1373  default:
1374  EFM_ASSERT(0);
1375  break;
1376  }
1377  break;
1378 
1379  case CMU_LFBPRESC0_REG:
1380  switch (clock)
1381  {
1382 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1383  case cmuClock_LEUART0:
1384  EFM_ASSERT(div <= cmuClkDiv_8);
1385 
1386  /* LF register about to be modified require sync. busy check */
1387  syncReg(CMU_SYNCBUSY_LFBPRESC0);
1388 
1389  /* Convert to correct scale */
1390  div = CMU_DivToLog2(div);
1391 
1392  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
1393  | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
1394  break;
1395 #endif
1396 
1397 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1398  case cmuClock_LEUART1:
1399  EFM_ASSERT(div <= cmuClkDiv_8);
1400 
1401  /* LF register about to be modified require sync. busy check */
1402  syncReg(CMU_SYNCBUSY_LFBPRESC0);
1403 
1404  /* Convert to correct scale */
1405  div = CMU_DivToLog2(div);
1406 
1407  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
1408  | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
1409  break;
1410 #endif
1411 
1412  default:
1413  EFM_ASSERT(0);
1414  break;
1415  }
1416  break;
1417 
1418  default:
1419  EFM_ASSERT(0);
1420  break;
1421  }
1422 #endif
1423 }
1424 
1425 
1426 /***************************************************************************/
1453 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
1454 {
1455  volatile uint32_t *reg;
1456  uint32_t bit;
1457  uint32_t sync = 0;
1458 
1459  /* Identify enable register */
1460  switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
1461  {
1462 #if defined( _CMU_CTRL_HFPERCLKEN_MASK )
1463  case CMU_CTRL_EN_REG:
1464  reg = &CMU->CTRL;
1465  break;
1466 #endif
1467 
1468 #if defined( _CMU_HFCORECLKEN0_MASK )
1469  case CMU_HFCORECLKEN0_EN_REG:
1470  reg = &CMU->HFCORECLKEN0;
1471 #if defined( CMU_MAX_FREQ_HFLE )
1472  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
1473 #endif
1474  break;
1475 #endif
1476 
1477 #if defined( _CMU_HFBUSCLKEN0_MASK )
1478  case CMU_HFBUSCLKEN0_EN_REG:
1479  reg = &CMU->HFBUSCLKEN0;
1480  break;
1481 #endif
1482 
1483 #if defined( _CMU_HFPERCLKDIV_MASK )
1484  case CMU_HFPERCLKDIV_EN_REG:
1485  reg = &CMU->HFPERCLKDIV;
1486  break;
1487 #endif
1488 
1489  case CMU_HFPERCLKEN0_EN_REG:
1490  reg = &CMU->HFPERCLKEN0;
1491  break;
1492 
1493  case CMU_LFACLKEN0_EN_REG:
1494  reg = &CMU->LFACLKEN0;
1495  sync = CMU_SYNCBUSY_LFACLKEN0;
1496  break;
1497 
1498  case CMU_LFBCLKEN0_EN_REG:
1499  reg = &CMU->LFBCLKEN0;
1500  sync = CMU_SYNCBUSY_LFBCLKEN0;
1501  break;
1502 
1503 #if defined( _CMU_LFCCLKEN0_MASK )
1504  case CMU_LFCCLKEN0_EN_REG:
1505  reg = &CMU->LFCCLKEN0;
1506  sync = CMU_SYNCBUSY_LFCCLKEN0;
1507  break;
1508 #endif
1509 
1510 #if defined( _CMU_LFECLKEN0_MASK )
1511  case CMU_LFECLKEN0_EN_REG:
1512  reg = &CMU->LFECLKEN0;
1513  sync = CMU_SYNCBUSY_LFECLKEN0;
1514  break;
1515 #endif
1516 
1517  case CMU_PCNT_EN_REG:
1518  reg = &CMU->PCNTCTRL;
1519  break;
1520 
1521  default: /* Cannot enable/disable clock point */
1522  EFM_ASSERT(0);
1523  return;
1524  }
1525 
1526  /* Get bit position used to enable/disable */
1527  bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
1528 
1529  /* LF synchronization required? */
1530  if (sync)
1531  {
1532  syncReg(sync);
1533  }
1534 
1535  /* Set/clear bit as requested */
1536  BUS_RegBitWrite(reg, bit, enable);
1537 }
1538 
1539 
1540 /***************************************************************************/
1550 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
1551 {
1552  uint32_t ret;
1553 
1554  switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
1555  {
1556  case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1557  ret = SystemHFClockGet();
1558  break;
1559 
1560  case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1561  ret = SystemHFClockGet();
1562  /* Calculate frequency after HFPER divider. */
1563 #if defined( _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK )
1564  ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1565  >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
1566 #endif
1567 #if defined( _CMU_HFPERPRESC_PRESC_MASK )
1568  ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
1569  >> _CMU_HFPERPRESC_PRESC_SHIFT);
1570 #endif
1571  break;
1572 
1573 #if defined( _SILICON_LABS_32B_SERIES_1 )
1574 #if defined( CRYPTO_PRESENT ) \
1575  || defined( LDMA_PRESENT ) \
1576  || defined( GPCRC_PRESENT ) \
1577  || defined( PRS_PRESENT ) \
1578  || defined( GPIO_PRESENT )
1579  case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1580  ret = SystemHFClockGet();
1581  break;
1582 #endif
1583 
1584  case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1585  ret = SystemHFClockGet();
1586  ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
1587  >> _CMU_HFCOREPRESC_PRESC_SHIFT);
1588  break;
1589 
1590  case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1591  ret = SystemHFClockGet();
1592  ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
1593  >> _CMU_HFEXPPRESC_PRESC_SHIFT);
1594  break;
1595 #endif
1596 
1597 #if defined( _SILICON_LABS_32B_SERIES_0 )
1598 #if defined( AES_PRESENT ) \
1599  || defined( DMA_PRESENT ) \
1600  || defined( EBI_PRESENT ) \
1601  || defined( USB_PRESENT )
1602  case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1603  {
1604  ret = SystemCoreClockGet();
1605  } break;
1606 #endif
1607 #endif
1608 
1609  case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1610  ret = lfClkGet(cmuClock_LFA);
1611  break;
1612 
1613 #if defined( _CMU_LFACLKEN0_RTC_MASK )
1614  case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1615  ret = lfClkGet(cmuClock_LFA);
1616  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
1617  >> _CMU_LFAPRESC0_RTC_SHIFT;
1618  break;
1619 #endif
1620 
1621 #if defined( _CMU_LFECLKEN0_RTCC_MASK )
1622  case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1623  ret = lfClkGet(cmuClock_LFE);
1624  break;
1625 #endif
1626 
1627 #if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
1628  case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1629  ret = lfClkGet(cmuClock_LFA);
1630 #if defined( _SILICON_LABS_32B_SERIES_0 )
1631  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1632  >> _CMU_LFAPRESC0_LETIMER0_SHIFT;
1633 #elif defined( _SILICON_LABS_32B_SERIES_1 )
1634  ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1635  >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
1636 #endif
1637  break;
1638 #endif
1639 
1640 #if defined( _CMU_LFACLKEN0_LCD_MASK )
1641  case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1642  ret = lfClkGet(cmuClock_LFA);
1643  ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1644  >> _CMU_LFAPRESC0_LCD_SHIFT)
1645  + CMU_DivToLog2(cmuClkDiv_16);
1646  break;
1647 
1648  case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1649  ret = lfClkGet(cmuClock_LFA);
1650  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1651  >> _CMU_LFAPRESC0_LCD_SHIFT;
1652  ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
1653  >> _CMU_LCDCTRL_FDIV_SHIFT);
1654  break;
1655 #endif
1656 
1657 #if defined( _CMU_LFACLKEN0_LESENSE_MASK )
1658  case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1659  ret = lfClkGet(cmuClock_LFA);
1660  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1661  >> _CMU_LFAPRESC0_LESENSE_SHIFT;
1662  break;
1663 #endif
1664 
1665  case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1666  ret = lfClkGet(cmuClock_LFB);
1667  break;
1668 
1669 #if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
1670  case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1671  ret = lfClkGet(cmuClock_LFB);
1672 #if defined( _SILICON_LABS_32B_SERIES_0 )
1673  ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1674  >> _CMU_LFBPRESC0_LEUART0_SHIFT;
1675 #elif defined( _SILICON_LABS_32B_SERIES_1 )
1676  ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1677  >> _CMU_LFBPRESC0_LEUART0_SHIFT);
1678 #endif
1679  break;
1680 #endif
1681 
1682 #if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
1683  case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1684  ret = lfClkGet(cmuClock_LFB);
1685 #if defined( _SILICON_LABS_32B_SERIES_0 )
1686  ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1687  >> _CMU_LFBPRESC0_LEUART1_SHIFT;
1688 #elif defined( _SILICON_LABS_32B_SERIES_1 )
1689  ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1690  >> _CMU_LFBPRESC0_LEUART1_SHIFT);
1691 #endif
1692  break;
1693 #endif
1694 
1695 #if defined( _CMU_LFBCLKEN0_CSEN_MASK )
1696  case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1697  ret = lfClkGet(cmuClock_LFB);
1698  ret /= CMU_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK)
1699  >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4);
1700  break;
1701 #endif
1702 
1703 #if defined( _SILICON_LABS_32B_SERIES_1 )
1704  case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1705  ret = lfClkGet(cmuClock_LFE);
1706  break;
1707 #endif
1708 
1709  case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1710  ret = dbgClkGet();
1711  break;
1712 
1713  case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1714  ret = auxClkGet();
1715  break;
1716 
1717 #if defined(USB_PRESENT)
1718  case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1719  ret = usbCClkGet();
1720  break;
1721 #endif
1722 
1723  default:
1724  EFM_ASSERT(0);
1725  ret = 0;
1726  break;
1727  }
1728 
1729  return ret;
1730 }
1731 
1732 
1733 #if defined( _SILICON_LABS_32B_SERIES_1 )
1734 /***************************************************************************/
1746 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
1747 {
1748  uint32_t prescReg;
1749  uint32_t ret;
1750 
1751  /* Get prescaler register id. */
1752  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1753 
1754  switch (prescReg)
1755  {
1756  case CMU_HFPRESC_REG:
1757  ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
1758  >> _CMU_HFPRESC_PRESC_SHIFT);
1759  break;
1760 
1761  case CMU_HFEXPPRESC_REG:
1762  ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
1763  >> _CMU_HFEXPPRESC_PRESC_SHIFT);
1764  break;
1765 
1766  case CMU_HFCLKLEPRESC_REG:
1767  ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
1768  >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
1769  break;
1770 
1771  case CMU_HFPERPRESC_REG:
1772  ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
1773  >> _CMU_HFPERPRESC_PRESC_SHIFT);
1774  break;
1775 
1776  case CMU_HFCOREPRESC_REG:
1777  ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
1778  >> _CMU_HFCOREPRESC_PRESC_SHIFT);
1779  break;
1780 
1781  case CMU_LFAPRESC0_REG:
1782  switch (clock)
1783  {
1784 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
1785  case cmuClock_LETIMER0:
1786  ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1787  >> _CMU_LFAPRESC0_LETIMER0_SHIFT));
1788  /* Convert the exponent to prescaler value. */
1789  ret = CMU_Log2ToDiv(ret) - 1U;
1790  break;
1791 #endif
1792 
1793 #if defined( _CMU_LFAPRESC0_LESENSE_MASK )
1794  case cmuClock_LESENSE:
1795  ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1796  >> _CMU_LFAPRESC0_LESENSE_SHIFT));
1797  /* Convert the exponent to prescaler value. */
1798  ret = CMU_Log2ToDiv(ret) - 1U;
1799  break;
1800 #endif
1801 
1802  default:
1803  EFM_ASSERT(0);
1804  ret = 0U;
1805  break;
1806  }
1807  break;
1808 
1809  case CMU_LFBPRESC0_REG:
1810  switch (clock)
1811  {
1812 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
1813  case cmuClock_LEUART0:
1814  ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1815  >> _CMU_LFBPRESC0_LEUART0_SHIFT));
1816  /* Convert the exponent to prescaler value. */
1817  ret = CMU_Log2ToDiv(ret) - 1U;
1818  break;
1819 #endif
1820 
1821 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
1822  case cmuClock_LEUART1:
1823  ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1824  >> _CMU_LFBPRESC0_LEUART1_SHIFT));
1825  /* Convert the exponent to prescaler value. */
1826  ret = CMU_Log2ToDiv(ret) - 1U;
1827  break;
1828 #endif
1829 
1830 #if defined( _CMU_LFBPRESC0_CSEN_MASK )
1831  case cmuClock_CSEN_LF:
1832  ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK)
1833  >> _CMU_LFBPRESC0_CSEN_SHIFT));
1834  /* Convert the exponent to prescaler value. */
1835  ret = CMU_Log2ToDiv(ret + 4) - 1U;
1836  break;
1837 #endif
1838 
1839  default:
1840  EFM_ASSERT(0);
1841  ret = 0U;
1842  break;
1843  }
1844  break;
1845 
1846  case CMU_LFEPRESC0_REG:
1847  switch (clock)
1848  {
1849 #if defined( RTCC_PRESENT )
1850  case cmuClock_RTCC:
1851  /* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */
1852  /* allowed value. Convert the exponent to prescaler value. */
1853  ret = _CMU_LFEPRESC0_RTCC_DIV1;
1854  break;
1855 
1856  default:
1857  EFM_ASSERT(0);
1858  ret = 0U;
1859  break;
1860 #endif
1861  }
1862  break;
1863 
1864  default:
1865  EFM_ASSERT(0);
1866  ret = 0U;
1867  break;
1868  }
1869 
1870  return ret;
1871 }
1872 #endif
1873 
1874 
1875 #if defined( _SILICON_LABS_32B_SERIES_1 )
1876 /***************************************************************************/
1894 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
1895 {
1896  uint32_t freq;
1897  uint32_t prescReg;
1898 
1899  /* Get divisor reg id */
1900  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1901 
1902  switch (prescReg)
1903  {
1904  case CMU_HFPRESC_REG:
1905  EFM_ASSERT(presc < 32U);
1906 
1907  /* Configure worst case wait-states for flash and HFLE. */
1908  flashWaitStateMax();
1909  setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
1910 
1911  CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
1912  | (presc << _CMU_HFPRESC_PRESC_SHIFT);
1913 
1914  /* Update CMSIS core clock variable (this function updates the global variable).
1915  Optimize flash and HFLE wait states. */
1916  freq = SystemCoreClockGet();
1917  flashWaitStateControl(freq);
1918  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE) ,CMU_MAX_FREQ_HFLE);
1919  break;
1920 
1921  case CMU_HFEXPPRESC_REG:
1922  EFM_ASSERT(presc < 32U);
1923 
1924  CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
1925  | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
1926  break;
1927 
1928  case CMU_HFCLKLEPRESC_REG:
1929  EFM_ASSERT(presc < 2U);
1930 
1931  /* Specifies the clock divider for HFCLKLE. When running at frequencies
1932  * higher than 32 MHz, this must be set to DIV4. */
1933  CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
1934  | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
1935  break;
1936 
1937  case CMU_HFPERPRESC_REG:
1938  EFM_ASSERT(presc < 512U);
1939 
1940  CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
1941  | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
1942  break;
1943 
1944  case CMU_HFCOREPRESC_REG:
1945  EFM_ASSERT(presc < 512U);
1946 
1947  /* Configure worst case wait-states for flash and HFLE. */
1948  flashWaitStateMax();
1949  setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
1950 
1951  CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
1952  | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
1953 
1954  /* Update CMSIS core clock variable (this function updates the global variable).
1955  Optimize flash and HFLE wait states. */
1956  freq = SystemCoreClockGet();
1957  flashWaitStateControl(freq);
1958  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE) ,CMU_MAX_FREQ_HFLE);
1959  break;
1960 
1961  case CMU_LFAPRESC0_REG:
1962  switch (clock)
1963  {
1964 #if defined( RTC_PRESENT )
1965  case cmuClock_RTC:
1966  EFM_ASSERT(presc <= 32768U);
1967 
1968  /* Convert prescaler value to DIV exponent scale. */
1969  presc = CMU_PrescToLog2(presc);
1970 
1971  /* LF register about to be modified require sync. Busy check. */
1972  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1973 
1974  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
1975  | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
1976  break;
1977 #endif
1978 
1979 #if defined( RTCC_PRESENT )
1980  case cmuClock_RTCC:
1981 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
1982  /* DIV1 is the only accepted value. */
1983  EFM_ASSERT(presc <= 0U);
1984 
1985  /* LF register about to be modified require sync. Busy check.. */
1986  syncReg(CMU_SYNCBUSY_LFEPRESC0);
1987 
1988  CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
1989  | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
1990 #else
1991  EFM_ASSERT(presc <= 32768U);
1992 
1993  /* Convert prescaler value to DIV exponent scale. */
1994  presc = CMU_PrescToLog2(presc);
1995 
1996  /* LF register about to be modified require sync. Busy check. */
1997  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1998 
1999  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
2000  | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
2001 #endif
2002  break;
2003 #endif
2004 
2005 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
2006  case cmuClock_LETIMER0:
2007  EFM_ASSERT(presc <= 32768U);
2008 
2009  /* Convert prescaler value to DIV exponent scale. */
2010  presc = CMU_PrescToLog2(presc);
2011 
2012  /* LF register about to be modified require sync. Busy check. */
2013  syncReg(CMU_SYNCBUSY_LFAPRESC0);
2014 
2015  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
2016  | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
2017  break;
2018 #endif
2019 
2020 #if defined( _CMU_LFAPRESC0_LESENSE_MASK )
2021  case cmuClock_LESENSE:
2022  EFM_ASSERT(presc <= 8);
2023 
2024  /* Convert prescaler value to DIV exponent scale. */
2025  presc = CMU_PrescToLog2(presc);
2026 
2027  /* LF register about to be modified require sync. Busy check. */
2028  syncReg(CMU_SYNCBUSY_LFAPRESC0);
2029 
2030  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
2031  | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT);
2032  break;
2033 #endif
2034 
2035  default:
2036  EFM_ASSERT(0);
2037  break;
2038  }
2039  break;
2040 
2041  case CMU_LFBPRESC0_REG:
2042  switch (clock)
2043  {
2044 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
2045  case cmuClock_LEUART0:
2046  EFM_ASSERT(presc <= 8U);
2047 
2048  /* Convert prescaler value to DIV exponent scale. */
2049  presc = CMU_PrescToLog2(presc);
2050 
2051  /* LF register about to be modified require sync. Busy check. */
2052  syncReg(CMU_SYNCBUSY_LFBPRESC0);
2053 
2054  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
2055  | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
2056  break;
2057 #endif
2058 
2059 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
2060  case cmuClock_LEUART1:
2061  EFM_ASSERT(presc <= 8U);
2062 
2063  /* Convert prescaler value to DIV exponent scale. */
2064  presc = CMU_PrescToLog2(presc);
2065 
2066  /* LF register about to be modified require sync. Busy check. */
2067  syncReg(CMU_SYNCBUSY_LFBPRESC0);
2068 
2069  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
2070  | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
2071  break;
2072 #endif
2073 
2074 #if defined( _CMU_LFBPRESC0_CSEN_MASK )
2075  case cmuClock_CSEN_LF:
2076  EFM_ASSERT((presc <= 127U) && (presc >= 15U));
2077 
2078  /* Convert prescaler value to DIV exponent scale.
2079  * DIV16 is the lowest supported prescaler. */
2080  presc = CMU_PrescToLog2(presc) - 4;
2081 
2082  /* LF register about to be modified require sync. Busy check. */
2083  syncReg(CMU_SYNCBUSY_LFBPRESC0);
2084 
2085  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK)
2086  | (presc << _CMU_LFBPRESC0_CSEN_SHIFT);
2087  break;
2088 #endif
2089 
2090  default:
2091  EFM_ASSERT(0);
2092  break;
2093  }
2094  break;
2095 
2096  case CMU_LFEPRESC0_REG:
2097  switch (clock)
2098  {
2099 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
2100  case cmuClock_RTCC:
2101  EFM_ASSERT(presc <= 0U);
2102 
2103  /* LF register about to be modified require sync. Busy check. */
2104  syncReg(CMU_SYNCBUSY_LFEPRESC0);
2105 
2106  CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
2107  | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
2108  break;
2109 #endif
2110 
2111  default:
2112  EFM_ASSERT(0);
2113  break;
2114  }
2115  break;
2116 
2117  default:
2118  EFM_ASSERT(0);
2119  break;
2120  }
2121 }
2122 #endif
2123 
2124 
2125 /***************************************************************************/
2146 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
2147 {
2148  CMU_Select_TypeDef ret = cmuSelect_Disabled;
2149  uint32_t selReg;
2150 
2151  selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2152 
2153  switch (selReg)
2154  {
2155  case CMU_HFCLKSEL_REG:
2156 #if defined( _CMU_HFCLKSTATUS_MASK )
2157  switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
2158  {
2159  case CMU_HFCLKSTATUS_SELECTED_LFXO:
2160  ret = cmuSelect_LFXO;
2161  break;
2162 
2163  case CMU_HFCLKSTATUS_SELECTED_LFRCO:
2164  ret = cmuSelect_LFRCO;
2165  break;
2166 
2167  case CMU_HFCLKSTATUS_SELECTED_HFXO:
2168  ret = cmuSelect_HFXO;
2169  break;
2170 
2171  default:
2172  ret = cmuSelect_HFRCO;
2173  break;
2174  }
2175 #else
2176  switch (CMU->STATUS
2177  & (CMU_STATUS_HFRCOSEL
2178  | CMU_STATUS_HFXOSEL
2179  | CMU_STATUS_LFRCOSEL
2180 #if defined( CMU_STATUS_USHFRCODIV2SEL )
2181  | CMU_STATUS_USHFRCODIV2SEL
2182 #endif
2183  | CMU_STATUS_LFXOSEL))
2184  {
2185  case CMU_STATUS_LFXOSEL:
2186  ret = cmuSelect_LFXO;
2187  break;
2188 
2189  case CMU_STATUS_LFRCOSEL:
2190  ret = cmuSelect_LFRCO;
2191  break;
2192 
2193  case CMU_STATUS_HFXOSEL:
2194  ret = cmuSelect_HFXO;
2195  break;
2196 
2197 #if defined( CMU_STATUS_USHFRCODIV2SEL )
2198  case CMU_STATUS_USHFRCODIV2SEL:
2199  ret = cmuSelect_USHFRCODIV2;
2200  break;
2201 #endif
2202 
2203  default:
2204  ret = cmuSelect_HFRCO;
2205  break;
2206  }
2207 #endif
2208  break;
2209 
2210 #if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFACLKSEL_MASK )
2211  case CMU_LFACLKSEL_REG:
2212 #if defined( _CMU_LFCLKSEL_MASK )
2213  switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
2214  {
2215  case CMU_LFCLKSEL_LFA_LFRCO:
2216  ret = cmuSelect_LFRCO;
2217  break;
2218 
2219  case CMU_LFCLKSEL_LFA_LFXO:
2220  ret = cmuSelect_LFXO;
2221  break;
2222 
2223 #if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
2224  case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
2225  ret = cmuSelect_HFCLKLE;
2226  break;
2227 #endif
2228 
2229  default:
2230 #if defined( CMU_LFCLKSEL_LFAE )
2231  if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
2232  {
2233  ret = cmuSelect_ULFRCO;
2234  break;
2235  }
2236 #else
2237  ret = cmuSelect_Disabled;
2238 #endif
2239  break;
2240  }
2241 
2242 #elif defined( _CMU_LFACLKSEL_MASK )
2243  switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
2244  {
2245  case CMU_LFACLKSEL_LFA_LFRCO:
2246  ret = cmuSelect_LFRCO;
2247  break;
2248 
2249  case CMU_LFACLKSEL_LFA_LFXO:
2250  ret = cmuSelect_LFXO;
2251  break;
2252 
2253  case CMU_LFACLKSEL_LFA_ULFRCO:
2254  ret = cmuSelect_ULFRCO;
2255  break;
2256 
2257 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2258  case CMU_LFACLKSEL_LFA_HFCLKLE:
2259  ret = cmuSelect_HFCLKLE;
2260  break;
2261 #endif
2262 
2263 #if defined( CMU_LFACLKSEL_LFA_PLFRCO )
2264  case CMU_LFACLKSEL_LFA_PLFRCO:
2265  ret = cmuSelect_PLFRCO;
2266  break;
2267 #endif
2268 
2269  default:
2270  ret = cmuSelect_Disabled;
2271  break;
2272  }
2273 #endif
2274  break;
2275 #endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */
2276 
2277 #if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFBCLKSEL_MASK )
2278  case CMU_LFBCLKSEL_REG:
2279 #if defined( _CMU_LFCLKSEL_MASK )
2280  switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
2281  {
2282  case CMU_LFCLKSEL_LFB_LFRCO:
2283  ret = cmuSelect_LFRCO;
2284  break;
2285 
2286  case CMU_LFCLKSEL_LFB_LFXO:
2287  ret = cmuSelect_LFXO;
2288  break;
2289 
2290 #if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
2291  case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
2292  ret = cmuSelect_HFCLKLE;
2293  break;
2294 #endif
2295 
2296 #if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
2297  case CMU_LFCLKSEL_LFB_HFCLKLE:
2298  ret = cmuSelect_HFCLKLE;
2299  break;
2300 #endif
2301 
2302  default:
2303 #if defined( CMU_LFCLKSEL_LFBE )
2304  if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
2305  {
2306  ret = cmuSelect_ULFRCO;
2307  break;
2308  }
2309 #else
2310  ret = cmuSelect_Disabled;
2311 #endif
2312  break;
2313  }
2314 
2315 #elif defined( _CMU_LFBCLKSEL_MASK )
2316  switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
2317  {
2318  case CMU_LFBCLKSEL_LFB_LFRCO:
2319  ret = cmuSelect_LFRCO;
2320  break;
2321 
2322  case CMU_LFBCLKSEL_LFB_LFXO:
2323  ret = cmuSelect_LFXO;
2324  break;
2325 
2326  case CMU_LFBCLKSEL_LFB_ULFRCO:
2327  ret = cmuSelect_ULFRCO;
2328  break;
2329 
2330  case CMU_LFBCLKSEL_LFB_HFCLKLE:
2331  ret = cmuSelect_HFCLKLE;
2332  break;
2333 
2334 #if defined( CMU_LFBCLKSEL_LFB_PLFRCO )
2335  case CMU_LFBCLKSEL_LFB_PLFRCO:
2336  ret = cmuSelect_PLFRCO;
2337  break;
2338 #endif
2339 
2340  default:
2341  ret = cmuSelect_Disabled;
2342  break;
2343  }
2344 #endif
2345  break;
2346 #endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */
2347 
2348 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2349  case CMU_LFCCLKSEL_REG:
2350  switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
2351  {
2352  case CMU_LFCLKSEL_LFC_LFRCO:
2353  ret = cmuSelect_LFRCO;
2354  break;
2355 
2356  case CMU_LFCLKSEL_LFC_LFXO:
2357  ret = cmuSelect_LFXO;
2358  break;
2359 
2360  default:
2361  ret = cmuSelect_Disabled;
2362  break;
2363  }
2364  break;
2365 #endif
2366 
2367 #if defined( _CMU_LFECLKSEL_LFE_MASK )
2368  case CMU_LFECLKSEL_REG:
2369  switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
2370  {
2371  case CMU_LFECLKSEL_LFE_LFRCO:
2372  ret = cmuSelect_LFRCO;
2373  break;
2374 
2375  case CMU_LFECLKSEL_LFE_LFXO:
2376  ret = cmuSelect_LFXO;
2377  break;
2378 
2379  case CMU_LFECLKSEL_LFE_ULFRCO:
2380  ret = cmuSelect_ULFRCO;
2381  break;
2382 
2383 #if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
2384  case CMU_LFECLKSEL_LFE_HFCLKLE:
2385  ret = cmuSelect_HFCLKLE;
2386  break;
2387 #endif
2388 
2389 #if defined( CMU_LFECLKSEL_LFE_PLFRCO )
2390  case CMU_LFECLKSEL_LFE_PLFRCO:
2391  ret = cmuSelect_PLFRCO;
2392  break;
2393 #endif
2394 
2395  default:
2396  ret = cmuSelect_Disabled;
2397  break;
2398  }
2399  break;
2400 #endif /* CMU_LFECLKSEL_REG */
2401 
2402  case CMU_DBGCLKSEL_REG:
2403 #if defined( _CMU_DBGCLKSEL_DBG_MASK )
2404  switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
2405  {
2406  case CMU_DBGCLKSEL_DBG_HFCLK:
2407  ret = cmuSelect_HFCLK;
2408  break;
2409 
2410  case CMU_DBGCLKSEL_DBG_AUXHFRCO:
2411  ret = cmuSelect_AUXHFRCO;
2412  break;
2413  }
2414 
2415 #elif defined( _CMU_CTRL_DBGCLK_MASK )
2416  switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
2417  {
2418  case CMU_CTRL_DBGCLK_AUXHFRCO:
2419  ret = cmuSelect_AUXHFRCO;
2420  break;
2421 
2422  case CMU_CTRL_DBGCLK_HFCLK:
2423  ret = cmuSelect_HFCLK;
2424  break;
2425  }
2426 #else
2427  ret = cmuSelect_AUXHFRCO;
2428 #endif
2429  break;
2430 
2431 #if defined( USB_PRESENT )
2432  case CMU_USBCCLKSEL_REG:
2433  switch (CMU->STATUS
2434  & (CMU_STATUS_USBCLFXOSEL
2435 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2436  | CMU_STATUS_USBCHFCLKSEL
2437 #endif
2438 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2439  | CMU_STATUS_USBCUSHFRCOSEL
2440 #endif
2441  | CMU_STATUS_USBCLFRCOSEL))
2442  {
2443 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2444  case CMU_STATUS_USBCHFCLKSEL:
2445  ret = cmuSelect_HFCLK;
2446  break;
2447 #endif
2448 
2449 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2450  case CMU_STATUS_USBCUSHFRCOSEL:
2451  ret = cmuSelect_USHFRCO;
2452  break;
2453 #endif
2454 
2455  case CMU_STATUS_USBCLFXOSEL:
2456  ret = cmuSelect_LFXO;
2457  break;
2458 
2459  case CMU_STATUS_USBCLFRCOSEL:
2460  ret = cmuSelect_LFRCO;
2461  break;
2462 
2463  default:
2464  ret = cmuSelect_Disabled;
2465  break;
2466  }
2467  break;
2468 #endif
2469 
2470  default:
2471  EFM_ASSERT(0);
2472  ret = cmuSelect_Error;
2473  break;
2474  }
2475 
2476  return ret;
2477 }
2478 
2479 
2480 /***************************************************************************/
2521 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
2522 {
2523  uint32_t select = cmuOsc_HFRCO;
2524  CMU_Osc_TypeDef osc = cmuOsc_HFRCO;
2525  uint32_t freq;
2526  uint32_t tmp;
2527  uint32_t selRegId;
2528 #if defined( _SILICON_LABS_32B_SERIES_1 )
2529  volatile uint32_t *selReg = NULL;
2530 #endif
2531 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2532  uint32_t lfExtended = 0;
2533 #endif
2534 
2535 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
2536  uint32_t vScaleFrequency = 0; /* Use default */
2537 
2538  /* Start voltage upscaling before clock is set. */
2539  if (clock == cmuClock_HF)
2540  {
2541  if (ref == cmuSelect_HFXO)
2542  {
2543  vScaleFrequency = SystemHFXOClockGet();
2544  }
2545  else if ((ref == cmuSelect_HFRCO)
2546  && (CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX))
2547  {
2548  vScaleFrequency = CMU_HFRCOBandGet();
2549  }
2550  if (vScaleFrequency != 0)
2551  {
2552  EMU_VScaleEM01ByClock(vScaleFrequency, false);
2553  }
2554  }
2555 #endif
2556 
2557  selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2558 
2559  switch (selRegId)
2560  {
2561  case CMU_HFCLKSEL_REG:
2562  switch (ref)
2563  {
2564  case cmuSelect_LFXO:
2565 #if defined( _SILICON_LABS_32B_SERIES_1 )
2566  select = CMU_HFCLKSEL_HF_LFXO;
2567 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2568  select = CMU_CMD_HFCLKSEL_LFXO;
2569 #endif
2570  osc = cmuOsc_LFXO;
2571  break;
2572 
2573  case cmuSelect_LFRCO:
2574 #if defined( _SILICON_LABS_32B_SERIES_1 )
2575  select = CMU_HFCLKSEL_HF_LFRCO;
2576 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2577  select = CMU_CMD_HFCLKSEL_LFRCO;
2578 #endif
2579  osc = cmuOsc_LFRCO;
2580  break;
2581 
2582  case cmuSelect_HFXO:
2583 #if defined( CMU_HFCLKSEL_HF_HFXO )
2584  select = CMU_HFCLKSEL_HF_HFXO;
2585 #elif defined( CMU_CMD_HFCLKSEL_HFXO )
2586  select = CMU_CMD_HFCLKSEL_HFXO;
2587 #endif
2588  osc = cmuOsc_HFXO;
2589 #if defined( CMU_MAX_FREQ_HFLE )
2590  /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known.
2591  This is known after 'select' is written below. */
2592  setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
2593 #endif
2594 #if defined( CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ )
2595  /* Adjust HFXO buffer current for frequencies above 32MHz */
2596  if (SystemHFXOClockGet() > 32000000)
2597  {
2598  CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
2599  | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ;
2600  }
2601  else
2602  {
2603  CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
2604  | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
2605  }
2606 #endif
2607  break;
2608 
2609  case cmuSelect_HFRCO:
2610 #if defined( _SILICON_LABS_32B_SERIES_1 )
2611  select = CMU_HFCLKSEL_HF_HFRCO;
2612 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2613  select = CMU_CMD_HFCLKSEL_HFRCO;
2614 #endif
2615  osc = cmuOsc_HFRCO;
2616 #if defined( CMU_MAX_FREQ_HFLE )
2617  /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known.
2618  This is known after 'select' is written below. */
2619  setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
2620 #endif
2621  break;
2622 
2623 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
2624  case cmuSelect_USHFRCODIV2:
2625  select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
2626  osc = cmuOsc_USHFRCO;
2627  break;
2628 #endif
2629 
2630 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
2631  case cmuSelect_ULFRCO:
2632  /* ULFRCO cannot be used as HFCLK */
2633  EFM_ASSERT(0);
2634  return;
2635 #endif
2636 
2637  default:
2638  EFM_ASSERT(0);
2639  return;
2640  }
2641 
2642  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2643  CMU_OscillatorEnable(osc, true, true);
2644 
2645  /* Configure worst case wait states for flash access before selecting */
2646  flashWaitStateMax();
2647 
2648 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
2649  /* Wait for voltage upscaling to complete before clock is set. */
2650  if (vScaleFrequency != 0)
2651  {
2652  EMU_VScaleWait();
2653  }
2654 #endif
2655 
2656  /* Switch to selected oscillator */
2657 #if defined( _CMU_HFCLKSEL_MASK )
2658  CMU->HFCLKSEL = select;
2659 #else
2660  CMU->CMD = select;
2661 #endif
2662 #if defined( CMU_MAX_FREQ_HFLE )
2663  /* Update HFLE configuration after 'select' is set.
2664  Note that the HFCLKLE clock is connected differently on planform 1 and 2 */
2665  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
2666 #endif
2667 
2668  /* Update CMSIS core clock variable */
2669  /* (The function will update the global variable) */
2670  freq = SystemCoreClockGet();
2671 
2672  /* Optimize flash access wait state setting for currently selected core clk */
2673  flashWaitStateControl(freq);
2674 
2675 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
2676  /* Keep EMU module informed on source HF clock frequency. This will apply voltage
2677  downscaling after clock is set if downscaling is configured. */
2678  if (vScaleFrequency == 0)
2679  {
2680  EMU_VScaleEM01ByClock(0, true);
2681  }
2682 #endif
2683  break;
2684 
2685 #if defined( _SILICON_LABS_32B_SERIES_1 )
2686  case CMU_LFACLKSEL_REG:
2687  selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;
2688 #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2689  /* HFCLKCLE can not be used as LFACLK */
2690  EFM_ASSERT(ref != cmuSelect_HFCLKLE);
2691 #endif
2692  /* Fall through and select clock source */
2693 
2694  case CMU_LFECLKSEL_REG:
2695  selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;
2696 #if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
2697  /* HFCLKCLE can not be used as LFECLK */
2698  EFM_ASSERT(ref != cmuSelect_HFCLKLE);
2699 #endif
2700  /* Fall through and select clock source */
2701 
2702  case CMU_LFBCLKSEL_REG:
2703  selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;
2704  switch (ref)
2705  {
2706  case cmuSelect_Disabled:
2707  tmp = _CMU_LFACLKSEL_LFA_DISABLED;
2708  break;
2709 
2710  case cmuSelect_LFXO:
2711  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2712  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2713  tmp = _CMU_LFACLKSEL_LFA_LFXO;
2714  break;
2715 
2716  case cmuSelect_LFRCO:
2717  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2718  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2719  tmp = _CMU_LFACLKSEL_LFA_LFRCO;
2720  break;
2721 
2722  case cmuSelect_HFCLKLE:
2723  /* Ensure correct HFLE wait-states and enable HFCLK to LE */
2724  setHfLeConfig(SystemCoreClockGet(), CMU_MAX_FREQ_HFLE);
2725  BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);
2726  tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
2727  break;
2728 
2729  case cmuSelect_ULFRCO:
2730  /* ULFRCO is always on, there is no need to enable it. */
2731  tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
2732  break;
2733 
2734 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
2735  case cmuSelect_PLFRCO:
2736  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2737  CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true);
2738  tmp = _CMU_LFACLKSEL_LFA_PLFRCO;
2739  break;
2740 #endif
2741 
2742  default:
2743  EFM_ASSERT(0);
2744  return;
2745  }
2746  *selReg = tmp;
2747  break;
2748 
2749 #elif defined( _SILICON_LABS_32B_SERIES_0 )
2750  case CMU_LFACLKSEL_REG:
2751  case CMU_LFBCLKSEL_REG:
2752  switch (ref)
2753  {
2754  case cmuSelect_Disabled:
2755  tmp = _CMU_LFCLKSEL_LFA_DISABLED;
2756  break;
2757 
2758  case cmuSelect_LFXO:
2759  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2760  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2761  tmp = _CMU_LFCLKSEL_LFA_LFXO;
2762  break;
2763 
2764  case cmuSelect_LFRCO:
2765  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2766  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2767  tmp = _CMU_LFCLKSEL_LFA_LFRCO;
2768  break;
2769 
2770  case cmuSelect_HFCLKLE:
2771 #if defined( CMU_MAX_FREQ_HFLE )
2772  /* Set HFLE wait-state and divider */
2773  freq = SystemCoreClockGet();
2774  setHfLeConfig(freq, CMU_MAX_FREQ_HFLE);
2775 #endif
2776  /* Ensure HFCORE to LE clocking is enabled */
2777  BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1);
2778  tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
2779  break;
2780 
2781 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2782  case cmuSelect_ULFRCO:
2783  /* ULFRCO is always enabled */
2784  tmp = _CMU_LFCLKSEL_LFA_DISABLED;
2785  lfExtended = 1;
2786  break;
2787 #endif
2788 
2789  default:
2790  /* Illegal clock source for LFA/LFB selected */
2791  EFM_ASSERT(0);
2792  return;
2793  }
2794 
2795  /* Apply select */
2796  if (selRegId == CMU_LFACLKSEL_REG)
2797  {
2798 #if defined( _CMU_LFCLKSEL_LFAE_MASK )
2799  CMU->LFCLKSEL = (CMU->LFCLKSEL
2800  & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))
2801  | (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
2802  | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
2803 #else
2804  CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
2805  | (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
2806 #endif
2807  }
2808  else
2809  {
2810 #if defined( _CMU_LFCLKSEL_LFBE_MASK )
2811  CMU->LFCLKSEL = (CMU->LFCLKSEL
2812  & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))
2813  | (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
2814  | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
2815 #else
2816  CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)
2817  | (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
2818 #endif
2819  }
2820  break;
2821 
2822 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2823  case CMU_LFCCLKSEL_REG:
2824  switch(ref)
2825  {
2826  case cmuSelect_Disabled:
2827  tmp = _CMU_LFCLKSEL_LFA_DISABLED;
2828  break;
2829 
2830  case cmuSelect_LFXO:
2831  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2832  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2833  tmp = _CMU_LFCLKSEL_LFC_LFXO;
2834  break;
2835 
2836  case cmuSelect_LFRCO:
2837  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2838  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2839  tmp = _CMU_LFCLKSEL_LFC_LFRCO;
2840  break;
2841 
2842  default:
2843  /* Illegal clock source for LFC selected */
2844  EFM_ASSERT(0);
2845  return;
2846  }
2847 
2848  /* Apply select */
2849  CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)
2850  | (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
2851  break;
2852 #endif
2853 #endif
2854 
2855 #if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
2856  case CMU_DBGCLKSEL_REG:
2857  switch(ref)
2858  {
2859 #if defined( CMU_DBGCLKSEL_DBG )
2860  case cmuSelect_AUXHFRCO:
2861  /* Select AUXHFRCO as debug clock */
2862  CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
2863  break;
2864 
2865  case cmuSelect_HFCLK:
2866  /* Select divided HFCLK as debug clock */
2867  CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
2868  break;
2869 #endif
2870 
2871 #if defined( CMU_CTRL_DBGCLK )
2872  case cmuSelect_AUXHFRCO:
2873  /* Select AUXHFRCO as debug clock */
2874  CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2875  | CMU_CTRL_DBGCLK_AUXHFRCO;
2876  break;
2877 
2878  case cmuSelect_HFCLK:
2879  /* Select divided HFCLK as debug clock */
2880  CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2881  | CMU_CTRL_DBGCLK_HFCLK;
2882  break;
2883 #endif
2884 
2885  default:
2886  /* Illegal clock source for debug selected */
2887  EFM_ASSERT(0);
2888  return;
2889  }
2890  break;
2891 #endif
2892 
2893 #if defined( USB_PRESENT )
2894  case CMU_USBCCLKSEL_REG:
2895  switch(ref)
2896  {
2897  case cmuSelect_LFXO:
2898  /* Select LFXO as clock source for USB, can only be used in sleep mode */
2899  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2900  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2901 
2902  /* Switch oscillator */
2903  CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
2904 
2905  /* Wait until clock is activated */
2906  while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
2907  {
2908  }
2909  break;
2910 
2911  case cmuSelect_LFRCO:
2912  /* Select LFRCO as clock source for USB, can only be used in sleep mode */
2913  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2914  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2915 
2916  /* Switch oscillator */
2917  CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
2918 
2919  /* Wait until clock is activated */
2920  while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
2921  {
2922  }
2923  break;
2924 
2925 #if defined( CMU_STATUS_USBCHFCLKSEL )
2926  case cmuSelect_HFCLK:
2927  /* Select undivided HFCLK as clock source for USB */
2928  /* Oscillator must already be enabled to avoid a core lockup */
2929  CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
2930  /* Wait until clock is activated */
2931  while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
2932  {
2933  }
2934  break;
2935 #endif
2936 
2937 #if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
2938  case cmuSelect_USHFRCO:
2939  /* Select USHFRCO as clock source for USB */
2940  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2941  CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
2942 
2943  /* Switch oscillator */
2944  CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
2945 
2946  /* Wait until clock is activated */
2947  while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
2948  {
2949  }
2950  break;
2951 #endif
2952 
2953  default:
2954  /* Illegal clock source for USB */
2955  EFM_ASSERT(0);
2956  return;
2957  }
2958  break;
2959 #endif
2960 
2961  default:
2962  EFM_ASSERT(0);
2963  break;
2964  }
2965 #if defined( CMU_MAX_FREQ_HFLE )
2966  /* Get to assert wait-state config. */
2967  getHfLeConfig();
2968 #endif
2969 }
2970 
2971 /**************************************************************************/
3000 void CMU_FreezeEnable(bool enable)
3001 {
3002  if (enable)
3003  {
3004  /* Wait for any ongoing LF synchronization to complete. This is just to */
3005  /* protect against the rare case when a user */
3006  /* - modifies a register requiring LF sync */
3007  /* - then enables freeze before LF sync completed */
3008  /* - then modifies the same register again */
3009  /* since modifying a register while it is in sync progress should be */
3010  /* avoided. */
3011  while (CMU->SYNCBUSY)
3012  {
3013  }
3014 
3015  CMU->FREEZE = CMU_FREEZE_REGFREEZE;
3016  }
3017  else
3018  {
3019  CMU->FREEZE = 0;
3020  }
3021 }
3022 
3023 
3024 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
3025 /***************************************************************************/
3032 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
3033 {
3034  return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
3035  >> _CMU_HFRCOCTRL_BAND_SHIFT);
3036 }
3037 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
3038 
3039 
3040 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
3041 /***************************************************************************/
3049 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
3050 {
3051  uint32_t tuning;
3052  uint32_t freq;
3053  CMU_Select_TypeDef osc;
3054 
3055  /* Read tuning value from calibration table */
3056  switch (band)
3057  {
3058  case cmuHFRCOBand_1MHz:
3059  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
3060  >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
3061  break;
3062 
3063  case cmuHFRCOBand_7MHz:
3064  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)
3065  >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
3066  break;
3067 
3068  case cmuHFRCOBand_11MHz:
3069  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)
3070  >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
3071  break;
3072 
3073  case cmuHFRCOBand_14MHz:
3074  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)
3075  >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
3076  break;
3077 
3078  case cmuHFRCOBand_21MHz:
3079  tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
3080  >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
3081  break;
3082 
3083 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
3084  case cmuHFRCOBand_28MHz:
3085  tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
3086  >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
3087  break;
3088 #endif
3089 
3090  default:
3091  EFM_ASSERT(0);
3092  return;
3093  }
3094 
3095  /* If HFRCO is used for core clock, we have to consider flash access WS. */
3096  osc = CMU_ClockSelectGet(cmuClock_HF);
3097  if (osc == cmuSelect_HFRCO)
3098  {
3099  /* Configure worst case wait states for flash access before setting divider */
3100  flashWaitStateMax();
3101  }
3102 
3103  /* Set band/tuning */
3104  CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
3105  ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK))
3106  | (band << _CMU_HFRCOCTRL_BAND_SHIFT)
3107  | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
3108 
3109  /* If HFRCO is used for core clock, optimize flash WS */
3110  if (osc == cmuSelect_HFRCO)
3111  {
3112  /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
3113  freq = SystemCoreClockGet();
3114  flashWaitStateControl(freq);
3115  }
3116 
3117 #if defined(CMU_MAX_FREQ_HFLE)
3118  /* Reduce HFLE frequency if possible. */
3119  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
3120 #endif
3121 
3122 }
3123 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
3124 
3125 
3126 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
3127 /**************************************************************************/
3137 static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
3138 {
3139  switch (freq)
3140  {
3141  /* 1, 2 and 4MHz share the same calibration word */
3142  case cmuHFRCOFreq_1M0Hz:
3143  case cmuHFRCOFreq_2M0Hz:
3144  case cmuHFRCOFreq_4M0Hz:
3145  return DEVINFO->HFRCOCAL0;
3146 
3147  case cmuHFRCOFreq_7M0Hz:
3148  return DEVINFO->HFRCOCAL3;
3149 
3150  case cmuHFRCOFreq_13M0Hz:
3151  return DEVINFO->HFRCOCAL6;
3152 
3153  case cmuHFRCOFreq_16M0Hz:
3154  return DEVINFO->HFRCOCAL7;
3155 
3156  case cmuHFRCOFreq_19M0Hz:
3157  return DEVINFO->HFRCOCAL8;
3158 
3159  case cmuHFRCOFreq_26M0Hz:
3160  return DEVINFO->HFRCOCAL10;
3161 
3162  case cmuHFRCOFreq_32M0Hz:
3163  return DEVINFO->HFRCOCAL11;
3164 
3165  case cmuHFRCOFreq_38M0Hz:
3166  return DEVINFO->HFRCOCAL12;
3167 
3168  default: /* cmuHFRCOFreq_UserDefined */
3169  return 0;
3170  }
3171 }
3172 
3173 
3174 /***************************************************************************/
3181 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void)
3182 {
3183  return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
3184 }
3185 
3186 
3187 /***************************************************************************/
3194 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)
3195 {
3196  uint32_t freqCal;
3197  uint32_t sysFreq;
3198 
3199  /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
3200  freqCal = CMU_HFRCODevinfoGet(setFreq);
3201  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
3202  SystemHfrcoFreq = (uint32_t)setFreq;
3203 
3204  /* Set max wait-states while changing core clock */
3205  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
3206  {
3207  flashWaitStateMax();
3208  }
3209 
3210  /* Wait for any previous sync to complete, and then set calibration data
3211  for the selected frequency. */
3212  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));
3213 
3214  /* Check for valid calibration data */
3215  EFM_ASSERT(freqCal != UINT_MAX);
3216 
3217  /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
3218  switch(setFreq)
3219  {
3220  case cmuHFRCOFreq_1M0Hz:
3221  freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3222  | CMU_HFRCOCTRL_CLKDIV_DIV4;
3223  break;
3224 
3225  case cmuHFRCOFreq_2M0Hz:
3226  freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3227  | CMU_HFRCOCTRL_CLKDIV_DIV2;
3228  break;
3229 
3230  case cmuHFRCOFreq_4M0Hz:
3231  freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3232  | CMU_HFRCOCTRL_CLKDIV_DIV1;
3233  break;
3234 
3235  default:
3236  break;
3237  }
3238 
3239  /* Update HFLE configuration before updating HFRCO.
3240  Use the new set frequency. */
3241  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
3242  {
3243  /* setFreq is worst-case as dividers may reduce the HFLE frequency. */
3244  setHfLeConfig(setFreq, CMU_MAX_FREQ_HFLE);
3245  }
3246 
3247  CMU->HFRCOCTRL = freqCal;
3248 
3249  /* If HFRCO is selected as HF clock, optimize flash access wait-state configuration
3250  for this frequency and update CMSIS core clock variable. */
3251  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
3252  {
3253  /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
3254  sysFreq = SystemCoreClockGet();
3255  EFM_ASSERT(sysFreq <= (uint32_t)setFreq);
3256  EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
3257  EFM_ASSERT(setFreq == SystemHfrcoFreq);
3258  flashWaitStateControl(sysFreq);
3259  }
3260 
3261  /* Reduce HFLE frequency if possible. */
3262  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
3263 
3264  /* Update voltage scaling */
3265 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
3266  EMU_VScaleEM01ByClock(0, true);
3267 #endif
3268 }
3269 #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */
3270 
3271 #if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
3272 /***************************************************************************/
3282 uint32_t CMU_HFRCOStartupDelayGet(void)
3283 {
3284  return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)
3285  >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
3286 }
3287 
3288 
3289 /***************************************************************************/
3299 void CMU_HFRCOStartupDelaySet(uint32_t delay)
3300 {
3301  EFM_ASSERT(delay <= 31);
3302 
3303  delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
3304  CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))
3305  | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
3306 }
3307 #endif
3308 
3309 
3310 #if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
3311 /***************************************************************************/
3330 void CMU_HFXOAutostartEnable(uint32_t userSel,
3331  bool enEM0EM1Start,
3332  bool enEM0EM1StartSel)
3333 {
3334  uint32_t hfxoFreq;
3335  uint32_t hfxoCtrl;
3336 
3337  /* Mask supported enable bits. */
3338 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
3339  userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK;
3340 #else
3341  userSel = 0;
3342 #endif
3343 
3344  hfxoCtrl = CMU->HFXOCTRL & ~( userSel
3345  | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
3346  | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
3347 
3348  hfxoCtrl |= userSel
3349  | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
3350  | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
3351 
3352  /* Set wait-states for HFXO if automatic start and select is configured. */
3353  if (userSel || enEM0EM1StartSel)
3354  {
3355  hfxoFreq = SystemHFXOClockGet();
3356  flashWaitStateControl(hfxoFreq);
3357  setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE);
3358  }
3359 
3360  /* Update HFXOCTRL after wait-states are updated as HF may automatically switch
3361  to HFXO when automatic select is enabled . */
3362  CMU->HFXOCTRL = hfxoCtrl;
3363 }
3364 #endif
3365 
3366 
3367 /**************************************************************************/
3379 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
3380 {
3381  /* Do not disable HFXO if it is currently selected as HF/Core clock */
3382  EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO);
3383 
3384  /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */
3385 #if defined( _EMU_PWRCTRL_REGPWRSEL_MASK )
3386  EFM_ASSERT(EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD);
3387 #endif
3388 
3389  /* HFXO must be disabled before reconfiguration */
3390  CMU_OscillatorEnable(cmuOsc_HFXO, false, true);
3391 
3392 #if defined( _CMU_HFXOCTRL_MASK )
3393  /* Verify that the deprecated autostart fields are not used,
3394  * @ref CMU_HFXOAutostartEnable must be used instead. */
3395  EFM_ASSERT(!(hfxoInit->autoStartEm01
3396  || hfxoInit->autoSelEm01
3397  || hfxoInit->autoStartSelOnRacWakeup));
3398 
3399  uint32_t mode = CMU_HFXOCTRL_MODE_XTAL;
3400 
3401  /* AC coupled external clock not supported */
3402  EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled);
3403  if (hfxoInit->mode == cmuOscMode_External)
3404  {
3405  mode = CMU_HFXOCTRL_MODE_EXTCLK;
3406  }
3407 
3408  /* Apply control settings */
3409  BUS_RegMaskedWrite(&CMU->HFXOCTRL,
3410  _CMU_HFXOCTRL_LOWPOWER_MASK | _CMU_HFXOCTRL_MODE_MASK,
3411  (hfxoInit->lowPowerMode ? CMU_HFXOCTRL_LOWPOWER : 0) | mode);
3412 
3413  /* Set XTAL tuning parameters */
3414 
3415 #if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK)
3416  /* Set peak detection threshold */
3417  BUS_RegMaskedWrite(&CMU->HFXOCTRL1,
3418  _CMU_HFXOCTRL1_PEAKDETTHR_MASK,
3419  hfxoInit->thresholdPeakDetect);
3420 #endif
3421 
3422  /* Set tuning for startup and steady state */
3423  BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,
3424  _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
3425  | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK,
3426  (hfxoInit->ctuneStartup
3427  << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
3428  | (hfxoInit->xoCoreBiasTrimStartup
3429  << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT));
3430 
3431  BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
3432  _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
3433  | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
3434  | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
3435  | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
3436  (hfxoInit->ctuneSteadyState
3437  << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
3438  | (hfxoInit->regIshSteadyState
3439  << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
3440  | (hfxoInit->xoCoreBiasTrimSteadyState
3441  << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
3442  | getRegIshUpperVal(hfxoInit->regIshSteadyState));
3443 
3444  /* Set timeouts */
3445  BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,
3446  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
3447  | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
3448  | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
3449  | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
3450  (hfxoInit->timeoutShuntOptimization
3451  << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
3452  | (hfxoInit->timeoutPeakDetect
3453  << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
3454  | (hfxoInit->timeoutSteady
3455  << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
3456  | (hfxoInit->timeoutStartup
3457  << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
3458 #else
3459  BUS_RegMaskedWrite(&CMU->CTRL,
3460  _CMU_CTRL_HFXOTIMEOUT_MASK
3461  | _CMU_CTRL_HFXOBOOST_MASK
3462  | _CMU_CTRL_HFXOMODE_MASK
3463  | _CMU_CTRL_HFXOGLITCHDETEN_MASK,
3464  (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT)
3465  | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT)
3466  | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT)
3467  | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0));
3468 #endif
3469 }
3470 
3471 
3472 /***************************************************************************/
3479 uint32_t CMU_LCDClkFDIVGet(void)
3480 {
3481 #if defined( LCD_PRESENT )
3482  return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
3483 #else
3484  return 0;
3485 #endif /* defined(LCD_PRESENT) */
3486 }
3487 
3488 
3489 /***************************************************************************/
3502 void CMU_LCDClkFDIVSet(uint32_t div)
3503 {
3504 #if defined( LCD_PRESENT )
3505  EFM_ASSERT(div <= cmuClkDiv_128);
3506 
3507  /* Do not allow modification if LCD clock enabled */
3508  if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
3509  {
3510  return;
3511  }
3512 
3513  div <<= _CMU_LCDCTRL_FDIV_SHIFT;
3514  div &= _CMU_LCDCTRL_FDIV_MASK;
3515  CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div;
3516 #else
3517  (void)div; /* Unused parameter */
3518 #endif /* defined(LCD_PRESENT) */
3519 }
3520 
3521 
3522 /**************************************************************************/
3534 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)
3535 {
3536  /* Do not disable LFXO if it is currently selected as HF/Core clock */
3537  EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO);
3538 
3539  /* LFXO must be disabled before reconfiguration */
3540  CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
3541 
3542 #if defined( _CMU_LFXOCTRL_MASK )
3543  BUS_RegMaskedWrite(&CMU->LFXOCTRL,
3544  _CMU_LFXOCTRL_TUNING_MASK
3545  | _CMU_LFXOCTRL_GAIN_MASK
3546  | _CMU_LFXOCTRL_TIMEOUT_MASK
3547  | _CMU_LFXOCTRL_MODE_MASK,
3548  (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)
3549  | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)
3550  | (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT)
3551  | (lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT));
3552 #else
3553  bool cmuBoost = (lfxoInit->boost & 0x2);
3554  BUS_RegMaskedWrite(&CMU->CTRL,
3555  _CMU_CTRL_LFXOTIMEOUT_MASK
3556  | _CMU_CTRL_LFXOBOOST_MASK
3557  | _CMU_CTRL_LFXOMODE_MASK,
3558  (lfxoInit->timeout << _CMU_CTRL_LFXOTIMEOUT_SHIFT)
3559  | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT)
3560  | (lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT));
3561 #endif
3562 
3563 #if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
3564  bool emuReduce = (lfxoInit->boost & 0x1);
3565  BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0);
3566 #endif
3567 }
3568 
3569 
3570 /***************************************************************************/
3594 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
3595 {
3596  uint32_t rdyBitPos;
3597 #if defined( _SILICON_LABS_32B_SERIES_1 )
3598  uint32_t ensBitPos;
3599 #endif
3600 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
3601  uint32_t hfxoTrimStatus;
3602 #endif
3603 
3604  uint32_t enBit;
3605  uint32_t disBit;
3606 
3607  switch (osc)
3608  {
3609  case cmuOsc_HFRCO:
3610  enBit = CMU_OSCENCMD_HFRCOEN;
3611  disBit = CMU_OSCENCMD_HFRCODIS;
3612  rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;
3613 #if defined( _SILICON_LABS_32B_SERIES_1 )
3614  ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;
3615 #endif
3616  break;
3617 
3618  case cmuOsc_HFXO:
3619  enBit = CMU_OSCENCMD_HFXOEN;
3620  disBit = CMU_OSCENCMD_HFXODIS;
3621  rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;
3622 #if defined( _SILICON_LABS_32B_SERIES_1 )
3623  ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;
3624 #endif
3625  break;
3626 
3627  case cmuOsc_AUXHFRCO:
3628  enBit = CMU_OSCENCMD_AUXHFRCOEN;
3629  disBit = CMU_OSCENCMD_AUXHFRCODIS;
3630  rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;
3631 #if defined( _SILICON_LABS_32B_SERIES_1 )
3632  ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;
3633 #endif
3634  break;
3635 
3636  case cmuOsc_LFRCO:
3637  enBit = CMU_OSCENCMD_LFRCOEN;
3638  disBit = CMU_OSCENCMD_LFRCODIS;
3639  rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;
3640 #if defined( _SILICON_LABS_32B_SERIES_1 )
3641  ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;
3642 #endif
3643  break;
3644 
3645  case cmuOsc_LFXO:
3646  enBit = CMU_OSCENCMD_LFXOEN;
3647  disBit = CMU_OSCENCMD_LFXODIS;
3648  rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;
3649 #if defined( _SILICON_LABS_32B_SERIES_1 )
3650  ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;
3651 #endif
3652  break;
3653 
3654 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
3655  case cmuOsc_USHFRCO:
3656  enBit = CMU_OSCENCMD_USHFRCOEN;
3657  disBit = CMU_OSCENCMD_USHFRCODIS;
3658  rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
3659 #if defined( _SILICON_LABS_32B_SERIES_1 )
3660  ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
3661 #endif
3662  break;
3663 #endif
3664 
3665 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
3666  case cmuOsc_PLFRCO:
3667  enBit = CMU_OSCENCMD_PLFRCOEN;
3668  disBit = CMU_OSCENCMD_PLFRCODIS;
3669  rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT;
3670  ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT;
3671  break;
3672 #endif
3673 
3674  default:
3675  /* Undefined clock source or cmuOsc_ULFRCO. ULFRCO is always enabled,
3676  and cannot be disabled. Ie. the definition of cmuOsc_ULFRCO is primarely
3677  intended for information: the ULFRCO is always on. */
3678  EFM_ASSERT(0);
3679  return;
3680  }
3681 
3682  if (enable)
3683  {
3684  #if defined( _CMU_HFXOCTRL_MASK )
3685  bool firstHfxoEnable = false;
3686 
3687  /* Enabling the HFXO for the first time requires special handling. We use the
3688  * PEAKDETSHUTOPTMODE field of the HFXOCTRL register to see if this is the
3689  * first time the HFXO is enabled. */
3690  if ((osc == cmuOsc_HFXO) &&
3691  ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK))
3692  == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
3693  {
3694  firstHfxoEnable = true;
3695  /* First time we enable an external clock we should switch to CMD mode to make sure that
3696  * we only do SCO and not PDA tuning. */
3697  if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_EXTCLK)
3698  {
3699  CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
3700  | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
3701  }
3702  }
3703 #endif
3704  CMU->OSCENCMD = enBit;
3705 
3706 #if defined( _SILICON_LABS_32B_SERIES_1 )
3707  /* Always wait for ENS to go high */
3708  while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))
3709  {
3710  }
3711 #endif
3712 
3713  /* Wait for clock to become ready after enable */
3714  if (wait)
3715  {
3716  while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
3717 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
3718  if ((osc == cmuOsc_HFXO) && firstHfxoEnable)
3719  {
3720  if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) == CMU_HFXOCTRL_MODE_EXTCLK)
3721  {
3722  /* External clock mode should only do shunt current optimization. */
3723  CMU_OscillatorTuningOptimize(cmuOsc_HFXO, cmuHFXOTuningMode_ShuntCommand, true);
3724  }
3725  else
3726  {
3727  /* Wait for peak detection and shunt current optimization to complete. */
3728  CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto);
3729  }
3730 
3731  /* Disable the HFXO again to apply the trims. Apply trim from HFXOTRIMSTATUS
3732  when disabled. */
3733  hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO);
3734  CMU_OscillatorEnable(cmuOsc_HFXO, false, true);
3735  CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus);
3736 
3737  /* Restart in CMD mode. */
3738  CMU->OSCENCMD = enBit;
3739  while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
3740  }
3741 #endif
3742  }
3743  }
3744  else
3745  {
3746  CMU->OSCENCMD = disBit;
3747 
3748 #if defined( _SILICON_LABS_32B_SERIES_1 )
3749  /* Always wait for ENS to go low */
3750  while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))
3751  {
3752  }
3753 #endif
3754  }
3755 }
3756 
3757 
3758 /***************************************************************************/
3772 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
3773 {
3774  uint32_t ret;
3775 
3776  switch (osc)
3777  {
3778  case cmuOsc_LFRCO:
3779  ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)
3780  >> _CMU_LFRCOCTRL_TUNING_SHIFT;
3781  break;
3782 
3783  case cmuOsc_HFRCO:
3784  ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK)
3785  >> _CMU_HFRCOCTRL_TUNING_SHIFT;
3786  break;
3787 
3788  case cmuOsc_AUXHFRCO:
3789  ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)
3790  >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
3791  break;
3792 
3793 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3794  case cmuOsc_HFXO:
3795  ret = CMU->HFXOTRIMSTATUS & ( _CMU_HFXOTRIMSTATUS_REGISH_MASK
3796  | _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK);
3797  break;
3798 #endif
3799 
3800  default:
3801  EFM_ASSERT(0);
3802  ret = 0;
3803  break;
3804  }
3805 
3806  return ret;
3807 }
3808 
3809 
3810 /***************************************************************************/
3830 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
3831 {
3832 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3833  uint32_t regIshUpper;
3834 #endif
3835 
3836  switch (osc)
3837  {
3838  case cmuOsc_LFRCO:
3839  EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK
3840  >> _CMU_LFRCOCTRL_TUNING_SHIFT));
3841  val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
3842 #if defined( _SILICON_LABS_32B_SERIES_1 )
3843  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));
3844 #endif
3845  CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))
3846  | (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
3847  break;
3848 
3849  case cmuOsc_HFRCO:
3850  EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK
3851  >> _CMU_HFRCOCTRL_TUNING_SHIFT));
3852  val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
3853 #if defined( _SILICON_LABS_32B_SERIES_1 )
3854  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))
3855  {
3856  }
3857 #endif
3858  CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))
3859  | (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
3860  break;
3861 
3862  case cmuOsc_AUXHFRCO:
3863  EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK
3864  >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
3865  val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
3866 #if defined( _SILICON_LABS_32B_SERIES_1 )
3867  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))
3868  {
3869  }
3870 #endif
3871  CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))
3872  | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
3873  break;
3874 
3875 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3876  case cmuOsc_HFXO:
3877 
3878  /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled */
3879  EFM_ASSERT(!(CMU->STATUS & CMU_STATUS_HFXOENS));
3880 
3881  /* Switch to command mode. Automatic SCO and PDA calibration is not done
3882  at the next enable. Set user REGISH, REGISHUPPER and IBTRIMXOCORE. */
3883  CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
3884  | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
3885 
3886  regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK)
3887  >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT);
3888 
3889  BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
3890  _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
3891  | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
3892  | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
3893  val | regIshUpper);
3894  break;
3895 #endif
3896 
3897  default:
3898  EFM_ASSERT(0);
3899  break;
3900  }
3901 }
3902 
3903 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
3904 /***************************************************************************/
3918 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc,
3919  CMU_HFXOTuningMode_TypeDef mode)
3920 {
3921  EFM_ASSERT(osc == cmuOsc_HFXO);
3922  uint32_t waitFlags;
3923 
3924  /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only */
3925  (void)osc;
3926 
3927  if (BUS_RegMaskedRead(&CMU->HFXOCTRL, _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
3928  == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD)
3929  {
3930  waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
3931  }
3932  else
3933  {
3934  /* Set wait flags for each command and wait */
3935  switch (mode)
3936  {
3937  case cmuHFXOTuningMode_ShuntCommand:
3938  waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY;
3939  break;
3940 
3941  case cmuHFXOTuningMode_Auto:
3942  /* Fall through */
3943  case cmuHFXOTuningMode_PeakShuntCommand:
3944  waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
3945  break;
3946 
3947  default:
3948  waitFlags = _CMU_STATUS_MASK;
3949  EFM_ASSERT(false);
3950  }
3951  }
3952  while ((CMU->STATUS & waitFlags) != waitFlags);
3953 
3954  /* Check error flags */
3955  if (waitFlags & CMU_STATUS_HFXOPEAKDETRDY)
3956  {
3957  return (CMU->IF & CMU_IF_HFXOPEAKDETERR ? true : false);
3958  }
3959  return true;
3960 }
3961 
3962 
3963 /***************************************************************************/
3982 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
3983  CMU_HFXOTuningMode_TypeDef mode,
3984  bool wait)
3985 {
3986  switch (osc)
3987  {
3988  case cmuOsc_HFXO:
3989  if (mode)
3990  {
3991  /* Clear error flag before command write */
3992  CMU->IFC = CMU_IFC_HFXOPEAKDETERR;
3993  CMU->CMD = mode;
3994  }
3995  if (wait)
3996  {
3997  return CMU_OscillatorTuningWait(osc, mode);
3998  }
3999 
4000  default:
4001  EFM_ASSERT(false);
4002  }
4003  return true;
4004 }
4005 #endif
4006 
4007 
4008 /**************************************************************************/
4019 bool CMU_PCNTClockExternalGet(unsigned int instance)
4020 {
4021  uint32_t setting;
4022 
4023  switch (instance)
4024  {
4025 #if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
4026  case 0:
4027  setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
4028  break;
4029 
4030 #if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
4031  case 1:
4032  setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
4033  break;
4034 
4035 #if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
4036  case 2:
4037  setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
4038  break;
4039 #endif
4040 #endif
4041 #endif
4042 
4043  default:
4044  setting = 0;
4045  break;
4046  }
4047  return (setting ? true : false);
4048 }
4049 
4050 
4051 /**************************************************************************/
4061 void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
4062 {
4063 #if defined( PCNT_PRESENT )
4064  uint32_t setting = 0;
4065 
4066  EFM_ASSERT(instance < PCNT_COUNT);
4067 
4068  if (external)
4069  {
4070  setting = 1;
4071  }
4072 
4073  BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting);
4074 
4075 #else
4076  (void)instance; /* Unused parameter */
4077  (void)external; /* Unused parameter */
4078 #endif
4079 }
4080 
4081 
4082 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
4083 /***************************************************************************/
4090 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
4091 {
4092  return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF
4093  & _CMU_USHFRCOCONF_BAND_MASK)
4094  >> _CMU_USHFRCOCONF_BAND_SHIFT);
4095 }
4096 #endif
4097 
4098 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
4099 /***************************************************************************/
4106 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
4107 {
4108  uint32_t tuning;
4109  uint32_t fineTuning;
4110  CMU_Select_TypeDef osc;
4111 
4112  /* Cannot switch band if USHFRCO is already selected as HF clock. */
4113  osc = CMU_ClockSelectGet(cmuClock_HF);
4114  EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
4115 
4116  /* Read tuning value from calibration table */
4117  switch (band)
4118  {
4119  case cmuUSHFRCOBand_24MHz:
4120  tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
4121  >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
4122  fineTuning = (DEVINFO->USHFRCOCAL0
4123  & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
4124  >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
4125  break;
4126 
4127  case cmuUSHFRCOBand_48MHz:
4128  tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)
4129  >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
4130  fineTuning = (DEVINFO->USHFRCOCAL0
4131  & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)
4132  >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
4133  /* Enable the clock divider before switching the band from 24 to 48MHz */
4134  BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
4135  break;
4136 
4137  default:
4138  EFM_ASSERT(0);
4139  return;
4140  }
4141 
4142  /* Set band and tuning */
4143  CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)
4144  | (band << _CMU_USHFRCOCONF_BAND_SHIFT);
4145  CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)
4146  | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
4147  CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)
4148  | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
4149 
4150  /* Disable the clock divider after switching the band from 48 to 24MHz */
4151  if (band == cmuUSHFRCOBand_24MHz)
4152  {
4153  BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
4154  }
4155 }
4156 #endif
4157 
4158 
4159 
4162 #endif /* __EM_CMU_H */
CMU_LFXOInit_TypeDef
Definition: em_cmu.h:1025
em_cmu.h
Clock management unit (CMU) API.
CMU_ClockSelectSet
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
Definition: em_cmu.c:2521
CMU_HFXOInit_TypeDef::xoCoreBiasTrimSteadyState
uint8_t xoCoreBiasTrimSteadyState
Definition: em_cmu.h:1083
cmuAUXHFRCOFreq_2M0Hz
Definition: em_cmu.h:240
cmuSelect_HFCLK
Definition: em_cmu.h:972
CMU_OSCENCMD_HFRCOEN
#define CMU_OSCENCMD_HFRCOEN
Definition: efr32mg1p_cmu.h:775
CMU_AUXHFRCODevinfoGet
static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO.
Definition: em_cmu.c:782
_CMU_LFACLKSEL_LFA_LFXO
#define _CMU_LFACLKSEL_LFA_LFXO
Definition: efr32mg1p_cmu.h:886
cmuSelect_AUXHFRCO
Definition: em_cmu.h:971
_CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT
#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT
Definition: efr32mg1p_cmu.h:1623
CMU_FREEZE_REGFREEZE
#define CMU_FREEZE_REGFREEZE
Definition: efr32mg1p_cmu.h:1651
_CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT
Definition: efr32mg1p_cmu.h:446
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK
Definition: efr32mg1p_cmu.h:347
cmuHFXOTuningMode_ShuntCommand
Definition: em_cmu.h:1000
_CMU_LFACLKSEL_LFA_SHIFT
#define _CMU_LFACLKSEL_LFA_SHIFT
Definition: efr32mg1p_cmu.h:881
cmuSelect_HFXO
Definition: em_cmu.h:968
_CMU_CALCNT_CALCNT_SHIFT
#define _CMU_CALCNT_CALCNT_SHIFT
Definition: efr32mg1p_cmu.h:767
CMU_PCNTClockExternalSet
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
Definition: em_cmu.c:4061
CMU_CMD_CALSTART
#define CMU_CMD_CALSTART
Definition: efr32mg1p_cmu.h:829
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT
Definition: efr32mg1p_cmu.h:471
cmuOscMode_External
Definition: em_cmu.h:958
_CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT
Definition: efr32mg1p_cmu.h:450
_CMU_HFPRESC_HFCLKLEPRESC_MASK
#define _CMU_HFPRESC_HFCLKLEPRESC_MASK
Definition: efr32mg1p_cmu.h:1486
cmuHFRCOFreq_38M0Hz
Definition: em_cmu.h:228
cmuHFRCOFreq_1M0Hz
Definition: em_cmu.h:219
cmuAUXHFRCOFreq_32M0Hz
Definition: em_cmu.h:247
CMU_HFCLKSEL_HF_HFRCO
#define CMU_HFCLKSEL_HF_HFRCO
Definition: efr32mg1p_cmu.h:873
CMU_HFXOInit_TypeDef::regIshSteadyState
uint8_t regIshSteadyState
Definition: em_cmu.h:1081
em_assert.h
Emlib peripheral API "assert" implementation.
CMU_HFRCOCTRL_CLKDIV_DIV2
#define CMU_HFRCOCTRL_CLKDIV_DIV2
Definition: efr32mg1p_cmu.h:241
_ROMTABLE_PID0_REVMAJOR_SHIFT
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
Definition: efr32mg1p_romtable.h:62
CMU_HFXOInit_TypeDef::timeoutStartup
uint8_t timeoutStartup
Definition: em_cmu.h:1088
_CMU_LFEPRESC0_RTCC_DIV1
#define _CMU_LFEPRESC0_RTCC_DIV1
Definition: efr32mg1p_cmu.h:1581
systemPartFamilyEfm32Giant
Definition: em_system.h:71
CMU_Calibrate
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
Definition: em_cmu.c:904
em_bus.h
RAM and peripheral bit-field set and clear API.
cmuClock_LEUART0
Definition: em_cmu.h:848
systemPartFamilyEzr32Leopard
Definition: em_system.h:110
CMU_LFBCLKSEL_LFB_HFCLKLE
#define CMU_LFBCLKSEL_LFB_HFCLKLE
Definition: efr32mg1p_cmu.h:909
CMU_HFXOCTRL_AUTOSTARTEM0EM1
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1
Definition: efr32mg1p_cmu.h:391
cmuSelect_HFCLKLE
Definition: em_cmu.h:970
cmuAUXHFRCOFreq_7M0Hz
Definition: em_cmu.h:242
CMU_OSCENCMD_HFXOEN
#define CMU_OSCENCMD_HFXOEN
Definition: efr32mg1p_cmu.h:785
CMU_Select_TypeDef
CMU_Select_TypeDef
Definition: em_cmu.h:962
CMU_LFXOInit_TypeDef::timeout
uint8_t timeout
Definition: em_cmu.h:1033
cmuClock_RTCC
Definition: em_cmu.h:918
CMU_CALCTRL_DOWNSEL_AUXHFRCO
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO
Definition: efr32mg1p_cmu.h:700
_CMU_LFXOCTRL_TIMEOUT_SHIFT
#define _CMU_LFXOCTRL_TIMEOUT_SHIFT
Definition: efr32mg1p_cmu.h:620
CMU_HFRCODevinfoGet
static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
Get a pointer to the HFRCO frequency calibration word in DEVINFO.
Definition: em_cmu.c:3137
MSC
#define MSC
Definition: efr32mg1p233f256gm48.h:333
_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
Definition: efr32mg1p_cmu.h:447
CMU_HFXOInit_TypeDef
Definition: em_cmu.h:1072
cmuHFRCOFreq_16M0Hz
Definition: em_cmu.h:224
cmuClkDiv_8
#define cmuClkDiv_8
Definition: em_cmu.h:152
_CMU_SYNCBUSY_LFRCOBSY_SHIFT
#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT
Definition: efr32mg1p_cmu.h:1628
CMU_DBGCLKSEL_DBG_HFCLK
#define CMU_DBGCLKSEL_DBG_HFCLK
Definition: efr32mg1p_cmu.h:860
cmuAUXHFRCOFreq_1M0Hz
Definition: em_cmu.h:239
cmuSelect_LFRCO
Definition: em_cmu.h:967
cmuOscMode_AcCoupled
Definition: em_cmu.h:957
_CMU_LFACLKSEL_LFA_DISABLED
#define _CMU_LFACLKSEL_LFA_DISABLED
Definition: efr32mg1p_cmu.h:884
cmuHFRCOFreq_2M0Hz
Definition: em_cmu.h:220
_CMU_LFXOCTRL_GAIN_MASK
#define _CMU_LFXOCTRL_GAIN_MASK
Definition: efr32mg1p_cmu.h:598
_CMU_HFEXPPRESC_PRESC_MASK
#define _CMU_HFEXPPRESC_PRESC_MASK
Definition: efr32mg1p_cmu.h:1518
CMU_ClockPrescSet
void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc)
Set clock prescaler.
Definition: em_cmu.c:1894
_CMU_LFACLKSEL_LFA_LFRCO
#define _CMU_LFACLKSEL_LFA_LFRCO
Definition: efr32mg1p_cmu.h:885
cmuAUXHFRCOFreq_19M0Hz
Definition: em_cmu.h:245
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK
Definition: efr32mg1p_cmu.h:398
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
Definition: efr32mg1p_cmu.h:554
_CMU_STATUS_AUXHFRCORDY_SHIFT
#define _CMU_STATUS_AUXHFRCORDY_SHIFT
Definition: efr32mg1p_cmu.h:957
CMU_HFCLKSEL_HF_LFRCO
#define CMU_HFCLKSEL_HF_LFRCO
Definition: efr32mg1p_cmu.h:875
_CMU_HFXOSTARTUPCTRL_CTUNE_MASK
#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
Definition: efr32mg1p_cmu.h:427
CMU_HFXOCTRL_MODE_XTAL
#define CMU_HFXOCTRL_MODE_XTAL
Definition: efr32mg1p_cmu.h:344
CMU_SYNCBUSY_LFAPRESC0
#define CMU_SYNCBUSY_LFAPRESC0
Definition: efr32mg1p_cmu.h:1592
_CMU_CALCNT_CALCNT_MASK
#define _CMU_CALCNT_CALCNT_MASK
Definition: efr32mg1p_cmu.h:768
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT
Definition: efr32mg1p_cmu.h:527
CMU_CALCTRL_UPSEL_HFRCO
#define CMU_CALCTRL_UPSEL_HFRCO
Definition: efr32mg1p_cmu.h:680
CMU_HFXOCTRL_AUTOSTARTSELEM0EM1
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1
Definition: efr32mg1p_cmu.h:396
MSC_UNLOCK_CODE
#define MSC_UNLOCK_CODE
Definition: efr32mg1p233f256gm48.h:394
CMU_HFXOInit_TypeDef::thresholdPeakDetect
uint8_t thresholdPeakDetect
Definition: em_cmu.h:1084
MSC_READCTRL_MODE_WS1
#define MSC_READCTRL_MODE_WS1
Definition: efr32mg1p_msc.h:136
CMU_HFXOInit_TypeDef::lowPowerMode
bool lowPowerMode
Definition: em_cmu.h:1075
SystemHFClockGet
uint32_t SystemHFClockGet(void)
Get the current HFCLK frequency.
Definition: system_efr32mg1p.c:181
_CMU_LFECLKSEL_LFE_MASK
#define _CMU_LFECLKSEL_LFE_MASK
Definition: efr32mg1p_cmu.h:916
CMU_FreezeEnable
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
Definition: em_cmu.c:3000
cmuHFXOTuningMode_PeakShuntCommand
Definition: em_cmu.h:1001
_CMU_AUXHFRCOCTRL_CLKDIV_MASK
#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK
Definition: efr32mg1p_cmu.h:278
CMU_AUXHFRCOFreq_TypeDef
CMU_AUXHFRCOFreq_TypeDef
Definition: em_cmu.h:237
CMU_HFCLKSEL_HF_HFXO
#define CMU_HFCLKSEL_HF_HFXO
Definition: efr32mg1p_cmu.h:874
_CMU_LFXOCTRL_GAIN_SHIFT
#define _CMU_LFXOCTRL_GAIN_SHIFT
Definition: efr32mg1p_cmu.h:597
_CMU_STATUS_MASK
#define _CMU_STATUS_MASK
Definition: efr32mg1p_cmu.h:930
BUS_RegBitRead
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
Definition: em_bus.h:187
CMU_HFXOCTRL_MODE_EXTCLK
#define CMU_HFXOCTRL_MODE_EXTCLK
Definition: efr32mg1p_cmu.h:345
CMU_OSCENCMD_LFXOEN
#define CMU_OSCENCMD_LFXOEN
Definition: efr32mg1p_cmu.h:815
_CMU_LFBPRESC0_LEUART0_MASK
#define _CMU_LFBPRESC0_LEUART0_MASK
Definition: efr32mg1p_cmu.h:1566
_CMU_HFXOCTRL_MODE_MASK
#define _CMU_HFXOCTRL_MODE_MASK
Definition: efr32mg1p_cmu.h:339
CMU_LFACLKSEL_LFA_LFXO
#define CMU_LFACLKSEL_LFA_LFXO
Definition: efr32mg1p_cmu.h:891
CMU_HFXOInit
void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
Set HFXO control registers.
Definition: em_cmu.c:3379
CMU_CALCTRL_DOWNSEL_HFXO
#define CMU_CALCTRL_DOWNSEL_HFXO
Definition: efr32mg1p_cmu.h:696
CMU_HFPRESC_HFCLKLEPRESC_DIV4
#define CMU_HFPRESC_HFCLKLEPRESC_DIV4
Definition: efr32mg1p_cmu.h:1492
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
Definition: efr32mg1p_cmu.h:443
CMU_HFXOInit_TypeDef::autoStartSelOnRacWakeup
bool autoStartSelOnRacWakeup
Definition: em_cmu.h:1078
cmuHFRCOFreq_7M0Hz
Definition: em_cmu.h:222
CMU_OSCENCMD_LFRCODIS
#define CMU_OSCENCMD_LFRCODIS
Definition: efr32mg1p_cmu.h:810
CMU_LFXOInit_TypeDef::gain
uint8_t gain
Definition: em_cmu.h:1029
CMU_DBGCLKSEL_DBG_AUXHFRCO
#define CMU_DBGCLKSEL_DBG_AUXHFRCO
Definition: efr32mg1p_cmu.h:859
_ROMTABLE_PID3_REVMINORLSB_SHIFT
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
Definition: efr32mg1p_romtable.h:68
CMU_ClkDiv_TypeDef
uint32_t CMU_ClkDiv_TypeDef
Definition: em_cmu.h:167
em_common.h
General purpose utilities.
_CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT
#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT
Definition: efr32mg1p_cmu.h:426
cmuClock_LETIMER0
Definition: em_cmu.h:776
cmuClock_LFA
Definition: em_cmu.h:759
_CMU_HFCOREPRESC_PRESC_SHIFT
#define _CMU_HFCOREPRESC_PRESC_SHIFT
Definition: efr32mg1p_cmu.h:1497
CMU_Log2ToDiv
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
Definition: em_cmu.h:1449
CMU_HFCLKSEL_HF_LFXO
#define CMU_HFCLKSEL_HF_LFXO
Definition: efr32mg1p_cmu.h:876
_CMU_LFXOCTRL_MODE_SHIFT
#define _CMU_LFXOCTRL_MODE_SHIFT
Definition: efr32mg1p_cmu.h:587
_CMU_HFRCOCTRL_CLKDIV_MASK
#define _CMU_HFRCOCTRL_CLKDIV_MASK
Definition: efr32mg1p_cmu.h:234
CMU_HFRCOBandGet
CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void)
Get current HFRCO frequency.
Definition: em_cmu.c:3181
_CMU_SYNCBUSY_HFRCOBSY_SHIFT
#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT
Definition: efr32mg1p_cmu.h:1618
_CMU_STATUS_LFXOENS_SHIFT
#define _CMU_STATUS_LFXOENS_SHIFT
Definition: efr32mg1p_cmu.h:972
cmuSelect_LFXO
Definition: em_cmu.h:966
_CMU_HFPRESC_HFCLKLEPRESC_SHIFT
#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
Definition: efr32mg1p_cmu.h:1485
CMU_AUXHFRCOCTRL_CLKDIV_DIV2
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2
Definition: efr32mg1p_cmu.h:285
_CMU_LFACLKSEL_LFA_ULFRCO
#define _CMU_LFACLKSEL_LFA_ULFRCO
Definition: efr32mg1p_cmu.h:887
CMU_HFRCOCTRL_CLKDIV_DIV1
#define CMU_HFRCOCTRL_CLKDIV_DIV1
Definition: efr32mg1p_cmu.h:240
MSC_READCTRL_MODE_WS0
#define MSC_READCTRL_MODE_WS0
Definition: efr32mg1p_msc.h:134
CMU_AUXHFRCOBandGet
CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void)
Get current AUXHFRCO frequency.
Definition: em_cmu.c:828
_CMU_CALCTRL_UPSEL_MASK
#define _CMU_CALCTRL_UPSEL_MASK
Definition: efr32mg1p_cmu.h:669
_CMU_HFPERPRESC_PRESC_SHIFT
#define _CMU_HFPERPRESC_PRESC_SHIFT
Definition: efr32mg1p_cmu.h:1507
SYSTEM_GetProdRev
__STATIC_INLINE uint8_t SYSTEM_GetProdRev(void)
Get the production revision for this part.
Definition: em_system.h:303
SystemCoreClockGet
uint32_t SystemCoreClockGet(void)
Get the current core clock frequency.
Definition: system_efr32mg1p.c:137
_CMU_HFXOTRIMSTATUS_REGISH_MASK
#define _CMU_HFXOTRIMSTATUS_REGISH_MASK
Definition: efr32mg1p_cmu.h:1041
CMU_OscillatorTuningSet
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
Definition: em_cmu.c:3830
CMU_LFECLKSEL_LFE_LFXO
#define CMU_LFECLKSEL_LFE_LFXO
Definition: efr32mg1p_cmu.h:925
CMU_LFBCLKSEL_LFB_LFXO
#define CMU_LFBCLKSEL_LFB_LFXO
Definition: efr32mg1p_cmu.h:908
SYSTEM_GetFamily
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
Get family identifier of the MCU.
Definition: em_system.h:451
CMU_HFXOInit_TypeDef::autoSelEm01
bool autoSelEm01
Definition: em_cmu.h:1077
CMU_CalibrateConfig
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)
Configure clock calibration.
Definition: em_cmu.c:985
CMU_SYNCBUSY_LFECLKEN0
#define CMU_SYNCBUSY_LFECLKEN0
Definition: efr32mg1p_cmu.h:1607
_CMU_HFCLKSTATUS_SELECTED_MASK
#define _CMU_HFCLKSTATUS_SELECTED_MASK
Definition: efr32mg1p_cmu.h:1021
cmuAUXHFRCOFreq_38M0Hz
Definition: em_cmu.h:248
_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK
Definition: efr32mg1p_cmu.h:1037
SystemHfrcoFreq
uint32_t SystemHfrcoFreq
System HFRCO frequency.
Definition: system_efr32mg1p.c:113
_CMU_LFAPRESC0_LETIMER0_MASK
#define _CMU_LFAPRESC0_LETIMER0_MASK
Definition: efr32mg1p_cmu.h:1528
CMU_HFXOCTRL_LOWPOWER
#define CMU_HFXOCTRL_LOWPOWER
Definition: efr32mg1p_cmu.h:356
_CMU_AUXHFRCOCTRL_TUNING_MASK
#define _CMU_AUXHFRCOCTRL_TUNING_MASK
Definition: efr32mg1p_cmu.h:257
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
Definition: efr32mg1p_cmu.h:464
CMU_LFACLKSEL_LFA_LFRCO
#define CMU_LFACLKSEL_LFA_LFRCO
Definition: efr32mg1p_cmu.h:890
_CMU_HFPRESC_PRESC_MASK
#define _CMU_HFPRESC_PRESC_MASK
Definition: efr32mg1p_cmu.h:1480
_CMU_HFPERPRESC_PRESC_MASK
#define _CMU_HFPERPRESC_PRESC_MASK
Definition: efr32mg1p_cmu.h:1508
CMU_HFXOInit_TypeDef::timeoutPeakDetect
uint8_t timeoutPeakDetect
Definition: em_cmu.h:1086
cmuClkDiv_32768
#define cmuClkDiv_32768
Definition: em_cmu.h:164
CMU_HFRCOCTRL_CLKDIV_DIV4
#define CMU_HFRCOCTRL_CLKDIV_DIV4
Definition: efr32mg1p_cmu.h:242
_CMU_LFAPRESC0_LETIMER0_SHIFT
#define _CMU_LFAPRESC0_LETIMER0_SHIFT
Definition: efr32mg1p_cmu.h:1527
CMU_HFXOInit_TypeDef::timeoutSteady
uint8_t timeoutSteady
Definition: em_cmu.h:1087
CMU_STATUS_HFXOSHUNTOPTRDY
#define CMU_STATUS_HFXOSHUNTOPTRDY
Definition: efr32mg1p_cmu.h:996
_CMU_LFECLKSEL_LFE_SHIFT
#define _CMU_LFECLKSEL_LFE_SHIFT
Definition: efr32mg1p_cmu.h:915
SystemHFXOClockGet
uint32_t SystemHFXOClockGet(void)
Get high frequency crystal oscillator clock frequency for target system.
Definition: system_efr32mg1p.c:231
cmuSelect_HFRCO
Definition: em_cmu.h:969
_CMU_STATUS_LFRCORDY_SHIFT
#define _CMU_STATUS_LFRCORDY_SHIFT
Definition: efr32mg1p_cmu.h:967
CMU_AUXHFRCOCTRL_CLKDIV_DIV4
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4
Definition: efr32mg1p_cmu.h:286
CMU_OSCENCMD_HFXODIS
#define CMU_OSCENCMD_HFXODIS
Definition: efr32mg1p_cmu.h:790
CMU_LFACLKSEL_LFA_ULFRCO
#define CMU_LFACLKSEL_LFA_ULFRCO
Definition: efr32mg1p_cmu.h:892
SystemLFXOClockGet
uint32_t SystemLFXOClockGet(void)
Get low frequency crystal oscillator clock frequency for target system.
Definition: system_efr32mg1p.c:343
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT
Definition: efr32mg1p_cmu.h:442
CMU_CALCTRL_UPSEL_LFXO
#define CMU_CALCTRL_UPSEL_LFXO
Definition: efr32mg1p_cmu.h:679
CMU_ClockPrescGet
uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
Get clock prescaler.
Definition: em_cmu.c:1746
_CMU_LFBCLKSEL_LFB_MASK
#define _CMU_LFBCLKSEL_LFB_MASK
Definition: efr32mg1p_cmu.h:898
CMU_LCDClkFDIVGet
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
Definition: em_cmu.c:3479
CMU_DivToLog2
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
Definition: em_cmu.h:1311
cmuHFRCOFreq_4M0Hz
Definition: em_cmu.h:221
CMU_Clock_TypeDef
CMU_Clock_TypeDef
Definition: em_cmu.h:257
_CMU_LFBPRESC0_LEUART0_SHIFT
#define _CMU_LFBPRESC0_LEUART0_SHIFT
Definition: efr32mg1p_cmu.h:1565
SystemLFRCOClockGet
uint32_t SystemLFRCOClockGet(void)
Get low frequency RC oscillator clock frequency for target system.
Definition: system_efr32mg1p.c:307
CMU_CalibrateCountGet
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
Definition: em_cmu.c:1072
ROMTABLE
#define ROMTABLE
Definition: efr32mg1p233f256gm48.h:359
DEVINFO
#define DEVINFO
Definition: efr32mg1p233f256gm48.h:358
_ROMTABLE_PID0_REVMAJOR_MASK
#define _ROMTABLE_PID0_REVMAJOR_MASK
Definition: efr32mg1p_romtable.h:61
CMU_LFXOInit_TypeDef::mode
CMU_OscMode_TypeDef mode
Definition: em_cmu.h:1034
cmuClkDiv_16
#define cmuClkDiv_16
Definition: em_cmu.h:153
CMU_ClkPresc_TypeDef
uint32_t CMU_ClkPresc_TypeDef
Definition: em_cmu.h:171
CMU_SYNCBUSY_LFACLKEN0
#define CMU_SYNCBUSY_LFACLKEN0
Definition: efr32mg1p_cmu.h:1587
CMU_STATUS_HFXOENS
#define CMU_STATUS_HFXOENS
Definition: efr32mg1p_cmu.h:941
CMU_HFXOInit_TypeDef::xoCoreBiasTrimStartup
uint8_t xoCoreBiasTrimStartup
Definition: em_cmu.h:1082
CMU_IF_HFXOPEAKDETERR
#define CMU_IF_HFXOPEAKDETERR
Definition: efr32mg1p_cmu.h:1093
CMU_OSCENCMD_AUXHFRCODIS
#define CMU_OSCENCMD_AUXHFRCODIS
Definition: efr32mg1p_cmu.h:800
_CMU_DBGCLKSEL_DBG_MASK
#define _CMU_DBGCLKSEL_DBG_MASK
Definition: efr32mg1p_cmu.h:854
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT
Definition: efr32mg1p_cmu.h:422
CMU_ClockEnable
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
Definition: em_cmu.c:1453
CMU_CALCTRL_UPSEL_HFXO
#define CMU_CALCTRL_UPSEL_HFXO
Definition: efr32mg1p_cmu.h:678
CMU_SYNCBUSY_LFEPRESC0
#define CMU_SYNCBUSY_LFEPRESC0
Definition: efr32mg1p_cmu.h:1612
_CMU_LFBCLKSEL_LFB_SHIFT
#define _CMU_LFBCLKSEL_LFB_SHIFT
Definition: efr32mg1p_cmu.h:897
CMU_LCDClkFDIVSet
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
Definition: em_cmu.c:3502
_ROMTABLE_PID2_REVMINORMSB_MASK
#define _ROMTABLE_PID2_REVMINORMSB_MASK
Definition: efr32mg1p_romtable.h:65
cmuOsc_LFRCO
Definition: em_cmu.h:938
CMU_PrescToLog2
__STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
Convert prescaler dividend to logarithmic value. Only works for even numbers equal to 2^n...
Definition: em_cmu.h:1467
CMU_LFXOInit_TypeDef::ctune
uint8_t ctune
Definition: em_cmu.h:1028
_CMU_LFXOCTRL_MODE_MASK
#define _CMU_LFXOCTRL_MODE_MASK
Definition: efr32mg1p_cmu.h:588
CMU_SYNCBUSY_LFBPRESC0
#define CMU_SYNCBUSY_LFBPRESC0
Definition: efr32mg1p_cmu.h:1602
CMU_LFBCLKSEL_LFB_LFRCO
#define CMU_LFBCLKSEL_LFB_LFRCO
Definition: efr32mg1p_cmu.h:907
CMU_CALCTRL_DOWNSEL_LFRCO
#define CMU_CALCTRL_DOWNSEL_LFRCO
Definition: efr32mg1p_cmu.h:699
_CMU_LFXOCTRL_TUNING_MASK
#define _CMU_LFXOCTRL_TUNING_MASK
Definition: efr32mg1p_cmu.h:584
_CMU_LFRCOCTRL_TUNING_MASK
#define _CMU_LFRCOCTRL_TUNING_MASK
Definition: efr32mg1p_cmu.h:301
_CMU_HFBUSCLKEN0_LE_SHIFT
#define _CMU_HFBUSCLKEN0_LE_SHIFT
Definition: efr32mg1p_cmu.h:1365
cmuClkDiv_128
#define cmuClkDiv_128
Definition: em_cmu.h:156
CMU_OSCENCMD_HFRCODIS
#define CMU_OSCENCMD_HFRCODIS
Definition: efr32mg1p_cmu.h:780
CMU_OSCENCMD_AUXHFRCOEN
#define CMU_OSCENCMD_AUXHFRCOEN
Definition: efr32mg1p_cmu.h:795
CMU_HFXOInit_TypeDef::timeoutShuntOptimization
uint8_t timeoutShuntOptimization
Definition: em_cmu.h:1085
CMU_HFRCOBandSet
void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)
Set HFRCO calibration for the selected target frequency.
Definition: em_cmu.c:3194
cmuHFRCOFreq_32M0Hz
Definition: em_cmu.h:227
cmuClock_DBG
Definition: em_cmu.h:280
CMU_HFRCOFreq_TypeDef
CMU_HFRCOFreq_TypeDef
Definition: em_cmu.h:217
CMU_HFXOInit_TypeDef::ctuneStartup
uint16_t ctuneStartup
Definition: em_cmu.h:1079
systemPartFamilyEfm32Leopard
Definition: em_system.h:77
cmuClock_HF
Definition: em_cmu.h:266
cmuHFRCOFreq_19M0Hz
Definition: em_cmu.h:225
cmuOsc_HFRCO
Definition: em_cmu.h:940
BUS_RegMaskedRead
__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, uint32_t mask)
Perform a peripheral register masked read.
Definition: em_bus.h:318
EMU
#define EMU
Definition: efr32mg1p233f256gm48.h:334
CMU_OscillatorEnable
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
Definition: em_cmu.c:3594
_CMU_STATUS_HFXORDY_SHIFT
#define _CMU_STATUS_HFXORDY_SHIFT
Definition: efr32mg1p_cmu.h:947
CMU_CALCTRL_UPSEL_AUXHFRCO
#define CMU_CALCTRL_UPSEL_AUXHFRCO
Definition: efr32mg1p_cmu.h:682
cmuOsc_HFXO
Definition: em_cmu.h:939
_CMU_LFXOCTRL_TIMEOUT_MASK
#define _CMU_LFXOCTRL_TIMEOUT_MASK
Definition: efr32mg1p_cmu.h:621
_CMU_STATUS_LFXORDY_SHIFT
#define _CMU_STATUS_LFXORDY_SHIFT
Definition: efr32mg1p_cmu.h:977
em_emu.h
Energy management unit (EMU) peripheral API.
cmuAUXHFRCOFreq_16M0Hz
Definition: em_cmu.h:244
cmuSelect_Disabled
Definition: em_cmu.h:965
cmuSelect_Error
Definition: em_cmu.h:964
CMU_LFBCLKSEL_LFB_ULFRCO
#define CMU_LFBCLKSEL_LFB_ULFRCO
Definition: efr32mg1p_cmu.h:910
CMU_CALCTRL_UPSEL_LFRCO
#define CMU_CALCTRL_UPSEL_LFRCO
Definition: efr32mg1p_cmu.h:681
_CMU_HFCOREPRESC_PRESC_MASK
#define _CMU_HFCOREPRESC_PRESC_MASK
Definition: efr32mg1p_cmu.h:1498
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT
Definition: efr32mg1p_cmu.h:463
_CMU_LFACLKSEL_LFA_MASK
#define _CMU_LFACLKSEL_LFA_MASK
Definition: efr32mg1p_cmu.h:882
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
Definition: efr32mg1p_cmu.h:423
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK
Definition: efr32mg1p_cmu.h:472
CMU_HFCLKSTATUS_SELECTED_LFXO
#define CMU_HFCLKSTATUS_SELECTED_LFXO
Definition: efr32mg1p_cmu.h:1031
cmuClock_LFE
Definition: em_cmu.h:910
cmuAUXHFRCOFreq_26M0Hz
Definition: em_cmu.h:246
BUS_RegMaskedWrite
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
Definition: em_bus.h:288
CMU_IFC_HFXOPEAKDETERR
#define CMU_IFC_HFXOPEAKDETERR
Definition: efr32mg1p_cmu.h:1251
CMU_STATUS_HFXOPEAKDETRDY
#define CMU_STATUS_HFXOPEAKDETRDY
Definition: efr32mg1p_cmu.h:991
cmuClkDiv_1
#define cmuClkDiv_1
Definition: em_cmu.h:149
CMU_Osc_TypeDef
CMU_Osc_TypeDef
Definition: em_cmu.h:935
CMU_HFXOTuningMode_TypeDef
CMU_HFXOTuningMode_TypeDef
Definition: em_cmu.h:997
cmuClock_LFB
Definition: em_cmu.h:840
_CMU_LFRCOCTRL_TUNING_SHIFT
#define _CMU_LFRCOCTRL_TUNING_SHIFT
Definition: efr32mg1p_cmu.h:300
_CMU_LFEPRESC0_RTCC_SHIFT
#define _CMU_LFEPRESC0_RTCC_SHIFT
Definition: efr32mg1p_cmu.h:1579
cmuAUXHFRCOFreq_4M0Hz
Definition: em_cmu.h:241
CMU_OSCENCMD_LFXODIS
#define CMU_OSCENCMD_LFXODIS
Definition: efr32mg1p_cmu.h:820
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT
Definition: efr32mg1p_cmu.h:553
_CMU_HFRCOCTRL_TUNING_SHIFT
#define _CMU_HFRCOCTRL_TUNING_SHIFT
Definition: efr32mg1p_cmu.h:212
SL_MIN
#define SL_MIN(a, b)
Macro for getting minimum value. No sideeffects, a and b are evaluated once only. ...
Definition: em_common.h:137
em_system.h
System API.
CMU_CALCTRL_DOWNSEL_HFRCO
#define CMU_CALCTRL_DOWNSEL_HFRCO
Definition: efr32mg1p_cmu.h:698
_CMU_STATUS_HFRCORDY_SHIFT
#define _CMU_STATUS_HFRCORDY_SHIFT
Definition: efr32mg1p_cmu.h:937
_CMU_HFPRESC_PRESC_SHIFT
#define _CMU_HFPRESC_PRESC_SHIFT
Definition: efr32mg1p_cmu.h:1479
_CMU_STATUS_LFRCOENS_SHIFT
#define _CMU_STATUS_LFRCOENS_SHIFT
Definition: efr32mg1p_cmu.h:962
_CMU_LFBCLKSEL_LFB_HFCLKLE
#define _CMU_LFBCLKSEL_LFB_HFCLKLE
Definition: efr32mg1p_cmu.h:903
CMU_OscillatorTuningOptimize
bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait)
Start and optionally wait for oscillator tuning optimization.
Definition: em_cmu.c:3982
_ROMTABLE_PID2_REVMINORMSB_SHIFT
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
Definition: efr32mg1p_romtable.h:66
_CMU_AUXHFRCOCTRL_TUNING_SHIFT
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT
Definition: efr32mg1p_cmu.h:256
_CMU_HFXOCTRL_LOWPOWER_MASK
#define _CMU_HFXOCTRL_LOWPOWER_MASK
Definition: efr32mg1p_cmu.h:358
cmuOsc_AUXHFRCO
Definition: em_cmu.h:941
_CMU_STATUS_HFXOENS_SHIFT
#define _CMU_STATUS_HFXOENS_SHIFT
Definition: efr32mg1p_cmu.h:942
cmuSelect_ULFRCO
Definition: em_cmu.h:981
CMU_AUXHFRCOBandSet
void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
Set AUXHFRCO calibration for the selected target frequency.
Definition: em_cmu.c:843
CMU_AUXHFRCOCTRL_CLKDIV_DIV1
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1
Definition: efr32mg1p_cmu.h:284
BUS_RegBitWrite
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
_CMU_LFXOCTRL_TUNING_SHIFT
#define _CMU_LFXOCTRL_TUNING_SHIFT
Definition: efr32mg1p_cmu.h:583
cmuClkDiv_512
#define cmuClkDiv_512
Definition: em_cmu.h:158
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
Definition: efr32mg1p_cmu.h:498
CMU_OscillatorTuningGet
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
Definition: em_cmu.c:3772
CMU_CALCTRL_DOWNSEL_LFXO
#define CMU_CALCTRL_DOWNSEL_LFXO
Definition: efr32mg1p_cmu.h:697
cmuOsc_LFXO
Definition: em_cmu.h:937
CMU_LFXOInit
void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)
Set LFXO control registers.
Definition: em_cmu.c:3534
_CMU_STATUS_AUXHFRCOENS_SHIFT
#define _CMU_STATUS_AUXHFRCOENS_SHIFT
Definition: efr32mg1p_cmu.h:952
CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0
Definition: efr32mg1p_cmu.h:1677
_ROMTABLE_PID3_REVMINORLSB_MASK
#define _ROMTABLE_PID3_REVMINORLSB_MASK
Definition: efr32mg1p_romtable.h:67
SystemULFRCOClockGet
uint32_t SystemULFRCOClockGet(void)
Get ultra low frequency RC oscillator clock frequency for target system.
Definition: system_efr32mg1p.c:326
_CMU_STATUS_CALRDY_SHIFT
#define _CMU_STATUS_CALRDY_SHIFT
Definition: efr32mg1p_cmu.h:982
_CMU_STATUS_HFRCOENS_SHIFT
#define _CMU_STATUS_HFRCOENS_SHIFT
Definition: efr32mg1p_cmu.h:932
CMU_HFCLKSTATUS_SELECTED_HFXO
#define CMU_HFCLKSTATUS_SELECTED_HFXO
Definition: efr32mg1p_cmu.h:1029
_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
Definition: efr32mg1p_cmu.h:451
CMU_SYNCBUSY_LFBCLKEN0
#define CMU_SYNCBUSY_LFBCLKEN0
Definition: efr32mg1p_cmu.h:1597
cmuHFRCOFreq_13M0Hz
Definition: em_cmu.h:223
CMU
#define CMU
Definition: efr32mg1p233f256gm48.h:336
SystemMaxCoreClockGet
uint32_t SystemMaxCoreClockGet(void)
Get the maximum core clock frequency.
Definition: system_efr32mg1p.c:164
_CMU_HFXOCTRL1_PEAKDETTHR_MASK
#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK
Definition: efr32mg1p_cmu.h:406
CMU_HFXOInit_TypeDef::autoStartEm01
bool autoStartEm01
Definition: em_cmu.h:1076
_CMU_HFEXPPRESC_PRESC_SHIFT
#define _CMU_HFEXPPRESC_PRESC_SHIFT
Definition: efr32mg1p_cmu.h:1517
CMU_HFXOInit_TypeDef::ctuneSteadyState
uint16_t ctuneSteadyState
Definition: em_cmu.h:1080
CMU_PCNTClockExternalGet
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
Definition: em_cmu.c:4019
CMU_ClockFreqGet
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
Definition: em_cmu.c:1550
PCNT_COUNT
#define PCNT_COUNT
Definition: efr32mg1p233f256gm48.h:207
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT
Definition: efr32mg1p_cmu.h:497
CMU_OscillatorTuningWait
bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode)
Wait for oscillator tuning optimization.
Definition: em_cmu.c:3918
_MSC_READCTRL_MODE_MASK
#define _MSC_READCTRL_MODE_MASK
Definition: efr32mg1p_msc.h:130
CMU_HFXOInit_TypeDef::mode
CMU_OscMode_TypeDef mode
Definition: em_cmu.h:1094
_CMU_CALCTRL_DOWNSEL_MASK
#define _CMU_CALCTRL_DOWNSEL_MASK
Definition: efr32mg1p_cmu.h:685
_CMU_CALCTRL_CONT_SHIFT
#define _CMU_CALCTRL_CONT_SHIFT
Definition: efr32mg1p_cmu.h:703
CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD
Definition: efr32mg1p_cmu.h:354
cmuAUXHFRCOFreq_13M0Hz
Definition: em_cmu.h:243
CMU_HFXOAutostartEnable
void CMU_HFXOAutostartEnable(uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel)
Enable or disable HFXO autostart.
Definition: em_cmu.c:3330
CMU_LFECLKSEL_LFE_LFRCO
#define CMU_LFECLKSEL_LFE_LFRCO
Definition: efr32mg1p_cmu.h:924
CMU_HFCLKSTATUS_SELECTED_LFRCO
#define CMU_HFCLKSTATUS_SELECTED_LFRCO
Definition: efr32mg1p_cmu.h:1030
CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD
Definition: efr32mg1p_cmu.h:353
cmuClock_HFLE
Definition: em_cmu.h:373
CMU_LFECLKSEL_LFE_ULFRCO
#define CMU_LFECLKSEL_LFE_ULFRCO
Definition: efr32mg1p_cmu.h:926
CMU_ClockDivSet
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
Definition: em_cmu.c:1244
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
Definition: efr32mg1p_cmu.h:393
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
Definition: efr32mg1p_cmu.h:528
CMU_OSCENCMD_LFRCOEN
#define CMU_OSCENCMD_LFRCOEN
Definition: efr32mg1p_cmu.h:805
cmuHFRCOFreq_26M0Hz
Definition: em_cmu.h:226
_CMU_HFRCOCTRL_TUNING_MASK
#define _CMU_HFRCOCTRL_TUNING_MASK
Definition: efr32mg1p_cmu.h:213
_CMU_LFEPRESC0_RTCC_MASK
#define _CMU_LFEPRESC0_RTCC_MASK
Definition: efr32mg1p_cmu.h:1580
CMU_ClockDivGet
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
Definition: em_cmu.c:1112
CMU_ClockSelectGet
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.
Definition: em_cmu.c:2146