EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
efr32mg1p_cmu.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
45  uint32_t RESERVED0[3];
46  __IOM uint32_t HFRCOCTRL;
48  uint32_t RESERVED1[1];
49  __IOM uint32_t AUXHFRCOCTRL;
51  uint32_t RESERVED2[1];
52  __IOM uint32_t LFRCOCTRL;
53  __IOM uint32_t HFXOCTRL;
54  __IOM uint32_t HFXOCTRL1;
55  __IOM uint32_t HFXOSTARTUPCTRL;
56  __IOM uint32_t HFXOSTEADYSTATECTRL;
57  __IOM uint32_t HFXOTIMEOUTCTRL;
58  __IOM uint32_t LFXOCTRL;
59  __IOM uint32_t ULFRCOCTRL;
61  uint32_t RESERVED3[4];
62  __IOM uint32_t CALCTRL;
63  __IOM uint32_t CALCNT;
64  uint32_t RESERVED4[2];
65  __IOM uint32_t OSCENCMD;
66  __IOM uint32_t CMD;
67  uint32_t RESERVED5[2];
68  __IOM uint32_t DBGCLKSEL;
69  __IOM uint32_t HFCLKSEL;
70  uint32_t RESERVED6[2];
71  __IOM uint32_t LFACLKSEL;
72  __IOM uint32_t LFBCLKSEL;
73  __IOM uint32_t LFECLKSEL;
75  uint32_t RESERVED7[1];
76  __IM uint32_t STATUS;
77  __IM uint32_t HFCLKSTATUS;
78  uint32_t RESERVED8[1];
79  __IM uint32_t HFXOTRIMSTATUS;
80  __IM uint32_t IF;
81  __IOM uint32_t IFS;
82  __IOM uint32_t IFC;
83  __IOM uint32_t IEN;
84  __IOM uint32_t HFBUSCLKEN0;
86  uint32_t RESERVED9[3];
87  __IOM uint32_t HFPERCLKEN0;
89  uint32_t RESERVED10[7];
90  __IOM uint32_t LFACLKEN0;
91  uint32_t RESERVED11[1];
92  __IOM uint32_t LFBCLKEN0;
94  uint32_t RESERVED12[1];
95  __IOM uint32_t LFECLKEN0;
96  uint32_t RESERVED13[3];
97  __IOM uint32_t HFPRESC;
99  uint32_t RESERVED14[1];
100  __IOM uint32_t HFCOREPRESC;
101  __IOM uint32_t HFPERPRESC;
103  uint32_t RESERVED15[1];
104  __IOM uint32_t HFEXPPRESC;
106  uint32_t RESERVED16[2];
107  __IOM uint32_t LFAPRESC0;
108  uint32_t RESERVED17[1];
109  __IOM uint32_t LFBPRESC0;
110  uint32_t RESERVED18[1];
111  __IOM uint32_t LFEPRESC0;
113  uint32_t RESERVED19[3];
114  __IM uint32_t SYNCBUSY;
115  __IOM uint32_t FREEZE;
116  uint32_t RESERVED20[2];
117  __IOM uint32_t PCNTCTRL;
119  uint32_t RESERVED21[2];
120  __IOM uint32_t ADCCTRL;
122  uint32_t RESERVED22[4];
123  __IOM uint32_t ROUTEPEN;
124  __IOM uint32_t ROUTELOC0;
126  uint32_t RESERVED23[2];
127  __IOM uint32_t LOCK;
128 } CMU_TypeDef;
130 /**************************************************************************/
135 /* Bit fields for CMU CTRL */
136 #define _CMU_CTRL_RESETVALUE 0x00300000UL
137 #define _CMU_CTRL_MASK 0x001101EFUL
138 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0
139 #define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL
140 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
141 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL
142 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL
143 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL
144 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL
145 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL
146 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL
147 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL
148 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL
149 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL
150 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL
151 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL
152 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL
153 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL
154 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0)
155 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0)
156 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0)
157 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0)
158 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0)
159 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0)
160 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0)
161 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0)
162 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0)
163 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0)
164 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0)
165 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0)
166 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0)
167 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0)
168 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5
169 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL
170 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
171 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL
172 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL
173 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL
174 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL
175 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL
176 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL
177 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL
178 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL
179 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL
180 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL
181 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL
182 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL
183 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL
184 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5)
185 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5)
186 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5)
187 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5)
188 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5)
189 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5)
190 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5)
191 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5)
192 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5)
193 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5)
194 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5)
195 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5)
196 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5)
197 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5)
198 #define CMU_CTRL_WSHFLE (0x1UL << 16)
199 #define _CMU_CTRL_WSHFLE_SHIFT 16
200 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL
201 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL
202 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16)
203 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20)
204 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20
205 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL
206 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL
207 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20)
209 /* Bit fields for CMU HFRCOCTRL */
210 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F3CUL
211 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL
212 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
213 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL
214 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000003CUL
215 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
216 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8
217 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL
218 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL
219 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8)
220 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16
221 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL
222 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL
223 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16)
224 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21
225 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL
226 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL
227 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21)
228 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24)
229 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24
230 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL
231 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL
232 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24)
233 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25
234 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL
235 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL
236 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL
237 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL
238 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL
239 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25)
240 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25)
241 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25)
242 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25)
243 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27)
244 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27
245 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL
246 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL
247 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
248 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28
249 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL
250 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL
251 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28)
253 /* Bit fields for CMU AUXHFRCOCTRL */
254 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F3CUL
255 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL
256 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
257 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL
258 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000003CUL
259 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
260 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8
261 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL
262 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL
263 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8)
264 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16
265 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL
266 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL
267 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16)
268 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21
269 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL
270 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL
271 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21)
272 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24)
273 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24
274 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL
275 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL
276 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24)
277 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25
278 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL
279 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL
280 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL
281 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL
282 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL
283 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25)
284 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25)
285 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25)
286 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25)
287 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27)
288 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27
289 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL
290 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL
291 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
292 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28
293 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL
294 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL
295 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28)
297 /* Bit fields for CMU LFRCOCTRL */
298 #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL
299 #define _CMU_LFRCOCTRL_MASK 0xF30701FFUL
300 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
301 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL
302 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL
303 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
304 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16)
305 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16
306 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL
307 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL
308 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16)
309 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17)
310 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17
311 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL
312 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL
313 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17)
314 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18)
315 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18
316 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL
317 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL
318 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18)
319 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24
320 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL
321 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL
322 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL
323 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL
324 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL
325 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24)
326 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24)
327 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24)
328 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24)
329 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28
330 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL
331 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL
332 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28)
334 /* Bit fields for CMU HFXOCTRL */
335 #define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL
336 #define _CMU_HFXOCTRL_MASK 0x37000731UL
337 #define CMU_HFXOCTRL_MODE (0x1UL << 0)
338 #define _CMU_HFXOCTRL_MODE_SHIFT 0
339 #define _CMU_HFXOCTRL_MODE_MASK 0x1UL
340 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL
341 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL
342 #define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL
343 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0)
344 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0)
345 #define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0)
346 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4
347 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL
348 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL
349 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL
350 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL
351 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL
352 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4)
353 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4)
354 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4)
355 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4)
356 #define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8)
357 #define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8
358 #define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL
359 #define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL
360 #define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8)
361 #define CMU_HFXOCTRL_XTI2GND (0x1UL << 9)
362 #define _CMU_HFXOCTRL_XTI2GND_SHIFT 9
363 #define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL
364 #define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL
365 #define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9)
366 #define CMU_HFXOCTRL_XTO2GND (0x1UL << 10)
367 #define _CMU_HFXOCTRL_XTO2GND_SHIFT 10
368 #define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL
369 #define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL
370 #define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10)
371 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24
372 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL
373 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL
374 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL
375 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL
376 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL
377 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL
378 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL
379 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL
380 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL
381 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL
382 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24)
383 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24)
384 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24)
385 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24)
386 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24)
387 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24)
388 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24)
389 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24)
390 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24)
391 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28)
392 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28
393 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL
394 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL
395 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28)
396 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29)
397 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29
398 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL
399 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL
400 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29)
402 /* Bit fields for CMU HFXOCTRL1 */
403 #define _CMU_HFXOCTRL1_RESETVALUE 0x00000240UL
404 #define _CMU_HFXOCTRL1_MASK 0x00000277UL
405 #define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 0
406 #define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7UL
407 #define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000000UL
408 #define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 0)
409 #define _CMU_HFXOCTRL1_REGLVL_SHIFT 4
410 #define _CMU_HFXOCTRL1_REGLVL_MASK 0x70UL
411 #define _CMU_HFXOCTRL1_REGLVL_DEFAULT 0x00000004UL
412 #define CMU_HFXOCTRL1_REGLVL_DEFAULT (_CMU_HFXOCTRL1_REGLVL_DEFAULT << 4)
413 #define CMU_HFXOCTRL1_XTIBIASEN (0x1UL << 9)
414 #define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT 9
415 #define _CMU_HFXOCTRL1_XTIBIASEN_MASK 0x200UL
416 #define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT 0x00000001UL
417 #define CMU_HFXOCTRL1_XTIBIASEN_DEFAULT (_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT << 9)
419 /* Bit fields for CMU HFXOSTARTUPCTRL */
420 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0xA1250060UL
421 #define _CMU_HFXOSTARTUPCTRL_MASK 0xFFEFF87FUL
422 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0
423 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL
424 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000060UL
425 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0)
426 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11
427 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL
428 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL
429 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11)
430 #define _CMU_HFXOSTARTUPCTRL_RESERVED0_SHIFT 21
431 #define _CMU_HFXOSTARTUPCTRL_RESERVED0_MASK 0xFE00000UL
432 #define _CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT 0x00000009UL
433 #define CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT (_CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT << 21)
434 #define _CMU_HFXOSTARTUPCTRL_RESERVED1_SHIFT 28
435 #define _CMU_HFXOSTARTUPCTRL_RESERVED1_MASK 0xF0000000UL
436 #define _CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT 0x0000000AUL
437 #define CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT (_CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT << 28)
439 /* Bit fields for CMU HFXOSTEADYSTATECTRL */
440 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30AAD09UL
441 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL
442 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0
443 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL
444 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000009UL
445 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0)
446 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7
447 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL
448 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL
449 #define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7)
450 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11
451 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL
452 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000155UL
453 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11)
454 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24
455 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL
456 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL
457 #define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24)
458 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26)
459 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26
460 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL
461 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL
462 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26)
463 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28
464 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL
465 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL
466 #define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28)
468 /* Bit fields for CMU HFXOTIMEOUTCTRL */
469 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x00026667UL
470 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FFFFFUL
471 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0
472 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL
473 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL
474 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL
475 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL
476 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL
477 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL
478 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL
479 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL
480 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL
481 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL
482 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL
483 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL
484 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL
485 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0)
486 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0)
487 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0)
488 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0)
489 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0)
490 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0)
491 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0)
492 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0)
493 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0)
494 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0)
495 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0)
496 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0)
497 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4
498 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL
499 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL
500 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL
501 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL
502 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL
503 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL
504 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL
505 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL
506 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL
507 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL
508 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL
509 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL
510 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL
511 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4)
512 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4)
513 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4)
514 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4)
515 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4)
516 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4)
517 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4)
518 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4)
519 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4)
520 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4)
521 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4)
522 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4)
523 #define _CMU_HFXOTIMEOUTCTRL_RESERVED2_SHIFT 8
524 #define _CMU_HFXOTIMEOUTCTRL_RESERVED2_MASK 0xF00UL
525 #define _CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT 0x00000006UL
526 #define CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT (_CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT << 8)
527 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12
528 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL
529 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL
530 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL
531 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL
532 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL
533 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL
534 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL
535 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x00000006UL
536 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL
537 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL
538 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL
539 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL
540 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL
541 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12)
542 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12)
543 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12)
544 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12)
545 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12)
546 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12)
547 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12)
548 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12)
549 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12)
550 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12)
551 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12)
552 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12)
553 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16
554 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL
555 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL
556 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL
557 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL
558 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL
559 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL
560 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL
561 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL
562 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL
563 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL
564 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL
565 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL
566 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL
567 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16)
568 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16)
569 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16)
570 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16)
571 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16)
572 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16)
573 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16)
574 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16)
575 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16)
576 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16)
577 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16)
578 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16)
580 /* Bit fields for CMU LFXOCTRL */
581 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL
582 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL
583 #define _CMU_LFXOCTRL_TUNING_SHIFT 0
584 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL
585 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL
586 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0)
587 #define _CMU_LFXOCTRL_MODE_SHIFT 8
588 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL
589 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL
590 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL
591 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL
592 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL
593 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8)
594 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8)
595 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8)
596 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8)
597 #define _CMU_LFXOCTRL_GAIN_SHIFT 11
598 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL
599 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL
600 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11)
601 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14)
602 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14
603 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL
604 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL
605 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14)
606 #define CMU_LFXOCTRL_AGC (0x1UL << 15)
607 #define _CMU_LFXOCTRL_AGC_SHIFT 15
608 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL
609 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL
610 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15)
611 #define _CMU_LFXOCTRL_CUR_SHIFT 16
612 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL
613 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL
614 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16)
615 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20)
616 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20
617 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL
618 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL
619 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20)
620 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24
621 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL
622 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL
623 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL
624 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL
625 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL
626 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL
627 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL
628 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL
629 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL
630 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL
631 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24)
632 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24)
633 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24)
634 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24)
635 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24)
636 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24)
637 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24)
638 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24)
639 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24)
641 /* Bit fields for CMU ULFRCOCTRL */
642 #define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL
643 #define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL
644 #define _CMU_ULFRCOCTRL_TUNING_SHIFT 0
645 #define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL
646 #define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL
647 #define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0)
648 #define _CMU_ULFRCOCTRL_MODE_SHIFT 10
649 #define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL
650 #define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL
651 #define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL
652 #define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL
653 #define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL
654 #define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL
655 #define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10)
656 #define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10)
657 #define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10)
658 #define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10)
659 #define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10)
660 #define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16
661 #define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL
662 #define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL
663 #define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16)
665 /* Bit fields for CMU CALCTRL */
666 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
667 #define _CMU_CALCTRL_MASK 0x0F0F0177UL
668 #define _CMU_CALCTRL_UPSEL_SHIFT 0
669 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
670 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
671 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
672 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
673 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
674 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
675 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
676 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL
677 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
678 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
679 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
680 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
681 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
682 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
683 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0)
684 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4
685 #define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL
686 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
687 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
688 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
689 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
690 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
691 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
692 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
693 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL
694 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4)
695 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4)
696 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4)
697 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4)
698 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4)
699 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4)
700 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4)
701 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4)
702 #define CMU_CALCTRL_CONT (0x1UL << 8)
703 #define _CMU_CALCTRL_CONT_SHIFT 8
704 #define _CMU_CALCTRL_CONT_MASK 0x100UL
705 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
706 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8)
707 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16
708 #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL
709 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL
710 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL
711 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL
712 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL
713 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL
714 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL
715 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL
716 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL
717 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL
718 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL
719 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL
720 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL
721 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL
722 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16)
723 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16)
724 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16)
725 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16)
726 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16)
727 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16)
728 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16)
729 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16)
730 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16)
731 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16)
732 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16)
733 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16)
734 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16)
735 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24
736 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL
737 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL
738 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL
739 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL
740 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL
741 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL
742 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL
743 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL
744 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL
745 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL
746 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL
747 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL
748 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL
749 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL
750 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24)
751 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24)
752 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24)
753 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24)
754 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24)
755 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24)
756 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24)
757 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24)
758 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24)
759 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24)
760 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24)
761 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24)
762 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24)
764 /* Bit fields for CMU CALCNT */
765 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
766 #define _CMU_CALCNT_MASK 0x000FFFFFUL
767 #define _CMU_CALCNT_CALCNT_SHIFT 0
768 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
769 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
770 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
772 /* Bit fields for CMU OSCENCMD */
773 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
774 #define _CMU_OSCENCMD_MASK 0x000003FFUL
775 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
776 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
777 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
778 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
779 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
780 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
781 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
782 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
783 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
784 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
785 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
786 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
787 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
788 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
789 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
790 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
791 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
792 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
793 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
794 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
795 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
796 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
797 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
798 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
799 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
800 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
801 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
802 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
803 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
804 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
805 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
806 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
807 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
808 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
809 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
810 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
811 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
812 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
813 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
814 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
815 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
816 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
817 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
818 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
819 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
820 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
821 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
822 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
823 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
824 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
826 /* Bit fields for CMU CMD */
827 #define _CMU_CMD_RESETVALUE 0x00000000UL
828 #define _CMU_CMD_MASK 0x00000033UL
829 #define CMU_CMD_CALSTART (0x1UL << 0)
830 #define _CMU_CMD_CALSTART_SHIFT 0
831 #define _CMU_CMD_CALSTART_MASK 0x1UL
832 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
833 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0)
834 #define CMU_CMD_CALSTOP (0x1UL << 1)
835 #define _CMU_CMD_CALSTOP_SHIFT 1
836 #define _CMU_CMD_CALSTOP_MASK 0x2UL
837 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
838 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1)
839 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4)
840 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4
841 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL
842 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL
843 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4)
844 #define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5)
845 #define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5
846 #define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL
847 #define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL
848 #define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5)
850 /* Bit fields for CMU DBGCLKSEL */
851 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL
852 #define _CMU_DBGCLKSEL_MASK 0x00000001UL
853 #define _CMU_DBGCLKSEL_DBG_SHIFT 0
854 #define _CMU_DBGCLKSEL_DBG_MASK 0x1UL
855 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL
856 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL
857 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL
858 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0)
859 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0)
860 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0)
862 /* Bit fields for CMU HFCLKSEL */
863 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL
864 #define _CMU_HFCLKSEL_MASK 0x00000007UL
865 #define _CMU_HFCLKSEL_HF_SHIFT 0
866 #define _CMU_HFCLKSEL_HF_MASK 0x7UL
867 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL
868 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL
869 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL
870 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL
871 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL
872 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0)
873 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0)
874 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0)
875 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0)
876 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0)
878 /* Bit fields for CMU LFACLKSEL */
879 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL
880 #define _CMU_LFACLKSEL_MASK 0x00000007UL
881 #define _CMU_LFACLKSEL_LFA_SHIFT 0
882 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL
883 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL
884 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL
885 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL
886 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL
887 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL
888 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0)
889 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0)
890 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0)
891 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0)
892 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0)
894 /* Bit fields for CMU LFBCLKSEL */
895 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL
896 #define _CMU_LFBCLKSEL_MASK 0x00000007UL
897 #define _CMU_LFBCLKSEL_LFB_SHIFT 0
898 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL
899 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL
900 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL
901 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL
902 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL
903 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL
904 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL
905 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0)
906 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0)
907 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0)
908 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0)
909 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0)
910 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0)
912 /* Bit fields for CMU LFECLKSEL */
913 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL
914 #define _CMU_LFECLKSEL_MASK 0x00000007UL
915 #define _CMU_LFECLKSEL_LFE_SHIFT 0
916 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL
917 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL
918 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL
919 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL
920 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL
921 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL
922 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0)
923 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0)
924 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0)
925 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0)
926 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0)
928 /* Bit fields for CMU STATUS */
929 #define _CMU_STATUS_RESETVALUE 0x00010003UL
930 #define _CMU_STATUS_MASK 0x07E103FFUL
931 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
932 #define _CMU_STATUS_HFRCOENS_SHIFT 0
933 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
934 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
935 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
936 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
937 #define _CMU_STATUS_HFRCORDY_SHIFT 1
938 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
939 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
940 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
941 #define CMU_STATUS_HFXOENS (0x1UL << 2)
942 #define _CMU_STATUS_HFXOENS_SHIFT 2
943 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
944 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
945 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
946 #define CMU_STATUS_HFXORDY (0x1UL << 3)
947 #define _CMU_STATUS_HFXORDY_SHIFT 3
948 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
949 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
950 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
951 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
952 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
953 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
954 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
955 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
956 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
957 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
958 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
959 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
960 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
961 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
962 #define _CMU_STATUS_LFRCOENS_SHIFT 6
963 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
964 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
965 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
966 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
967 #define _CMU_STATUS_LFRCORDY_SHIFT 7
968 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
969 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
970 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
971 #define CMU_STATUS_LFXOENS (0x1UL << 8)
972 #define _CMU_STATUS_LFXOENS_SHIFT 8
973 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
974 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
975 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
976 #define CMU_STATUS_LFXORDY (0x1UL << 9)
977 #define _CMU_STATUS_LFXORDY_SHIFT 9
978 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
979 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
980 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
981 #define CMU_STATUS_CALRDY (0x1UL << 16)
982 #define _CMU_STATUS_CALRDY_SHIFT 16
983 #define _CMU_STATUS_CALRDY_MASK 0x10000UL
984 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL
985 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16)
986 #define CMU_STATUS_HFXOREQ (0x1UL << 21)
987 #define _CMU_STATUS_HFXOREQ_SHIFT 21
988 #define _CMU_STATUS_HFXOREQ_MASK 0x200000UL
989 #define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL
990 #define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21)
991 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22)
992 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22
993 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL
994 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
995 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22)
996 #define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23)
997 #define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23
998 #define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL
999 #define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1000 #define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23)
1001 #define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24)
1002 #define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24
1003 #define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL
1004 #define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL
1005 #define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24)
1006 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25)
1007 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25
1008 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL
1009 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL
1010 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25)
1011 #define CMU_STATUS_HFXOREGILOW (0x1UL << 26)
1012 #define _CMU_STATUS_HFXOREGILOW_SHIFT 26
1013 #define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL
1014 #define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL
1015 #define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26)
1017 /* Bit fields for CMU HFCLKSTATUS */
1018 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL
1019 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL
1020 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0
1021 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL
1022 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL
1023 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL
1024 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL
1025 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL
1026 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL
1027 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0)
1028 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0)
1029 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0)
1030 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0)
1031 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0)
1033 /* Bit fields for CMU HFXOTRIMSTATUS */
1034 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL
1035 #define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL
1036 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0
1037 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL
1038 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL
1039 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0)
1040 #define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7
1041 #define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL
1042 #define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL
1043 #define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7)
1045 /* Bit fields for CMU IF */
1046 #define _CMU_IF_RESETVALUE 0x00000001UL
1047 #define _CMU_IF_MASK 0x80007F7FUL
1048 #define CMU_IF_HFRCORDY (0x1UL << 0)
1049 #define _CMU_IF_HFRCORDY_SHIFT 0
1050 #define _CMU_IF_HFRCORDY_MASK 0x1UL
1051 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
1052 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
1053 #define CMU_IF_HFXORDY (0x1UL << 1)
1054 #define _CMU_IF_HFXORDY_SHIFT 1
1055 #define _CMU_IF_HFXORDY_MASK 0x2UL
1056 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
1057 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
1058 #define CMU_IF_LFRCORDY (0x1UL << 2)
1059 #define _CMU_IF_LFRCORDY_SHIFT 2
1060 #define _CMU_IF_LFRCORDY_MASK 0x4UL
1061 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
1062 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
1063 #define CMU_IF_LFXORDY (0x1UL << 3)
1064 #define _CMU_IF_LFXORDY_SHIFT 3
1065 #define _CMU_IF_LFXORDY_MASK 0x8UL
1066 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
1067 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
1068 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
1069 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
1070 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
1071 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
1072 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
1073 #define CMU_IF_CALRDY (0x1UL << 5)
1074 #define _CMU_IF_CALRDY_SHIFT 5
1075 #define _CMU_IF_CALRDY_MASK 0x20UL
1076 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
1077 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
1078 #define CMU_IF_CALOF (0x1UL << 6)
1079 #define _CMU_IF_CALOF_SHIFT 6
1080 #define _CMU_IF_CALOF_MASK 0x40UL
1081 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
1082 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
1083 #define CMU_IF_HFXODISERR (0x1UL << 8)
1084 #define _CMU_IF_HFXODISERR_SHIFT 8
1085 #define _CMU_IF_HFXODISERR_MASK 0x100UL
1086 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL
1087 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8)
1088 #define CMU_IF_HFXOAUTOSW (0x1UL << 9)
1089 #define _CMU_IF_HFXOAUTOSW_SHIFT 9
1090 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL
1091 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL
1092 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9)
1093 #define CMU_IF_HFXOPEAKDETERR (0x1UL << 10)
1094 #define _CMU_IF_HFXOPEAKDETERR_SHIFT 10
1095 #define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL
1096 #define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1097 #define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10)
1098 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11)
1099 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11
1100 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL
1101 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1102 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11)
1103 #define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12)
1104 #define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12
1105 #define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL
1106 #define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1107 #define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12)
1108 #define CMU_IF_HFRCODIS (0x1UL << 13)
1109 #define _CMU_IF_HFRCODIS_SHIFT 13
1110 #define _CMU_IF_HFRCODIS_MASK 0x2000UL
1111 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL
1112 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13)
1113 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14)
1114 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14
1115 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL
1116 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL
1117 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14)
1118 #define CMU_IF_CMUERR (0x1UL << 31)
1119 #define _CMU_IF_CMUERR_SHIFT 31
1120 #define _CMU_IF_CMUERR_MASK 0x80000000UL
1121 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL
1122 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31)
1124 /* Bit fields for CMU IFS */
1125 #define _CMU_IFS_RESETVALUE 0x00000000UL
1126 #define _CMU_IFS_MASK 0x80007F7FUL
1127 #define CMU_IFS_HFRCORDY (0x1UL << 0)
1128 #define _CMU_IFS_HFRCORDY_SHIFT 0
1129 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
1130 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
1131 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
1132 #define CMU_IFS_HFXORDY (0x1UL << 1)
1133 #define _CMU_IFS_HFXORDY_SHIFT 1
1134 #define _CMU_IFS_HFXORDY_MASK 0x2UL
1135 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
1136 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
1137 #define CMU_IFS_LFRCORDY (0x1UL << 2)
1138 #define _CMU_IFS_LFRCORDY_SHIFT 2
1139 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
1140 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
1141 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
1142 #define CMU_IFS_LFXORDY (0x1UL << 3)
1143 #define _CMU_IFS_LFXORDY_SHIFT 3
1144 #define _CMU_IFS_LFXORDY_MASK 0x8UL
1145 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
1146 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
1147 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
1148 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
1149 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
1150 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
1151 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
1152 #define CMU_IFS_CALRDY (0x1UL << 5)
1153 #define _CMU_IFS_CALRDY_SHIFT 5
1154 #define _CMU_IFS_CALRDY_MASK 0x20UL
1155 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
1156 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
1157 #define CMU_IFS_CALOF (0x1UL << 6)
1158 #define _CMU_IFS_CALOF_SHIFT 6
1159 #define _CMU_IFS_CALOF_MASK 0x40UL
1160 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
1161 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
1162 #define CMU_IFS_HFXODISERR (0x1UL << 8)
1163 #define _CMU_IFS_HFXODISERR_SHIFT 8
1164 #define _CMU_IFS_HFXODISERR_MASK 0x100UL
1165 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL
1166 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8)
1167 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9)
1168 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9
1169 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL
1170 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL
1171 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9)
1172 #define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10)
1173 #define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10
1174 #define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL
1175 #define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1176 #define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10)
1177 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11)
1178 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11
1179 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL
1180 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1181 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11)
1182 #define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12)
1183 #define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12
1184 #define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL
1185 #define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1186 #define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12)
1187 #define CMU_IFS_HFRCODIS (0x1UL << 13)
1188 #define _CMU_IFS_HFRCODIS_SHIFT 13
1189 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL
1190 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL
1191 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13)
1192 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14)
1193 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14
1194 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL
1195 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL
1196 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14)
1197 #define CMU_IFS_CMUERR (0x1UL << 31)
1198 #define _CMU_IFS_CMUERR_SHIFT 31
1199 #define _CMU_IFS_CMUERR_MASK 0x80000000UL
1200 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL
1201 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31)
1203 /* Bit fields for CMU IFC */
1204 #define _CMU_IFC_RESETVALUE 0x00000000UL
1205 #define _CMU_IFC_MASK 0x80007F7FUL
1206 #define CMU_IFC_HFRCORDY (0x1UL << 0)
1207 #define _CMU_IFC_HFRCORDY_SHIFT 0
1208 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
1209 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
1210 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
1211 #define CMU_IFC_HFXORDY (0x1UL << 1)
1212 #define _CMU_IFC_HFXORDY_SHIFT 1
1213 #define _CMU_IFC_HFXORDY_MASK 0x2UL
1214 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
1215 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
1216 #define CMU_IFC_LFRCORDY (0x1UL << 2)
1217 #define _CMU_IFC_LFRCORDY_SHIFT 2
1218 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
1219 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
1220 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
1221 #define CMU_IFC_LFXORDY (0x1UL << 3)
1222 #define _CMU_IFC_LFXORDY_SHIFT 3
1223 #define _CMU_IFC_LFXORDY_MASK 0x8UL
1224 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
1225 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
1226 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
1227 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
1228 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
1229 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
1230 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
1231 #define CMU_IFC_CALRDY (0x1UL << 5)
1232 #define _CMU_IFC_CALRDY_SHIFT 5
1233 #define _CMU_IFC_CALRDY_MASK 0x20UL
1234 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
1235 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
1236 #define CMU_IFC_CALOF (0x1UL << 6)
1237 #define _CMU_IFC_CALOF_SHIFT 6
1238 #define _CMU_IFC_CALOF_MASK 0x40UL
1239 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
1240 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
1241 #define CMU_IFC_HFXODISERR (0x1UL << 8)
1242 #define _CMU_IFC_HFXODISERR_SHIFT 8
1243 #define _CMU_IFC_HFXODISERR_MASK 0x100UL
1244 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL
1245 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8)
1246 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9)
1247 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9
1248 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL
1249 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL
1250 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9)
1251 #define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10)
1252 #define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10
1253 #define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL
1254 #define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1255 #define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10)
1256 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11)
1257 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11
1258 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL
1259 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1260 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11)
1261 #define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12)
1262 #define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12
1263 #define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL
1264 #define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1265 #define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12)
1266 #define CMU_IFC_HFRCODIS (0x1UL << 13)
1267 #define _CMU_IFC_HFRCODIS_SHIFT 13
1268 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL
1269 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL
1270 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13)
1271 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14)
1272 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14
1273 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL
1274 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL
1275 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14)
1276 #define CMU_IFC_CMUERR (0x1UL << 31)
1277 #define _CMU_IFC_CMUERR_SHIFT 31
1278 #define _CMU_IFC_CMUERR_MASK 0x80000000UL
1279 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL
1280 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31)
1282 /* Bit fields for CMU IEN */
1283 #define _CMU_IEN_RESETVALUE 0x00000000UL
1284 #define _CMU_IEN_MASK 0x80007F7FUL
1285 #define CMU_IEN_HFRCORDY (0x1UL << 0)
1286 #define _CMU_IEN_HFRCORDY_SHIFT 0
1287 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
1288 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
1289 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
1290 #define CMU_IEN_HFXORDY (0x1UL << 1)
1291 #define _CMU_IEN_HFXORDY_SHIFT 1
1292 #define _CMU_IEN_HFXORDY_MASK 0x2UL
1293 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
1294 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
1295 #define CMU_IEN_LFRCORDY (0x1UL << 2)
1296 #define _CMU_IEN_LFRCORDY_SHIFT 2
1297 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
1298 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
1299 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
1300 #define CMU_IEN_LFXORDY (0x1UL << 3)
1301 #define _CMU_IEN_LFXORDY_SHIFT 3
1302 #define _CMU_IEN_LFXORDY_MASK 0x8UL
1303 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
1304 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
1305 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
1306 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
1307 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
1308 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
1309 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
1310 #define CMU_IEN_CALRDY (0x1UL << 5)
1311 #define _CMU_IEN_CALRDY_SHIFT 5
1312 #define _CMU_IEN_CALRDY_MASK 0x20UL
1313 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
1314 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
1315 #define CMU_IEN_CALOF (0x1UL << 6)
1316 #define _CMU_IEN_CALOF_SHIFT 6
1317 #define _CMU_IEN_CALOF_MASK 0x40UL
1318 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
1319 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
1320 #define CMU_IEN_HFXODISERR (0x1UL << 8)
1321 #define _CMU_IEN_HFXODISERR_SHIFT 8
1322 #define _CMU_IEN_HFXODISERR_MASK 0x100UL
1323 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL
1324 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8)
1325 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9)
1326 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9
1327 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL
1328 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL
1329 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9)
1330 #define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10)
1331 #define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10
1332 #define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL
1333 #define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1334 #define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10)
1335 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11)
1336 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11
1337 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL
1338 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1339 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11)
1340 #define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12)
1341 #define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12
1342 #define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL
1343 #define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1344 #define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12)
1345 #define CMU_IEN_HFRCODIS (0x1UL << 13)
1346 #define _CMU_IEN_HFRCODIS_SHIFT 13
1347 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL
1348 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL
1349 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13)
1350 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14)
1351 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14
1352 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL
1353 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL
1354 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14)
1355 #define CMU_IEN_CMUERR (0x1UL << 31)
1356 #define _CMU_IEN_CMUERR_SHIFT 31
1357 #define _CMU_IEN_CMUERR_MASK 0x80000000UL
1358 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL
1359 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31)
1361 /* Bit fields for CMU HFBUSCLKEN0 */
1362 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL
1363 #define _CMU_HFBUSCLKEN0_MASK 0x0000003FUL
1364 #define CMU_HFBUSCLKEN0_LE (0x1UL << 0)
1365 #define _CMU_HFBUSCLKEN0_LE_SHIFT 0
1366 #define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL
1367 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL
1368 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0)
1369 #define CMU_HFBUSCLKEN0_CRYPTO (0x1UL << 1)
1370 #define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT 1
1371 #define _CMU_HFBUSCLKEN0_CRYPTO_MASK 0x2UL
1372 #define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT 0x00000000UL
1373 #define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT << 1)
1374 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 2)
1375 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 2
1376 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x4UL
1377 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL
1378 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2)
1379 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 3)
1380 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 3
1381 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x8UL
1382 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL
1383 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3)
1384 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 4)
1385 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 4
1386 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x10UL
1387 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL
1388 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4)
1389 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 5)
1390 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 5
1391 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x20UL
1392 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL
1393 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5)
1395 /* Bit fields for CMU HFPERCLKEN0 */
1396 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
1397 #define _CMU_HFPERCLKEN0_MASK 0x000003FFUL
1398 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0)
1399 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0
1400 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL
1401 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
1402 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)
1403 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1)
1404 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1
1405 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL
1406 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
1407 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)
1408 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 2)
1409 #define _CMU_HFPERCLKEN0_USART0_SHIFT 2
1410 #define _CMU_HFPERCLKEN0_USART0_MASK 0x4UL
1411 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
1412 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2)
1413 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 3)
1414 #define _CMU_HFPERCLKEN0_USART1_SHIFT 3
1415 #define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL
1416 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
1417 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)
1418 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 4)
1419 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 4
1420 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x10UL
1421 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
1422 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 4)
1423 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 5)
1424 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 5
1425 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL
1426 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
1427 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5)
1428 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6)
1429 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6
1430 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL
1431 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL
1432 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 6)
1433 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 7)
1434 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 7
1435 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x80UL
1436 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
1437 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 7)
1438 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 8)
1439 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 8
1440 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x100UL
1441 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
1442 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 8)
1443 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 9)
1444 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 9
1445 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x200UL
1446 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL
1447 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 9)
1449 /* Bit fields for CMU LFACLKEN0 */
1450 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
1451 #define _CMU_LFACLKEN0_MASK 0x00000001UL
1452 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0)
1453 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0
1454 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL
1455 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
1456 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0)
1458 /* Bit fields for CMU LFBCLKEN0 */
1459 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
1460 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
1461 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
1462 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
1463 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
1464 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
1465 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
1467 /* Bit fields for CMU LFECLKEN0 */
1468 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL
1469 #define _CMU_LFECLKEN0_MASK 0x00000001UL
1470 #define CMU_LFECLKEN0_RTCC (0x1UL << 0)
1471 #define _CMU_LFECLKEN0_RTCC_SHIFT 0
1472 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL
1473 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL
1474 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0)
1476 /* Bit fields for CMU HFPRESC */
1477 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL
1478 #define _CMU_HFPRESC_MASK 0x01001F00UL
1479 #define _CMU_HFPRESC_PRESC_SHIFT 8
1480 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL
1481 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL
1482 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL
1483 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8)
1484 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8)
1485 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24
1486 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL
1487 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL
1488 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL
1489 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL
1490 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24)
1491 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24)
1492 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24)
1494 /* Bit fields for CMU HFCOREPRESC */
1495 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL
1496 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL
1497 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8
1498 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL
1499 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL
1500 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL
1501 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8)
1502 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8)
1504 /* Bit fields for CMU HFPERPRESC */
1505 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL
1506 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL
1507 #define _CMU_HFPERPRESC_PRESC_SHIFT 8
1508 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL
1509 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL
1510 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL
1511 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8)
1512 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8)
1514 /* Bit fields for CMU HFEXPPRESC */
1515 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL
1516 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL
1517 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8
1518 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL
1519 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL
1520 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL
1521 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8)
1522 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8)
1524 /* Bit fields for CMU LFAPRESC0 */
1525 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
1526 #define _CMU_LFAPRESC0_MASK 0x0000000FUL
1527 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0
1528 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL
1529 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
1530 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
1531 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
1532 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
1533 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
1534 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
1535 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
1536 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
1537 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
1538 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
1539 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
1540 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
1541 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
1542 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
1543 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
1544 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
1545 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0)
1546 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0)
1547 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0)
1548 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0)
1549 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0)
1550 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0)
1551 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0)
1552 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0)
1553 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0)
1554 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0)
1555 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0)
1556 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0)
1557 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0)
1558 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0)
1559 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0)
1560 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0)
1562 /* Bit fields for CMU LFBPRESC0 */
1563 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
1564 #define _CMU_LFBPRESC0_MASK 0x00000003UL
1565 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
1566 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
1567 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
1568 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
1569 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
1570 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
1571 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
1572 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
1573 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
1574 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
1576 /* Bit fields for CMU LFEPRESC0 */
1577 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL
1578 #define _CMU_LFEPRESC0_MASK 0x0000000FUL
1579 #define _CMU_LFEPRESC0_RTCC_SHIFT 0
1580 #define _CMU_LFEPRESC0_RTCC_MASK 0xFUL
1581 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL
1582 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0)
1584 /* Bit fields for CMU SYNCBUSY */
1585 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
1586 #define _CMU_SYNCBUSY_MASK 0x3F050055UL
1587 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
1588 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
1589 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
1590 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
1591 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
1592 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
1593 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
1594 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
1595 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
1596 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
1597 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
1598 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
1599 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
1600 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
1601 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
1602 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
1603 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
1604 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
1605 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
1606 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
1607 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16)
1608 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16
1609 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL
1610 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL
1611 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16)
1612 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18)
1613 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18
1614 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL
1615 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL
1616 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18)
1617 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24)
1618 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24
1619 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL
1620 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL
1621 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24)
1622 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25)
1623 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25
1624 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL
1625 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL
1626 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25)
1627 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26)
1628 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26
1629 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL
1630 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL
1631 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26)
1632 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27)
1633 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27
1634 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL
1635 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL
1636 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27)
1637 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28)
1638 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28
1639 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL
1640 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL
1641 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28)
1642 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29)
1643 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29
1644 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL
1645 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL
1646 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29)
1648 /* Bit fields for CMU FREEZE */
1649 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
1650 #define _CMU_FREEZE_MASK 0x00000001UL
1651 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
1652 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
1653 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
1654 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
1655 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
1656 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
1657 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
1658 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
1659 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
1661 /* Bit fields for CMU PCNTCTRL */
1662 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
1663 #define _CMU_PCNTCTRL_MASK 0x00000003UL
1664 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
1665 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
1666 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
1667 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
1668 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
1669 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
1670 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
1671 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
1672 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
1673 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
1674 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
1675 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
1676 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
1677 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
1679 /* Bit fields for CMU ADCCTRL */
1680 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL
1681 #define _CMU_ADCCTRL_MASK 0x00000130UL
1682 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4
1683 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL
1684 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL
1685 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL
1686 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL
1687 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL
1688 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL
1689 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4)
1690 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4)
1691 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4)
1692 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4)
1693 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4)
1694 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8)
1695 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8
1696 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL
1697 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL
1698 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8)
1700 /* Bit fields for CMU ROUTEPEN */
1701 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL
1702 #define _CMU_ROUTEPEN_MASK 0x00000003UL
1703 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0)
1704 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0
1705 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL
1706 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL
1707 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0)
1708 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1)
1709 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1
1710 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL
1711 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL
1712 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1)
1714 /* Bit fields for CMU ROUTELOC0 */
1715 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL
1716 #define _CMU_ROUTELOC0_MASK 0x00000707UL
1717 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0
1718 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL
1719 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL
1720 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL
1721 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL
1722 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL
1723 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL
1724 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL
1725 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL
1726 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL
1727 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL
1728 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0)
1729 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0)
1730 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0)
1731 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0)
1732 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0)
1733 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0)
1734 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0)
1735 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0)
1736 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0)
1737 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8
1738 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL
1739 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL
1740 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL
1741 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL
1742 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL
1743 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL
1744 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL
1745 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL
1746 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL
1747 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL
1748 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8)
1749 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8)
1750 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8)
1751 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8)
1752 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8)
1753 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8)
1754 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8)
1755 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8)
1756 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8)
1758 /* Bit fields for CMU LOCK */
1759 #define _CMU_LOCK_RESETVALUE 0x00000000UL
1760 #define _CMU_LOCK_MASK 0x0000FFFFUL
1761 #define _CMU_LOCK_LOCKKEY_SHIFT 0
1762 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
1763 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
1764 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
1765 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
1766 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
1767 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
1768 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
1769 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
1770 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
1771 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
1772 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
__IOM uint32_t LFECLKEN0
Definition: efr32mg1p_cmu.h:95
__IOM uint32_t DBGCLKSEL
Definition: efr32mg1p_cmu.h:68
__IOM uint32_t LFACLKSEL
Definition: efr32mg1p_cmu.h:71
__IOM uint32_t CALCTRL
Definition: efr32mg1p_cmu.h:62
__IOM uint32_t HFCOREPRESC
__IOM uint32_t HFEXPPRESC
__IOM uint32_t HFXOCTRL
Definition: efr32mg1p_cmu.h:53
__IM uint32_t IF
Definition: efr32mg1p_cmu.h:80
__IOM uint32_t IEN
Definition: efr32mg1p_cmu.h:83
__IOM uint32_t LFACLKEN0
Definition: efr32mg1p_cmu.h:90
__IOM uint32_t HFXOSTEADYSTATECTRL
Definition: efr32mg1p_cmu.h:56
__IOM uint32_t PCNTCTRL
__IOM uint32_t LFAPRESC0
__IOM uint32_t IFC
Definition: efr32mg1p_cmu.h:82
__IOM uint32_t ROUTELOC0
__IOM uint32_t HFBUSCLKEN0
Definition: efr32mg1p_cmu.h:84
__IOM uint32_t CTRL
Definition: efr32mg1p_cmu.h:43
__IOM uint32_t LFBPRESC0
__IOM uint32_t HFCLKSEL
Definition: efr32mg1p_cmu.h:69
__IOM uint32_t AUXHFRCOCTRL
Definition: efr32mg1p_cmu.h:49
__IOM uint32_t OSCENCMD
Definition: efr32mg1p_cmu.h:65
__IOM uint32_t FREEZE
__IM uint32_t STATUS
Definition: efr32mg1p_cmu.h:76
__IOM uint32_t LFBCLKEN0
Definition: efr32mg1p_cmu.h:92
__IOM uint32_t CALCNT
Definition: efr32mg1p_cmu.h:63
__IOM uint32_t HFPERCLKEN0
Definition: efr32mg1p_cmu.h:87
__IOM uint32_t ROUTEPEN
__IOM uint32_t IFS
Definition: efr32mg1p_cmu.h:81
__IOM uint32_t LFXOCTRL
Definition: efr32mg1p_cmu.h:58
__IM uint32_t HFXOTRIMSTATUS
Definition: efr32mg1p_cmu.h:79
__IOM uint32_t HFRCOCTRL
Definition: efr32mg1p_cmu.h:46
__IOM uint32_t LFEPRESC0
__IM uint32_t HFCLKSTATUS
Definition: efr32mg1p_cmu.h:77
__IOM uint32_t HFXOTIMEOUTCTRL
Definition: efr32mg1p_cmu.h:57
__IOM uint32_t CMD
Definition: efr32mg1p_cmu.h:66
__IOM uint32_t HFPRESC
Definition: efr32mg1p_cmu.h:97
__IOM uint32_t HFPERPRESC
__IM uint32_t SYNCBUSY
__IOM uint32_t HFXOCTRL1
Definition: efr32mg1p_cmu.h:54
__IOM uint32_t HFXOSTARTUPCTRL
Definition: efr32mg1p_cmu.h:55
__IOM uint32_t ULFRCOCTRL
Definition: efr32mg1p_cmu.h:59
__IOM uint32_t ADCCTRL
__IOM uint32_t LFRCOCTRL
Definition: efr32mg1p_cmu.h:52
__IOM uint32_t LFBCLKSEL
Definition: efr32mg1p_cmu.h:72
__IOM uint32_t LOCK
__IOM uint32_t LFECLKSEL
Definition: efr32mg1p_cmu.h:73