EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
EFR32MG1P233F256GM48

Detailed Description

Modules

 EFR32MG1P233F256GM48 Alternate Function
 
 EFR32MG1P233F256GM48 Bit Fields
 
 EFR32MG1P233F256GM48 Core
 Processor and Core Peripheral Section.
 
 EFR32MG1P233F256GM48 Part
 
 EFR32MG1P233F256GM48 Peripheral Declarations
 
 EFR32MG1P233F256GM48 Peripheral Memory Map
 
 EFR32MG1P233F256GM48 Peripheral Offsets
 
 EFR32MG1P233F256GM48 Peripheral TypeDefs
 Device Specific Peripheral Register Structures.
 

Macros

#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
 Set the value of a bit field within a register. More...
 

Typedefs

typedef enum IRQn IRQn_Type
 

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11,
  UsageFault_IRQn = -10,
  SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  EMU_IRQn = 0,
  WDOG0_IRQn = 2,
  LDMA_IRQn = 8,
  GPIO_EVEN_IRQn = 9,
  TIMER0_IRQn = 10,
  USART0_RX_IRQn = 11,
  USART0_TX_IRQn = 12,
  ACMP0_IRQn = 13,
  ADC0_IRQn = 14,
  IDAC0_IRQn = 15,
  I2C0_IRQn = 16,
  GPIO_ODD_IRQn = 17,
  TIMER1_IRQn = 18,
  USART1_RX_IRQn = 19,
  USART1_TX_IRQn = 20,
  LEUART0_IRQn = 21,
  PCNT0_IRQn = 22,
  CMU_IRQn = 23,
  MSC_IRQn = 24,
  CRYPTO_IRQn = 25,
  LETIMER0_IRQn = 26,
  RTCC_IRQn = 29,
  CRYOTIMER_IRQn = 31,
  FPUEH_IRQn = 33
}
 

Macro Definition Documentation

#define SET_BIT_FIELD (   REG,
  MASK,
  VALUE,
  OFFSET 
)    REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters
REGThe register to update
MASKThe mask for the bit field to update
VALUEThe value to write to the bit field
OFFSETThe number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 429 of file efr32mg1p233f256gm48.h.

Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition

Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn 

-14 Cortex-M4 Non Maskable Interrupt

HardFault_IRQn 

-13 Cortex-M4 Hard Fault Interrupt

MemoryManagement_IRQn 

-12 Cortex-M4 Memory Management Interrupt

BusFault_IRQn 

-11 Cortex-M4 Bus Fault Interrupt

UsageFault_IRQn 

-10 Cortex-M4 Usage Fault Interrupt

SVCall_IRQn 

-5 Cortex-M4 SV Call Interrupt

DebugMonitor_IRQn 

-4 Cortex-M4 Debug Monitor Interrupt

PendSV_IRQn 

-2 Cortex-M4 Pend SV Interrupt

SysTick_IRQn 

-1 Cortex-M4 System Tick Interrupt

EMU_IRQn 

0 EFR32 EMU Interrupt

WDOG0_IRQn 

2 EFR32 WDOG0 Interrupt

LDMA_IRQn 

8 EFR32 LDMA Interrupt

GPIO_EVEN_IRQn 

9 EFR32 GPIO_EVEN Interrupt

TIMER0_IRQn 

10 EFR32 TIMER0 Interrupt

USART0_RX_IRQn 

11 EFR32 USART0_RX Interrupt

USART0_TX_IRQn 

12 EFR32 USART0_TX Interrupt

ACMP0_IRQn 

13 EFR32 ACMP0 Interrupt

ADC0_IRQn 

14 EFR32 ADC0 Interrupt

IDAC0_IRQn 

15 EFR32 IDAC0 Interrupt

I2C0_IRQn 

16 EFR32 I2C0 Interrupt

GPIO_ODD_IRQn 

17 EFR32 GPIO_ODD Interrupt

TIMER1_IRQn 

18 EFR32 TIMER1 Interrupt

USART1_RX_IRQn 

19 EFR32 USART1_RX Interrupt

USART1_TX_IRQn 

20 EFR32 USART1_TX Interrupt

LEUART0_IRQn 

21 EFR32 LEUART0 Interrupt

PCNT0_IRQn 

22 EFR32 PCNT0 Interrupt

CMU_IRQn 

23 EFR32 CMU Interrupt

MSC_IRQn 

24 EFR32 MSC Interrupt

CRYPTO_IRQn 

25 EFR32 CRYPTO Interrupt

LETIMER0_IRQn 

26 EFR32 LETIMER0 Interrupt

RTCC_IRQn 

29 EFR32 RTCC Interrupt

CRYOTIMER_IRQn 

31 EFR32 CRYOTIMER Interrupt

FPUEH_IRQn 

33 EFR32 FPUEH Interrupt

Definition at line 52 of file efr32mg1p233f256gm48.h.