Detailed Description

CMSIS Cortex-M Peripheral Access Layer Header File for EFM32ZG222F32.

Version: 5.1.2

License

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
This notice may not be removed or altered from any source distribution.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.

Definition in file efm32zg222f32.h.

#include "arm_math.h"
#include "core_cm0plus.h"
#include "system_efm32zg.h"
#include "efm32zg_aes.h"
#include "efm32zg_dma_ch.h"
#include "efm32zg_dma.h"
#include "efm32zg_msc.h"
#include "efm32zg_emu.h"
#include "efm32zg_rmu.h"
#include "efm32zg_cmu.h"
#include "efm32zg_timer_cc.h"
#include "efm32zg_timer.h"
#include "efm32zg_acmp.h"
#include "efm32zg_usart.h"
#include "efm32zg_prs_ch.h"
#include "efm32zg_prs.h"
#include "efm32zg_idac.h"
#include "efm32zg_gpio_p.h"
#include "efm32zg_gpio.h"
#include "efm32zg_vcmp.h"
#include "efm32zg_adc.h"
#include "efm32zg_leuart.h"
#include "efm32zg_pcnt.h"
#include "efm32zg_i2c.h"
#include "efm32zg_rtc.h"
#include "efm32zg_wdog.h"
#include "efm32zg_dma_descriptor.h"
#include "efm32zg_devinfo.h"
#include "efm32zg_romtable.h"
#include "efm32zg_calibrate.h"
#include "efm32zg_prs_signals.h"
#include "efm32zg_dmareq.h"
#include "efm32zg_dmactrl.h"
#include "efm32zg_af_ports.h"
#include "efm32zg_af_pins.h"

Go to the source code of this file.

Macros
#define	__CM0PLUS_REV 0x001

#define	__MPU_PRESENT 0

#define	__NVIC_PRIO_BITS 2

#define	__Vendor_SysTickConfig 0

#define	__VTOR_PRESENT 1

#define	_EFM32_ZERO_FAMILY 1

#define	_EFM_DEVICE

#define	_SILICON_LABS_32B_PLATFORM 1

#define	_SILICON_LABS_32B_PLATFORM_1

#define	_SILICON_LABS_32B_SERIES 0

#define	_SILICON_LABS_32B_SERIES_0

#define	_SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */

#define	_SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */

#define	ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)

#define	ACMP0_BASE (0x40001000UL)

#define	ACMP_COUNT 1

#define	ACMP_PRESENT

#define	ADC0 ((ADC_TypeDef *) ADC0_BASE)

#define	ADC0_BASE (0x40002000UL)

#define	ADC_COUNT 1

#define	ADC_PRESENT

#define	AES ((AES_TypeDef *) AES_BASE)

#define	AES_BASE (0x400E0000UL)

#define	AES_COUNT 1

#define	AES_MEM_BASE ((uint32_t) 0x400E0000UL)

#define	AES_MEM_BITS ((uint32_t) 0x10UL)

#define	AES_MEM_END ((uint32_t) 0x400E03FFUL)

#define	AES_MEM_SIZE ((uint32_t) 0x400UL)

#define	AES_PRESENT

#define	AFACHAN_MAX 25

#define	AFCHAN_MAX 33

#define	AFCHANLOC_MAX 7

#define	ANALOG_COUNT 1

#define	ANALOG_PRESENT

#define	ARM_MATH_CM0PLUS

#define	BOOTLOADER_COUNT 1

#define	BOOTLOADER_PRESENT

#define	CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)

#define	CALIBRATE_BASE (0x0FE08000UL)

#define	CMU ((CMU_TypeDef *) CMU_BASE)

#define	CMU_BASE (0x400C8000UL)

#define	CMU_COUNT 1

#define	CMU_PRESENT

#define	CMU_UNLOCK_CODE 0x580E

#define	DBG_COUNT 1

#define	DBG_PRESENT

#define	DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)

#define	DEVINFO_BASE (0x0FE081B0UL)

#define	DMA ((DMA_TypeDef *) DMA_BASE)

#define	DMA_BASE (0x400C2000UL)

#define	DMA_CHAN_COUNT 4

#define	DMA_COUNT 1

#define	DMA_PRESENT

#define	EMU ((EMU_TypeDef *) EMU_BASE)

#define	EMU_BASE (0x400C6000UL)

#define	EMU_COUNT 1

#define	EMU_PRESENT

#define	EMU_UNLOCK_CODE 0xADE8

#define	EXT_IRQ_COUNT 19

#define	FLASH_BASE (0x00000000UL)

#define	FLASH_MEM_BASE ((uint32_t) 0x0UL)

#define	FLASH_MEM_BITS ((uint32_t) 0x28UL)

#define	FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)

#define	FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)

#define	FLASH_PAGE_SIZE 1024

#define	FLASH_SIZE (0x00008000UL)

#define	GPIO ((GPIO_TypeDef *) GPIO_BASE)

#define	GPIO_BASE (0x40006000UL)

#define	GPIO_COUNT 1

#define	GPIO_PRESENT

#define	GPIO_UNLOCK_CODE 0xA534

#define	HFXTAL_COUNT 1

#define	HFXTAL_PRESENT

#define	I2C0 ((I2C_TypeDef *) I2C0_BASE)

#define	I2C0_BASE (0x4000A000UL)

#define	I2C_COUNT 1

#define	I2C_PRESENT

#define	IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)

#define	IDAC0_BASE (0x40004000UL)

#define	IDAC_COUNT 1

#define	IDAC_PRESENT

#define	LE_COUNT 1

#define	LE_PRESENT

#define	LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)

#define	LEUART0_BASE (0x40084000UL)

#define	LEUART_COUNT 1

#define	LEUART_PRESENT

#define	LFXTAL_COUNT 1

#define	LFXTAL_PRESENT

#define	LOCKBITS_BASE (0x0FE04000UL)

#define	MSC ((MSC_TypeDef *) MSC_BASE)

#define	MSC_BASE (0x400C0000UL)

#define	MSC_COUNT 1

#define	MSC_PRESENT

#define	MSC_UNLOCK_CODE 0x1B71

#define	PART_NUMBER "EFM32ZG222F32"

#define	PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)

#define	PCNT0_BASE (0x40086000UL)

#define	PCNT_COUNT 1

#define	PCNT_PRESENT

#define	PER_MEM_BASE ((uint32_t) 0x40000000UL)

#define	PER_MEM_BITS ((uint32_t) 0x20UL)

#define	PER_MEM_END ((uint32_t) 0x400DFFFFUL)

#define	PER_MEM_SIZE ((uint32_t) 0xE0000UL)

#define	PRS ((PRS_TypeDef *) PRS_BASE)

#define	PRS_BASE (0x400CC000UL)

#define	PRS_CHAN_COUNT 4

#define	PRS_COUNT 1

#define	PRS_PRESENT

#define	RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)

#define	RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)

#define	RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)

#define	RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)

#define	RAM_MEM_BASE ((uint32_t) 0x20000000UL)

#define	RAM_MEM_BITS ((uint32_t) 0x18UL)

#define	RAM_MEM_END ((uint32_t) 0x2003FFFFUL)

#define	RAM_MEM_SIZE ((uint32_t) 0x40000UL)

#define	RMU ((RMU_TypeDef *) RMU_BASE)

#define	RMU_BASE (0x400CA000UL)

#define	RMU_COUNT 1

#define	RMU_PRESENT

#define	ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)

#define	ROMTABLE_BASE (0xF00FFFD0UL)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	RTC_BASE (0x40080000UL)

#define	RTC_COUNT 1

#define	RTC_PRESENT

#define	SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));
	Set the value of a bit field within a register. More...

#define	SRAM_BASE (0x20000000UL)

#define	SRAM_SIZE (0x00001000UL)

#define	TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)

#define	TIMER0_BASE (0x40010000UL)

#define	TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)

#define	TIMER1_BASE (0x40010400UL)

#define	TIMER_COUNT 2

#define	TIMER_PRESENT

#define	TIMER_UNLOCK_CODE 0xCE80

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	USART1_BASE (0x4000C400UL)

#define	USART_COUNT 1

#define	USART_PRESENT

#define	USERDATA_BASE (0x0FE00000UL)

#define	VCMP ((VCMP_TypeDef *) VCMP_BASE)

#define	VCMP_BASE (0x40000000UL)

#define	VCMP_COUNT 1

#define	VCMP_PRESENT

#define	WDOG ((WDOG_TypeDef *) WDOG_BASE)

#define	WDOG_BASE (0x40088000UL)

#define	WDOG_COUNT 1

#define	WDOG_PRESENT

Typedefs
typedef enum IRQn	IRQn_Type

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, ACMP0_IRQn = 3, ADC0_IRQn = 4, I2C0_IRQn = 5, GPIO_ODD_IRQn = 6, TIMER1_IRQn = 7, USART1_RX_IRQn = 8, USART1_TX_IRQn = 9, LEUART0_IRQn = 10, PCNT0_IRQn = 11, RTC_IRQn = 12, CMU_IRQn = 13, VCMP_IRQn = 14, MSC_IRQn = 15, AES_IRQn = 16 }

Detailed Description

License

Macros

Typedefs

Enumerations