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efm32zg_dmareq.h
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0)
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#define DMAREQ_ADC0_SCAN ((8 << 16) + 1)
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#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0)
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#define DMAREQ_USART1_TXBL ((13 << 16) + 1)
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#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2)
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#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3)
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#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4)
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#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0)
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#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1)
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#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2)
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#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0)
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#define DMAREQ_I2C0_TXBL ((20 << 16) + 1)
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#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0)
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#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1)
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#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2)
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#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3)
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#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0)
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#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1)
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#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2)
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#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3)
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#define DMAREQ_MSC_WDATA ((48 << 16) + 0)
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#define DMAREQ_AES_DATAWR ((49 << 16) + 0)
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#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1)
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#define DMAREQ_AES_DATARD ((49 << 16) + 2)
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#define DMAREQ_AES_KEYWR ((49 << 16) + 3)
platform
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EFM32ZG
Include
efm32zg_dmareq.h
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