EFM32 Wonder Gecko Software Documentation  efm32wg-doc-5.1.2
efm32wg995f256.h
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1 /**************************************************************************/
34 #ifndef EFM32WG995F256_H
35 #define EFM32WG995F256_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**************************************************************************/
46 /**************************************************************************/
52 typedef enum IRQn
53 {
54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
58  BusFault_IRQn = -11,
60  SVCall_IRQn = -5,
62  PendSV_IRQn = -2,
63  SysTick_IRQn = -1,
65 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/
66  DMA_IRQn = 0,
71  USB_IRQn = 5,
72  ACMP0_IRQn = 6,
73  ADC0_IRQn = 7,
74  DAC0_IRQn = 8,
75  I2C0_IRQn = 9,
76  I2C1_IRQn = 10,
78  TIMER1_IRQn = 12,
79  TIMER2_IRQn = 13,
80  TIMER3_IRQn = 14,
83  LESENSE_IRQn = 17,
90  LEUART0_IRQn = 24,
91  LEUART1_IRQn = 25,
93  PCNT0_IRQn = 27,
94  PCNT1_IRQn = 28,
95  PCNT2_IRQn = 29,
96  RTC_IRQn = 30,
97  BURTC_IRQn = 31,
98  CMU_IRQn = 32,
99  VCMP_IRQn = 33,
100  LCD_IRQn = 34,
101  MSC_IRQn = 35,
102  AES_IRQn = 36,
103  EBI_IRQn = 37,
104  EMU_IRQn = 38,
105  FPUEH_IRQn = 39,
106 } IRQn_Type;
107 
108 /**************************************************************************/
113 #define __MPU_PRESENT 1
114 #define __FPU_PRESENT 1
115 #define __VTOR_PRESENT 1
116 #define __NVIC_PRIO_BITS 3
117 #define __Vendor_SysTickConfig 0
121 /**************************************************************************/
127 #define _EFM32_WONDER_FAMILY 1
128 #define _EFM_DEVICE
129 #define _SILICON_LABS_32B_SERIES_0
130 #define _SILICON_LABS_32B_SERIES 0
131 #define _SILICON_LABS_GECKO_INTERNAL_SDID 74
132 #define _SILICON_LABS_GECKO_INTERNAL_SDID_74
133 #define _SILICON_LABS_32B_PLATFORM_1
134 #define _SILICON_LABS_32B_PLATFORM 1
136 /* If part number is not defined as compiler option, define it */
137 #if !defined(EFM32WG995F256)
138 #define EFM32WG995F256 1
139 #endif
140 
142 #define PART_NUMBER "EFM32WG995F256"
145 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
146 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
147 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
148 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
149 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
150 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
151 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
152 #define AES_MEM_BITS ((uint32_t) 0x10UL)
153 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
154 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
155 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
156 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
157 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL)
158 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL)
159 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL)
160 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL)
161 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
162 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
163 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
164 #define PER_MEM_BITS ((uint32_t) 0x20UL)
165 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
166 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
167 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
168 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
169 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
170 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
171 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
172 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
173 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
174 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL)
175 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL)
176 #define EBI_MEM_BITS ((uint32_t) 0x30UL)
179 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
180 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
183 #define FLASH_BASE (0x00000000UL)
184 #define FLASH_SIZE (0x00040000UL)
185 #define FLASH_PAGE_SIZE 2048
186 #define SRAM_BASE (0x20000000UL)
187 #define SRAM_SIZE (0x00008000UL)
188 #define __CM4_REV 0x001
189 #define PRS_CHAN_COUNT 12
190 #define DMA_CHAN_COUNT 12
191 #define EXT_IRQ_COUNT 40
194 #define AFCHAN_MAX 163
195 #define AFCHANLOC_MAX 7
196 
197 #define AFACHAN_MAX 53
198 
199 /* Part number capabilities */
200 
201 #define USART_PRESENT
202 #define USART_COUNT 3
203 #define UART_PRESENT
204 #define UART_COUNT 2
205 #define TIMER_PRESENT
206 #define TIMER_COUNT 4
207 #define ACMP_PRESENT
208 #define ACMP_COUNT 2
209 #define LEUART_PRESENT
210 #define LEUART_COUNT 2
211 #define LETIMER_PRESENT
212 #define LETIMER_COUNT 1
213 #define PCNT_PRESENT
214 #define PCNT_COUNT 3
215 #define I2C_PRESENT
216 #define I2C_COUNT 2
217 #define ADC_PRESENT
218 #define ADC_COUNT 1
219 #define DAC_PRESENT
220 #define DAC_COUNT 1
221 #define DMA_PRESENT
222 #define DMA_COUNT 1
223 #define AES_PRESENT
224 #define AES_COUNT 1
225 #define USBC_PRESENT
226 #define USBC_COUNT 1
227 #define USB_PRESENT
228 #define USB_COUNT 1
229 #define LE_PRESENT
230 #define LE_COUNT 1
231 #define MSC_PRESENT
232 #define MSC_COUNT 1
233 #define EMU_PRESENT
234 #define EMU_COUNT 1
235 #define RMU_PRESENT
236 #define RMU_COUNT 1
237 #define CMU_PRESENT
238 #define CMU_COUNT 1
239 #define LESENSE_PRESENT
240 #define LESENSE_COUNT 1
241 #define EBI_PRESENT
242 #define EBI_COUNT 1
243 #define FPUEH_PRESENT
244 #define FPUEH_COUNT 1
245 #define RTC_PRESENT
246 #define RTC_COUNT 1
247 #define GPIO_PRESENT
248 #define GPIO_COUNT 1
249 #define VCMP_PRESENT
250 #define VCMP_COUNT 1
251 #define PRS_PRESENT
252 #define PRS_COUNT 1
253 #define OPAMP_PRESENT
254 #define OPAMP_COUNT 1
255 #define BU_PRESENT
256 #define BU_COUNT 1
257 #define LCD_PRESENT
258 #define LCD_COUNT 1
259 #define BURTC_PRESENT
260 #define BURTC_COUNT 1
261 #define HFXTAL_PRESENT
262 #define HFXTAL_COUNT 1
263 #define LFXTAL_PRESENT
264 #define LFXTAL_COUNT 1
265 #define WDOG_PRESENT
266 #define WDOG_COUNT 1
267 #define DBG_PRESENT
268 #define DBG_COUNT 1
269 #define ETM_PRESENT
270 #define ETM_COUNT 1
271 #define BOOTLOADER_PRESENT
272 #define BOOTLOADER_COUNT 1
273 #define ANALOG_PRESENT
274 #define ANALOG_COUNT 1
275 
276 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
277 #include "system_efm32wg.h" /* System Header */
278 
281 /**************************************************************************/
287 #include "efm32wg_dma_ch.h"
288 #include "efm32wg_dma.h"
289 #include "efm32wg_aes.h"
290 #include "efm32wg_usb_hc.h"
291 #include "efm32wg_usb_diep.h"
292 #include "efm32wg_usb_doep.h"
293 #include "efm32wg_usb.h"
294 #include "efm32wg_msc.h"
295 #include "efm32wg_emu.h"
296 #include "efm32wg_rmu.h"
297 #include "efm32wg_cmu.h"
298 #include "efm32wg_lesense_st.h"
299 #include "efm32wg_lesense_buf.h"
300 #include "efm32wg_lesense_ch.h"
301 #include "efm32wg_lesense.h"
302 #include "efm32wg_ebi.h"
303 #include "efm32wg_fpueh.h"
304 #include "efm32wg_usart.h"
305 #include "efm32wg_timer_cc.h"
306 #include "efm32wg_timer.h"
307 #include "efm32wg_acmp.h"
308 #include "efm32wg_leuart.h"
309 #include "efm32wg_rtc.h"
310 #include "efm32wg_letimer.h"
311 #include "efm32wg_pcnt.h"
312 #include "efm32wg_i2c.h"
313 #include "efm32wg_gpio_p.h"
314 #include "efm32wg_gpio.h"
315 #include "efm32wg_vcmp.h"
316 #include "efm32wg_prs_ch.h"
317 #include "efm32wg_prs.h"
318 #include "efm32wg_adc.h"
319 #include "efm32wg_dac.h"
320 #include "efm32wg_lcd.h"
321 #include "efm32wg_burtc_ret.h"
322 #include "efm32wg_burtc.h"
323 #include "efm32wg_wdog.h"
324 #include "efm32wg_etm.h"
325 #include "efm32wg_dma_descriptor.h"
326 #include "efm32wg_devinfo.h"
327 #include "efm32wg_romtable.h"
328 #include "efm32wg_calibrate.h"
329 
332 /**************************************************************************/
337 #define DMA_BASE (0x400C2000UL)
338 #define AES_BASE (0x400E0000UL)
339 #define USB_BASE (0x400C4000UL)
340 #define MSC_BASE (0x400C0000UL)
341 #define EMU_BASE (0x400C6000UL)
342 #define RMU_BASE (0x400CA000UL)
343 #define CMU_BASE (0x400C8000UL)
344 #define LESENSE_BASE (0x4008C000UL)
345 #define EBI_BASE (0x40008000UL)
346 #define FPUEH_BASE (0x400C1C00UL)
347 #define USART0_BASE (0x4000C000UL)
348 #define USART1_BASE (0x4000C400UL)
349 #define USART2_BASE (0x4000C800UL)
350 #define UART0_BASE (0x4000E000UL)
351 #define UART1_BASE (0x4000E400UL)
352 #define TIMER0_BASE (0x40010000UL)
353 #define TIMER1_BASE (0x40010400UL)
354 #define TIMER2_BASE (0x40010800UL)
355 #define TIMER3_BASE (0x40010C00UL)
356 #define ACMP0_BASE (0x40001000UL)
357 #define ACMP1_BASE (0x40001400UL)
358 #define LEUART0_BASE (0x40084000UL)
359 #define LEUART1_BASE (0x40084400UL)
360 #define RTC_BASE (0x40080000UL)
361 #define LETIMER0_BASE (0x40082000UL)
362 #define PCNT0_BASE (0x40086000UL)
363 #define PCNT1_BASE (0x40086400UL)
364 #define PCNT2_BASE (0x40086800UL)
365 #define I2C0_BASE (0x4000A000UL)
366 #define I2C1_BASE (0x4000A400UL)
367 #define GPIO_BASE (0x40006000UL)
368 #define VCMP_BASE (0x40000000UL)
369 #define PRS_BASE (0x400CC000UL)
370 #define ADC0_BASE (0x40002000UL)
371 #define DAC0_BASE (0x40004000UL)
372 #define LCD_BASE (0x4008A000UL)
373 #define BURTC_BASE (0x40081000UL)
374 #define WDOG_BASE (0x40088000UL)
375 #define ETM_BASE (0xE0041000UL)
376 #define CALIBRATE_BASE (0x0FE08000UL)
377 #define DEVINFO_BASE (0x0FE081B0UL)
378 #define ROMTABLE_BASE (0xE00FFFD0UL)
379 #define LOCKBITS_BASE (0x0FE04000UL)
380 #define USERDATA_BASE (0x0FE00000UL)
384 /**************************************************************************/
389 #define DMA ((DMA_TypeDef *) DMA_BASE)
390 #define AES ((AES_TypeDef *) AES_BASE)
391 #define USB ((USB_TypeDef *) USB_BASE)
392 #define MSC ((MSC_TypeDef *) MSC_BASE)
393 #define EMU ((EMU_TypeDef *) EMU_BASE)
394 #define RMU ((RMU_TypeDef *) RMU_BASE)
395 #define CMU ((CMU_TypeDef *) CMU_BASE)
396 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE)
397 #define EBI ((EBI_TypeDef *) EBI_BASE)
398 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE)
399 #define USART0 ((USART_TypeDef *) USART0_BASE)
400 #define USART1 ((USART_TypeDef *) USART1_BASE)
401 #define USART2 ((USART_TypeDef *) USART2_BASE)
402 #define UART0 ((USART_TypeDef *) UART0_BASE)
403 #define UART1 ((USART_TypeDef *) UART1_BASE)
404 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
405 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
406 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
407 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE)
408 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
409 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
410 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
411 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
412 #define RTC ((RTC_TypeDef *) RTC_BASE)
413 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
414 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
415 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
416 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
417 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
418 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
419 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
420 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
421 #define PRS ((PRS_TypeDef *) PRS_BASE)
422 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
423 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
424 #define LCD ((LCD_TypeDef *) LCD_BASE)
425 #define BURTC ((BURTC_TypeDef *) BURTC_BASE)
426 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
427 #define ETM ((ETM_TypeDef *) ETM_BASE)
428 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
429 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
430 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
434 /**************************************************************************/
439 #include "efm32wg_prs_signals.h"
440 #include "efm32wg_dmareq.h"
441 #include "efm32wg_dmactrl.h"
442 #include "efm32wg_uart.h"
443 
444 /**************************************************************************/
448 #define MSC_UNLOCK_CODE 0x1B71
449 #define EMU_UNLOCK_CODE 0xADE8
450 #define CMU_UNLOCK_CODE 0x580E
451 #define TIMER_UNLOCK_CODE 0xCE80
452 #define GPIO_UNLOCK_CODE 0xA534
453 #define BURTC_UNLOCK_CODE 0xAEE8
459 /**************************************************************************/
464 #include "efm32wg_af_ports.h"
465 #include "efm32wg_af_pins.h"
466 
469 /**************************************************************************/
482 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
483  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
484 
489 #ifdef __cplusplus
490 }
491 #endif
492 #endif /* EFM32WG995F256_H */
EFM32WG_DAC register and bit field definitions.
EFM32WG_VCMP register and bit field definitions.
EFM32WG_ETM register and bit field definitions.
EFM32WG_BURTC register and bit field definitions.
EFM32WG_USB_HC register and bit field definitions.
EFM32WG_LESENSE register and bit field definitions.
EFM32WG_TIMER_CC register and bit field definitions.
EFM32WG_RMU register and bit field definitions.
enum IRQn IRQn_Type
EFM32WG_USB_DOEP register and bit field definitions.
EFM32WG_USB register and bit field definitions.
EFM32WG_PCNT register and bit field definitions.
EFM32WG_WDOG register and bit field definitions.
EFM32WG_LESENSE_CH register and bit field definitions.
EFM32WG_PRS register and bit field definitions.
EFM32WG_EMU register and bit field definitions.
EFM32WG_GPIO_P register and bit field definitions.
EFM32WG_RTC register and bit field definitions.
EFM32WG_CMU register and bit field definitions.
EFM32WG_LESENSE_ST register and bit field definitions.
EFM32WG_USB_DIEP register and bit field definitions.
EFM32WG_DMACTRL register and bit field definitions.
EFM32WG_BURTC_RET register and bit field definitions.
EFM32WG_CALIBRATE register and bit field definitions.
EFM32WG_TIMER register and bit field definitions.
IRQn
EFM32WG_LESENSE_BUF register and bit field definitions.
EFM32WG_GPIO register and bit field definitions.
EFM32WG_LEUART register and bit field definitions.
EFM32WG_LCD register and bit field definitions.
EFM32WG_ACMP register and bit field definitions.
EFM32WG_USART register and bit field definitions.
EFM32WG_I2C register and bit field definitions.
EFM32WG_FPUEH register and bit field definitions.
EFM32WG_DMA_DESCRIPTOR register and bit field definitions.
EFM32WG_EBI register and bit field definitions.
EFM32WG_ADC register and bit field definitions.
EFM32WG_ROMTABLE register and bit field definitions.
EFM32WG_DMAREQ register and bit field definitions.
EFM32WG_DMA_CH register and bit field definitions.
EFM32WG_DMA register and bit field definitions.
EFM32WG_DEVINFO register and bit field definitions.
CMSIS Cortex-M4 System Layer for EFM32WG devices.
EFM32WG_UART register and bit field definitions.
EFM32WG_AES register and bit field definitions.
EFM32WG_LETIMER register and bit field definitions.
EFM32WG_PRS_CH register and bit field definitions.
EFM32WG_AF_PINS register and bit field definitions.
EFM32WG_MSC register and bit field definitions.