Detailed Description

EFM32WG_CMU register and bit field definitions.

Version: 5.1.2

License

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Definition in file efm32wg_cmu.h.

Go to the source code of this file.

Data Structures
struct	CMU_TypeDef

Macros
#define	_CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL

#define	_CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL

#define	_CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL

#define	_CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL

#define	_CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL

#define	_CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL

#define	_CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL

#define	_CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL

#define	_CMU_AUXHFRCOCTRL_BAND_SHIFT 8

#define	_CMU_AUXHFRCOCTRL_MASK 0x000007FFUL

#define	_CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL

#define	_CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL

#define	_CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL

#define	_CMU_AUXHFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL

#define	_CMU_CALCNT_CALCNT_MASK 0xFFFFFUL

#define	_CMU_CALCNT_CALCNT_SHIFT 0

#define	_CMU_CALCNT_MASK 0x000FFFFFUL

#define	_CMU_CALCNT_RESETVALUE 0x00000000UL

#define	_CMU_CALCTRL_CONT_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_CONT_MASK 0x40UL

#define	_CMU_CALCTRL_CONT_SHIFT 6

#define	_CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL

#define	_CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL

#define	_CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL

#define	_CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL

#define	_CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL

#define	_CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL

#define	_CMU_CALCTRL_DOWNSEL_MASK 0x38UL

#define	_CMU_CALCTRL_DOWNSEL_SHIFT 3

#define	_CMU_CALCTRL_MASK 0x0000007FUL

#define	_CMU_CALCTRL_RESETVALUE 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL

#define	_CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL

#define	_CMU_CALCTRL_UPSEL_HFXO 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL

#define	_CMU_CALCTRL_UPSEL_LFXO 0x00000001UL

#define	_CMU_CALCTRL_UPSEL_MASK 0x7UL

#define	_CMU_CALCTRL_UPSEL_SHIFT 0

#define	_CMU_CMD_CALSTART_DEFAULT 0x00000000UL

#define	_CMU_CMD_CALSTART_MASK 0x8UL

#define	_CMU_CMD_CALSTART_SHIFT 3

#define	_CMU_CMD_CALSTOP_DEFAULT 0x00000000UL

#define	_CMU_CMD_CALSTOP_MASK 0x10UL

#define	_CMU_CMD_CALSTOP_SHIFT 4

#define	_CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL

#define	_CMU_CMD_HFCLKSEL_HFXO 0x00000002UL

#define	_CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL

#define	_CMU_CMD_HFCLKSEL_LFXO 0x00000004UL

#define	_CMU_CMD_HFCLKSEL_MASK 0x7UL

#define	_CMU_CMD_HFCLKSEL_SHIFT 0

#define	_CMU_CMD_MASK 0x000000FFUL

#define	_CMU_CMD_RESETVALUE 0x00000000UL

#define	_CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL

#define	_CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL

#define	_CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL

#define	_CMU_CMD_USBCCLKSEL_MASK 0xE0UL

#define	_CMU_CMD_USBCCLKSEL_SHIFT 5

#define	_CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL

#define	_CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL

#define	_CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL

#define	_CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL

#define	_CMU_CTRL_CLKOUTSEL0_SHIFT 20

#define	_CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL

#define	_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL

#define	_CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL

#define	_CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL

#define	_CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL

#define	_CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL

#define	_CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL

#define	_CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL

#define	_CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL

#define	_CMU_CTRL_CLKOUTSEL1_SHIFT 23

#define	_CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL

#define	_CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL

#define	_CMU_CTRL_DBGCLK_HFCLK 0x00000001UL

#define	_CMU_CTRL_DBGCLK_MASK 0x10000000UL

#define	_CMU_CTRL_DBGCLK_SHIFT 28

#define	_CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFCLKDIV_MASK 0x1C000UL

#define	_CMU_CTRL_HFCLKDIV_SHIFT 14

#define	_CMU_CTRL_HFLE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFLE_MASK 0x40000000UL

#define	_CMU_CTRL_HFLE_SHIFT 30

#define	_CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL

#define	_CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL

#define	_CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL

#define	_CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL

#define	_CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL

#define	_CMU_CTRL_HFXOBOOST_MASK 0xCUL

#define	_CMU_CTRL_HFXOBOOST_SHIFT 2

#define	_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL

#define	_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL

#define	_CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL

#define	_CMU_CTRL_HFXOBUFCUR_MASK 0x60UL

#define	_CMU_CTRL_HFXOBUFCUR_SHIFT 5

#define	_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL

#define	_CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7

#define	_CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL

#define	_CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL

#define	_CMU_CTRL_HFXOMODE_MASK 0x3UL

#define	_CMU_CTRL_HFXOMODE_SHIFT 0

#define	_CMU_CTRL_HFXOMODE_XTAL 0x00000000UL

#define	_CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL

#define	_CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL

#define	_CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL

#define	_CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL

#define	_CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL

#define	_CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL

#define	_CMU_CTRL_HFXOTIMEOUT_SHIFT 9

#define	_CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL

#define	_CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL

#define	_CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL

#define	_CMU_CTRL_LFXOBOOST_MASK 0x2000UL

#define	_CMU_CTRL_LFXOBOOST_SHIFT 13

#define	_CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL

#define	_CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL

#define	_CMU_CTRL_LFXOBUFCUR_SHIFT 17

#define	_CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL

#define	_CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL

#define	_CMU_CTRL_LFXOMODE_MASK 0x1800UL

#define	_CMU_CTRL_LFXOMODE_SHIFT 11

#define	_CMU_CTRL_LFXOMODE_XTAL 0x00000000UL

#define	_CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL

#define	_CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL

#define	_CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL

#define	_CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL

#define	_CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL

#define	_CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL

#define	_CMU_CTRL_LFXOTIMEOUT_SHIFT 18

#define	_CMU_CTRL_MASK 0x57FFFEEFUL

#define	_CMU_CTRL_RESETVALUE 0x000C262CUL

#define	_CMU_FREEZE_MASK 0x00000001UL

#define	_CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL

#define	_CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL

#define	_CMU_FREEZE_REGFREEZE_MASK 0x1UL

#define	_CMU_FREEZE_REGFREEZE_SHIFT 0

#define	_CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL

#define	_CMU_FREEZE_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8

#define	_CMU_HFCORECLKDIV_MASK 0x0000010FUL

#define	_CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_AES_MASK 0x2UL

#define	_CMU_HFCORECLKEN0_AES_SHIFT 1

#define	_CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_DMA_MASK 0x1UL

#define	_CMU_HFCORECLKEN0_DMA_SHIFT 0

#define	_CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_EBI_MASK 0x20UL

#define	_CMU_HFCORECLKEN0_EBI_SHIFT 5

#define	_CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_LE_MASK 0x10UL

#define	_CMU_HFCORECLKEN0_LE_SHIFT 4

#define	_CMU_HFCORECLKEN0_MASK 0x0000003FUL

#define	_CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_USB_MASK 0x8UL

#define	_CMU_HFCORECLKEN0_USB_SHIFT 3

#define	_CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_USBC_MASK 0x4UL

#define	_CMU_HFCORECLKEN0_USBC_SHIFT 2

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8

#define	_CMU_HFPERCLKDIV_MASK 0x0000010FUL

#define	_CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL

#define	_CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL

#define	_CMU_HFPERCLKEN0_ACMP0_SHIFT 9

#define	_CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL

#define	_CMU_HFPERCLKEN0_ACMP1_SHIFT 10

#define	_CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL

#define	_CMU_HFPERCLKEN0_ADC0_SHIFT 16

#define	_CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL

#define	_CMU_HFPERCLKEN0_DAC0_SHIFT 17

#define	_CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL

#define	_CMU_HFPERCLKEN0_GPIO_SHIFT 13

#define	_CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_I2C0_MASK 0x800UL

#define	_CMU_HFPERCLKEN0_I2C0_SHIFT 11

#define	_CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL

#define	_CMU_HFPERCLKEN0_I2C1_SHIFT 12

#define	_CMU_HFPERCLKEN0_MASK 0x0003FFFFUL

#define	_CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_PRS_MASK 0x8000UL

#define	_CMU_HFPERCLKEN0_PRS_SHIFT 15

#define	_CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL

#define	_CMU_HFPERCLKEN0_TIMER0_SHIFT 5

#define	_CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL

#define	_CMU_HFPERCLKEN0_TIMER1_SHIFT 6

#define	_CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL

#define	_CMU_HFPERCLKEN0_TIMER2_SHIFT 7

#define	_CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL

#define	_CMU_HFPERCLKEN0_TIMER3_SHIFT 8

#define	_CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_UART0_MASK 0x8UL

#define	_CMU_HFPERCLKEN0_UART0_SHIFT 3

#define	_CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_UART1_MASK 0x10UL

#define	_CMU_HFPERCLKEN0_UART1_SHIFT 4

#define	_CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USART0_MASK 0x1UL

#define	_CMU_HFPERCLKEN0_USART0_SHIFT 0

#define	_CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USART1_MASK 0x2UL

#define	_CMU_HFPERCLKEN0_USART1_SHIFT 1

#define	_CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USART2_MASK 0x4UL

#define	_CMU_HFPERCLKEN0_USART2_SHIFT 2

#define	_CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL

#define	_CMU_HFPERCLKEN0_VCMP_SHIFT 14

#define	_CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL

#define	_CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL

#define	_CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL

#define	_CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL

#define	_CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL

#define	_CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL

#define	_CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL

#define	_CMU_HFRCOCTRL_BAND_MASK 0x700UL

#define	_CMU_HFRCOCTRL_BAND_SHIFT 8

#define	_CMU_HFRCOCTRL_MASK 0x0001F7FFUL

#define	_CMU_HFRCOCTRL_RESETVALUE 0x00000380UL

#define	_CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL

#define	_CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL

#define	_CMU_HFRCOCTRL_SUDELAY_SHIFT 12

#define	_CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL

#define	_CMU_HFRCOCTRL_TUNING_MASK 0xFFUL

#define	_CMU_HFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IEN_AUXHFRCORDY_SHIFT 4

#define	_CMU_IEN_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IEN_CALOF_MASK 0x40UL

#define	_CMU_IEN_CALOF_SHIFT 6

#define	_CMU_IEN_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_CALRDY_MASK 0x20UL

#define	_CMU_IEN_CALRDY_SHIFT 5

#define	_CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_HFRCORDY_MASK 0x1UL

#define	_CMU_IEN_HFRCORDY_SHIFT 0

#define	_CMU_IEN_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_HFXORDY_MASK 0x2UL

#define	_CMU_IEN_HFXORDY_SHIFT 1

#define	_CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_LFRCORDY_MASK 0x4UL

#define	_CMU_IEN_LFRCORDY_SHIFT 2

#define	_CMU_IEN_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_LFXORDY_MASK 0x8UL

#define	_CMU_IEN_LFXORDY_SHIFT 3

#define	_CMU_IEN_MASK 0x000000FFUL

#define	_CMU_IEN_RESETVALUE 0x00000000UL

#define	_CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IEN_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IEN_USBCHFCLKSEL_SHIFT 7

#define	_CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IF_AUXHFRCORDY_SHIFT 4

#define	_CMU_IF_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IF_CALOF_MASK 0x40UL

#define	_CMU_IF_CALOF_SHIFT 6

#define	_CMU_IF_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IF_CALRDY_MASK 0x20UL

#define	_CMU_IF_CALRDY_SHIFT 5

#define	_CMU_IF_HFRCORDY_DEFAULT 0x00000001UL

#define	_CMU_IF_HFRCORDY_MASK 0x1UL

#define	_CMU_IF_HFRCORDY_SHIFT 0

#define	_CMU_IF_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_HFXORDY_MASK 0x2UL

#define	_CMU_IF_HFXORDY_SHIFT 1

#define	_CMU_IF_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_LFRCORDY_MASK 0x4UL

#define	_CMU_IF_LFRCORDY_SHIFT 2

#define	_CMU_IF_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_LFXORDY_MASK 0x8UL

#define	_CMU_IF_LFXORDY_SHIFT 3

#define	_CMU_IF_MASK 0x000000FFUL

#define	_CMU_IF_RESETVALUE 0x00000001UL

#define	_CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IF_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IF_USBCHFCLKSEL_SHIFT 7

#define	_CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IFC_AUXHFRCORDY_SHIFT 4

#define	_CMU_IFC_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IFC_CALOF_MASK 0x40UL

#define	_CMU_IFC_CALOF_SHIFT 6

#define	_CMU_IFC_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_CALRDY_MASK 0x20UL

#define	_CMU_IFC_CALRDY_SHIFT 5

#define	_CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_HFRCORDY_MASK 0x1UL

#define	_CMU_IFC_HFRCORDY_SHIFT 0

#define	_CMU_IFC_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_HFXORDY_MASK 0x2UL

#define	_CMU_IFC_HFXORDY_SHIFT 1

#define	_CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_LFRCORDY_MASK 0x4UL

#define	_CMU_IFC_LFRCORDY_SHIFT 2

#define	_CMU_IFC_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_LFXORDY_MASK 0x8UL

#define	_CMU_IFC_LFXORDY_SHIFT 3

#define	_CMU_IFC_MASK 0x000000FFUL

#define	_CMU_IFC_RESETVALUE 0x00000000UL

#define	_CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IFC_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IFC_USBCHFCLKSEL_SHIFT 7

#define	_CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IFS_AUXHFRCORDY_SHIFT 4

#define	_CMU_IFS_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IFS_CALOF_MASK 0x40UL

#define	_CMU_IFS_CALOF_SHIFT 6

#define	_CMU_IFS_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_CALRDY_MASK 0x20UL

#define	_CMU_IFS_CALRDY_SHIFT 5

#define	_CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_HFRCORDY_MASK 0x1UL

#define	_CMU_IFS_HFRCORDY_SHIFT 0

#define	_CMU_IFS_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_HFXORDY_MASK 0x2UL

#define	_CMU_IFS_HFXORDY_SHIFT 1

#define	_CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_LFRCORDY_MASK 0x4UL

#define	_CMU_IFS_LFRCORDY_SHIFT 2

#define	_CMU_IFS_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_LFXORDY_MASK 0x8UL

#define	_CMU_IFS_LFXORDY_SHIFT 3

#define	_CMU_IFS_MASK 0x000000FFUL

#define	_CMU_IFS_RESETVALUE 0x00000000UL

#define	_CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IFS_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IFS_USBCHFCLKSEL_SHIFT 7

#define	_CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL

#define	_CMU_LCDCTRL_FDIV_MASK 0x7UL

#define	_CMU_LCDCTRL_FDIV_SHIFT 0

#define	_CMU_LCDCTRL_MASK 0x0000007FUL

#define	_CMU_LCDCTRL_RESETVALUE 0x00000020UL

#define	_CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL

#define	_CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL

#define	_CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL

#define	_CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL

#define	_CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL

#define	_CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL

#define	_CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL

#define	_CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL

#define	_CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL

#define	_CMU_LCDCTRL_VBFDIV_MASK 0x70UL

#define	_CMU_LCDCTRL_VBFDIV_SHIFT 4

#define	_CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL

#define	_CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL

#define	_CMU_LCDCTRL_VBOOSTEN_SHIFT 3

#define	_CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_LCD_MASK 0x8UL

#define	_CMU_LFACLKEN0_LCD_SHIFT 3

#define	_CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_LESENSE_MASK 0x1UL

#define	_CMU_LFACLKEN0_LESENSE_SHIFT 0

#define	_CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_LETIMER0_MASK 0x4UL

#define	_CMU_LFACLKEN0_LETIMER0_SHIFT 2

#define	_CMU_LFACLKEN0_MASK 0x0000000FUL

#define	_CMU_LFACLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_RTC_MASK 0x2UL

#define	_CMU_LFACLKEN0_RTC_SHIFT 1

#define	_CMU_LFAPRESC0_LCD_DIV128 0x00000003UL

#define	_CMU_LFAPRESC0_LCD_DIV16 0x00000000UL

#define	_CMU_LFAPRESC0_LCD_DIV32 0x00000001UL

#define	_CMU_LFAPRESC0_LCD_DIV64 0x00000002UL

#define	_CMU_LFAPRESC0_LCD_MASK 0x3000UL

#define	_CMU_LFAPRESC0_LCD_SHIFT 12

#define	_CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_LESENSE_MASK 0x3UL

#define	_CMU_LFAPRESC0_LESENSE_SHIFT 0

#define	_CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL

#define	_CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL

#define	_CMU_LFAPRESC0_LETIMER0_SHIFT 8

#define	_CMU_LFAPRESC0_MASK 0x00003FF3UL

#define	_CMU_LFAPRESC0_RESETVALUE 0x00000000UL

#define	_CMU_LFAPRESC0_RTC_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL

#define	_CMU_LFAPRESC0_RTC_DIV128 0x00000007UL

#define	_CMU_LFAPRESC0_RTC_DIV16 0x00000004UL

#define	_CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL

#define	_CMU_LFAPRESC0_RTC_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL

#define	_CMU_LFAPRESC0_RTC_DIV256 0x00000008UL

#define	_CMU_LFAPRESC0_RTC_DIV32 0x00000005UL

#define	_CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL

#define	_CMU_LFAPRESC0_RTC_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL

#define	_CMU_LFAPRESC0_RTC_DIV512 0x00000009UL

#define	_CMU_LFAPRESC0_RTC_DIV64 0x00000006UL

#define	_CMU_LFAPRESC0_RTC_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL

#define	_CMU_LFAPRESC0_RTC_MASK 0xF0UL

#define	_CMU_LFAPRESC0_RTC_SHIFT 4

#define	_CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL

#define	_CMU_LFBCLKEN0_LEUART0_MASK 0x1UL

#define	_CMU_LFBCLKEN0_LEUART0_SHIFT 0

#define	_CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL

#define	_CMU_LFBCLKEN0_LEUART1_MASK 0x2UL

#define	_CMU_LFBCLKEN0_LEUART1_SHIFT 1

#define	_CMU_LFBCLKEN0_MASK 0x00000003UL

#define	_CMU_LFBCLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL

#define	_CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL

#define	_CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL

#define	_CMU_LFBPRESC0_LEUART0_MASK 0x3UL

#define	_CMU_LFBPRESC0_LEUART0_SHIFT 0

#define	_CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL

#define	_CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL

#define	_CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL

#define	_CMU_LFBPRESC0_LEUART1_MASK 0x30UL

#define	_CMU_LFBPRESC0_LEUART1_SHIFT 4

#define	_CMU_LFBPRESC0_MASK 0x00000033UL

#define	_CMU_LFBPRESC0_RESETVALUE 0x00000000UL

#define	_CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL

#define	_CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL

#define	_CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_LFA_LFXO 0x00000002UL

#define	_CMU_LFCLKSEL_LFA_MASK 0x3UL

#define	_CMU_LFCLKSEL_LFA_SHIFT 0

#define	_CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL

#define	_CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFAE_MASK 0x10000UL

#define	_CMU_LFCLKSEL_LFAE_SHIFT 16

#define	_CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL

#define	_CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL

#define	_CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_LFB_LFXO 0x00000002UL

#define	_CMU_LFCLKSEL_LFB_MASK 0xCUL

#define	_CMU_LFCLKSEL_LFB_SHIFT 2

#define	_CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL

#define	_CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFBE_MASK 0x100000UL

#define	_CMU_LFCLKSEL_LFBE_SHIFT 20

#define	_CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_MASK 0x0011000FUL

#define	_CMU_LFCLKSEL_RESETVALUE 0x00000005UL

#define	_CMU_LFRCOCTRL_MASK 0x0000007FUL

#define	_CMU_LFRCOCTRL_RESETVALUE 0x00000040UL

#define	_CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL

#define	_CMU_LFRCOCTRL_TUNING_MASK 0x7FUL

#define	_CMU_LFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_CMU_LOCK_LOCKKEY_LOCK 0x00000000UL

#define	_CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_CMU_LOCK_LOCKKEY_MASK 0xFFFFUL

#define	_CMU_LOCK_LOCKKEY_SHIFT 0

#define	_CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL

#define	_CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_CMU_LOCK_MASK 0x0000FFFFUL

#define	_CMU_LOCK_RESETVALUE 0x00000000UL

#define	_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL

#define	_CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5

#define	_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL

#define	_CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4

#define	_CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFRCODIS_MASK 0x2UL

#define	_CMU_OSCENCMD_HFRCODIS_SHIFT 1

#define	_CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFRCOEN_MASK 0x1UL

#define	_CMU_OSCENCMD_HFRCOEN_SHIFT 0

#define	_CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFXODIS_MASK 0x8UL

#define	_CMU_OSCENCMD_HFXODIS_SHIFT 3

#define	_CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFXOEN_MASK 0x4UL

#define	_CMU_OSCENCMD_HFXOEN_SHIFT 2

#define	_CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFRCODIS_MASK 0x80UL

#define	_CMU_OSCENCMD_LFRCODIS_SHIFT 7

#define	_CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFRCOEN_MASK 0x40UL

#define	_CMU_OSCENCMD_LFRCOEN_SHIFT 6

#define	_CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFXODIS_MASK 0x200UL

#define	_CMU_OSCENCMD_LFXODIS_SHIFT 9

#define	_CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFXOEN_MASK 0x100UL

#define	_CMU_OSCENCMD_LFXOEN_SHIFT 8

#define	_CMU_OSCENCMD_MASK 0x000003FFUL

#define	_CMU_OSCENCMD_RESETVALUE 0x00000000UL

#define	_CMU_PCNTCTRL_MASK 0x0000003FUL

#define	_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL

#define	_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1

#define	_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL

#define	_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2

#define	_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL

#define	_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL

#define	_CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3

#define	_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL

#define	_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4

#define	_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL

#define	_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL

#define	_CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5

#define	_CMU_PCNTCTRL_RESETVALUE 0x00000000UL

#define	_CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL

#define	_CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL

#define	_CMU_ROUTE_CLKOUT0PEN_SHIFT 0

#define	_CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL

#define	_CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL

#define	_CMU_ROUTE_CLKOUT1PEN_SHIFT 1

#define	_CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL

#define	_CMU_ROUTE_LOCATION_LOC0 0x00000000UL

#define	_CMU_ROUTE_LOCATION_LOC1 0x00000001UL

#define	_CMU_ROUTE_LOCATION_LOC2 0x00000002UL

#define	_CMU_ROUTE_LOCATION_MASK 0x1CUL

#define	_CMU_ROUTE_LOCATION_SHIFT 2

#define	_CMU_ROUTE_MASK 0x0000001FUL

#define	_CMU_ROUTE_RESETVALUE 0x00000000UL

#define	_CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_AUXHFRCOENS_MASK 0x10UL

#define	_CMU_STATUS_AUXHFRCOENS_SHIFT 4

#define	_CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_AUXHFRCORDY_MASK 0x20UL

#define	_CMU_STATUS_AUXHFRCORDY_SHIFT 5

#define	_CMU_STATUS_CALBSY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_CALBSY_MASK 0x4000UL

#define	_CMU_STATUS_CALBSY_SHIFT 14

#define	_CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL

#define	_CMU_STATUS_HFRCOENS_MASK 0x1UL

#define	_CMU_STATUS_HFRCOENS_SHIFT 0

#define	_CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL

#define	_CMU_STATUS_HFRCORDY_MASK 0x2UL

#define	_CMU_STATUS_HFRCORDY_SHIFT 1

#define	_CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL

#define	_CMU_STATUS_HFRCOSEL_MASK 0x400UL

#define	_CMU_STATUS_HFRCOSEL_SHIFT 10

#define	_CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_HFXOENS_MASK 0x4UL

#define	_CMU_STATUS_HFXOENS_SHIFT 2

#define	_CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_HFXORDY_MASK 0x8UL

#define	_CMU_STATUS_HFXORDY_SHIFT 3

#define	_CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_HFXOSEL_MASK 0x800UL

#define	_CMU_STATUS_HFXOSEL_SHIFT 11

#define	_CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFRCOENS_MASK 0x40UL

#define	_CMU_STATUS_LFRCOENS_SHIFT 6

#define	_CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFRCORDY_MASK 0x80UL

#define	_CMU_STATUS_LFRCORDY_SHIFT 7

#define	_CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFRCOSEL_MASK 0x1000UL

#define	_CMU_STATUS_LFRCOSEL_SHIFT 12

#define	_CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFXOENS_MASK 0x100UL

#define	_CMU_STATUS_LFXOENS_SHIFT 8

#define	_CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFXORDY_MASK 0x200UL

#define	_CMU_STATUS_LFXORDY_SHIFT 9

#define	_CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFXOSEL_MASK 0x2000UL

#define	_CMU_STATUS_LFXOSEL_SHIFT 13

#define	_CMU_STATUS_MASK 0x0003FFFFUL

#define	_CMU_STATUS_RESETVALUE 0x00000403UL

#define	_CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL

#define	_CMU_STATUS_USBCHFCLKSEL_SHIFT 15

#define	_CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL

#define	_CMU_STATUS_USBCLFRCOSEL_SHIFT 17

#define	_CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL

#define	_CMU_STATUS_USBCLFXOSEL_SHIFT 16

#define	_CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL

#define	_CMU_SYNCBUSY_LFACLKEN0_SHIFT 0

#define	_CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL

#define	_CMU_SYNCBUSY_LFAPRESC0_SHIFT 2

#define	_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL

#define	_CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4

#define	_CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL

#define	_CMU_SYNCBUSY_LFBPRESC0_SHIFT 6

#define	_CMU_SYNCBUSY_MASK 0x00000055UL

#define	_CMU_SYNCBUSY_RESETVALUE 0x00000000UL

#define	CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)

#define	CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)

#define	CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)

#define	CMU_CALCTRL_CONT (0x1UL << 6)

#define	CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)

#define	CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)

#define	CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)

#define	CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)

#define	CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)

#define	CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)

#define	CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)

#define	CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)

#define	CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)

#define	CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)

#define	CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)

#define	CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)

#define	CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)

#define	CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)

#define	CMU_CMD_CALSTART (0x1UL << 3)

#define	CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)

#define	CMU_CMD_CALSTOP (0x1UL << 4)

#define	CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)

#define	CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)

#define	CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)

#define	CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)

#define	CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)

#define	CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)

#define	CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)

#define	CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5)

#define	CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5)

#define	CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5)

#define	CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)

#define	CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)

#define	CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)

#define	CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)

#define	CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)

#define	CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)

#define	CMU_CTRL_DBGCLK (0x1UL << 28)

#define	CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)

#define	CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28)

#define	CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28)

#define	CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)

#define	CMU_CTRL_HFLE (0x1UL << 30)

#define	CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30)

#define	CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)

#define	CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5)

#define	CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)

#define	CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)

#define	CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)

#define	CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)

#define	CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)

#define	CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)

#define	CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)

#define	CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)

#define	CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)

#define	CMU_CTRL_LFXOBOOST (0x1UL << 13)

#define	CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)

#define	CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)

#define	CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)

#define	CMU_CTRL_LFXOBUFCUR (0x1UL << 17)

#define	CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)

#define	CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)

#define	CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)

#define	CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)

#define	CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)

#define	CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)

#define	CMU_FREEZE_REGFREEZE (0x1UL << 0)

#define	CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)

#define	CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)

#define	CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)

#define	CMU_HFCORECLKEN0_AES (0x1UL << 1)

#define	CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)

#define	CMU_HFCORECLKEN0_DMA (0x1UL << 0)

#define	CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)

#define	CMU_HFCORECLKEN0_EBI (0x1UL << 5)

#define	CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5)

#define	CMU_HFCORECLKEN0_LE (0x1UL << 4)

#define	CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)

#define	CMU_HFCORECLKEN0_USB (0x1UL << 3)

#define	CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)

#define	CMU_HFCORECLKEN0_USBC (0x1UL << 2)

#define	CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)

#define	CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)

#define	CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9)

#define	CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)

#define	CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10)

#define	CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10)

#define	CMU_HFPERCLKEN0_ADC0 (0x1UL << 16)

#define	CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)

#define	CMU_HFPERCLKEN0_DAC0 (0x1UL << 17)

#define	CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)

#define	CMU_HFPERCLKEN0_GPIO (0x1UL << 13)

#define	CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)

#define	CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)

#define	CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)

#define	CMU_HFPERCLKEN0_I2C1 (0x1UL << 12)

#define	CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)

#define	CMU_HFPERCLKEN0_PRS (0x1UL << 15)

#define	CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)

#define	CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5)

#define	CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5)

#define	CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6)

#define	CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6)

#define	CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7)

#define	CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7)

#define	CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8)

#define	CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8)

#define	CMU_HFPERCLKEN0_UART0 (0x1UL << 3)

#define	CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)

#define	CMU_HFPERCLKEN0_UART1 (0x1UL << 4)

#define	CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4)

#define	CMU_HFPERCLKEN0_USART0 (0x1UL << 0)

#define	CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)

#define	CMU_HFPERCLKEN0_USART1 (0x1UL << 1)

#define	CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)

#define	CMU_HFPERCLKEN0_USART2 (0x1UL << 2)

#define	CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)

#define	CMU_HFPERCLKEN0_VCMP (0x1UL << 14)

#define	CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)

#define	CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)

#define	CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)

#define	CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)

#define	CMU_IEN_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IEN_CALOF (0x1UL << 6)

#define	CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)

#define	CMU_IEN_CALRDY (0x1UL << 5)

#define	CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)

#define	CMU_IEN_HFRCORDY (0x1UL << 0)

#define	CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)

#define	CMU_IEN_HFXORDY (0x1UL << 1)

#define	CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)

#define	CMU_IEN_LFRCORDY (0x1UL << 2)

#define	CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)

#define	CMU_IEN_LFXORDY (0x1UL << 3)

#define	CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)

#define	CMU_IEN_USBCHFCLKSEL (0x1UL << 7)

#define	CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7)

#define	CMU_IF_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IF_CALOF (0x1UL << 6)

#define	CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)

#define	CMU_IF_CALRDY (0x1UL << 5)

#define	CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)

#define	CMU_IF_HFRCORDY (0x1UL << 0)

#define	CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)

#define	CMU_IF_HFXORDY (0x1UL << 1)

#define	CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)

#define	CMU_IF_LFRCORDY (0x1UL << 2)

#define	CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)

#define	CMU_IF_LFXORDY (0x1UL << 3)

#define	CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)

#define	CMU_IF_USBCHFCLKSEL (0x1UL << 7)

#define	CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7)

#define	CMU_IFC_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IFC_CALOF (0x1UL << 6)

#define	CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)

#define	CMU_IFC_CALRDY (0x1UL << 5)

#define	CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)

#define	CMU_IFC_HFRCORDY (0x1UL << 0)

#define	CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)

#define	CMU_IFC_HFXORDY (0x1UL << 1)

#define	CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)

#define	CMU_IFC_LFRCORDY (0x1UL << 2)

#define	CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)

#define	CMU_IFC_LFXORDY (0x1UL << 3)

#define	CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)

#define	CMU_IFC_USBCHFCLKSEL (0x1UL << 7)

#define	CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7)

#define	CMU_IFS_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IFS_CALOF (0x1UL << 6)

#define	CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)

#define	CMU_IFS_CALRDY (0x1UL << 5)

#define	CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)

#define	CMU_IFS_HFRCORDY (0x1UL << 0)

#define	CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)

#define	CMU_IFS_HFXORDY (0x1UL << 1)

#define	CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)

#define	CMU_IFS_LFRCORDY (0x1UL << 2)

#define	CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)

#define	CMU_IFS_LFXORDY (0x1UL << 3)

#define	CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)

#define	CMU_IFS_USBCHFCLKSEL (0x1UL << 7)

#define	CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7)

#define	CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0)

#define	CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)

#define	CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)

#define	CMU_LCDCTRL_VBOOSTEN (0x1UL << 3)

#define	CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3)

#define	CMU_LFACLKEN0_LCD (0x1UL << 3)

#define	CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3)

#define	CMU_LFACLKEN0_LESENSE (0x1UL << 0)

#define	CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)

#define	CMU_LFACLKEN0_LETIMER0 (0x1UL << 2)

#define	CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)

#define	CMU_LFACLKEN0_RTC (0x1UL << 1)

#define	CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1)

#define	CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12)

#define	CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12)

#define	CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12)

#define	CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12)

#define	CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)

#define	CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)

#define	CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)

#define	CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)

#define	CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)

#define	CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)

#define	CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4)

#define	CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4)

#define	CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4)

#define	CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4)

#define	CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4)

#define	CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4)

#define	CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4)

#define	CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4)

#define	CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4)

#define	CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4)

#define	CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4)

#define	CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4)

#define	CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4)

#define	CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4)

#define	CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4)

#define	CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4)

#define	CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)

#define	CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)

#define	CMU_LFBCLKEN0_LEUART1 (0x1UL << 1)

#define	CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)

#define	CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)

#define	CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)

#define	CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)

#define	CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)

#define	CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)

#define	CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)

#define	CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)

#define	CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)

#define	CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)

#define	CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)

#define	CMU_LFCLKSEL_LFAE (0x1UL << 16)

#define	CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)

#define	CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)

#define	CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)

#define	CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)

#define	CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)

#define	CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)

#define	CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)

#define	CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)

#define	CMU_LFCLKSEL_LFBE (0x1UL << 20)

#define	CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)

#define	CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)

#define	CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)

#define	CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)

#define	CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)

#define	CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)

#define	CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)

#define	CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)

#define	CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)

#define	CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)

#define	CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)

#define	CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)

#define	CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)

#define	CMU_OSCENCMD_HFRCODIS (0x1UL << 1)

#define	CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)

#define	CMU_OSCENCMD_HFRCOEN (0x1UL << 0)

#define	CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)

#define	CMU_OSCENCMD_HFXODIS (0x1UL << 3)

#define	CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)

#define	CMU_OSCENCMD_HFXOEN (0x1UL << 2)

#define	CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)

#define	CMU_OSCENCMD_LFRCODIS (0x1UL << 7)

#define	CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)

#define	CMU_OSCENCMD_LFRCOEN (0x1UL << 6)

#define	CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)

#define	CMU_OSCENCMD_LFXODIS (0x1UL << 9)

#define	CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)

#define	CMU_OSCENCMD_LFXOEN (0x1UL << 8)

#define	CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)

#define	CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)

#define	CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)

#define	CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)

#define	CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)

#define	CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)

#define	CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)

#define	CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2)

#define	CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)

#define	CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3)

#define	CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)

#define	CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)

#define	CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)

#define	CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4)

#define	CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)

#define	CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5)

#define	CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)

#define	CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)

#define	CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)

#define	CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)

#define	CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)

#define	CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)

#define	CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)

#define	CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)

#define	CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)

#define	CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)

#define	CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)

#define	CMU_STATUS_AUXHFRCOENS (0x1UL << 4)

#define	CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)

#define	CMU_STATUS_AUXHFRCORDY (0x1UL << 5)

#define	CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)

#define	CMU_STATUS_CALBSY (0x1UL << 14)

#define	CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)

#define	CMU_STATUS_HFRCOENS (0x1UL << 0)

#define	CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)

#define	CMU_STATUS_HFRCORDY (0x1UL << 1)

#define	CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)

#define	CMU_STATUS_HFRCOSEL (0x1UL << 10)

#define	CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)

#define	CMU_STATUS_HFXOENS (0x1UL << 2)

#define	CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)

#define	CMU_STATUS_HFXORDY (0x1UL << 3)

#define	CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)

#define	CMU_STATUS_HFXOSEL (0x1UL << 11)

#define	CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)

#define	CMU_STATUS_LFRCOENS (0x1UL << 6)

#define	CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)

#define	CMU_STATUS_LFRCORDY (0x1UL << 7)

#define	CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)

#define	CMU_STATUS_LFRCOSEL (0x1UL << 12)

#define	CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)

#define	CMU_STATUS_LFXOENS (0x1UL << 8)

#define	CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)

#define	CMU_STATUS_LFXORDY (0x1UL << 9)

#define	CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)

#define	CMU_STATUS_LFXOSEL (0x1UL << 13)

#define	CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)

#define	CMU_STATUS_USBCHFCLKSEL (0x1UL << 15)

#define	CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15)

#define	CMU_STATUS_USBCLFRCOSEL (0x1UL << 17)

#define	CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)

#define	CMU_STATUS_USBCLFXOSEL (0x1UL << 16)

#define	CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)

#define	CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)

#define	CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)

#define	CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)

#define	CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)

#define	CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)

#define	CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)

#define	CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)

#define	CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)

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