35 #if defined(RMU_COUNT) && (RMU_COUNT > 0)
69 #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL)
70 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
71 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL
72 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL
73 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL
74 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL
75 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL
76 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL
77 #define NUM_RSTCAUSES 7
80 #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL)
81 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
82 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL
83 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL
84 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL
85 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL
86 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL
87 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL
88 #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL
89 #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL
90 #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL
91 #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL
92 #define NUM_RSTCAUSES 11
95 #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL)
96 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
97 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL
98 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL
99 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL
100 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL
101 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL
102 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL
103 #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL
104 #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL
105 #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL
106 #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL
107 #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL
108 #define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL
109 #define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL
110 #define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL
111 #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL
112 #define NUM_RSTCAUSES 16
115 #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL)
116 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL
117 #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL
118 #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL
119 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL
120 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL
121 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL
122 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL
123 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL
124 #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL
125 #define NUM_RSTCAUSES 9
128 #error "RMU_RSTCAUSE XMASKs are not defined for this family."
131 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
133 #define ERRATA_FIX_EMU_E208_EN
144 uint32_t resetCauseMask;
146 uint32_t resetCauseZeroXMask;
147 } RMU_ResetCauseMasks_Typedef;
155 static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =
158 #if defined(RMU_RSTCAUSE_BODUNREGRST)
161 #if defined(RMU_RSTCAUSE_BODREGRST)
164 #if defined(RMU_RSTCAUSE_AVDDBOD)
165 { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
167 #if defined(RMU_RSTCAUSE_DVDDBOD)
168 { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
170 #if defined(RMU_RSTCAUSE_DECBOD)
171 { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
177 #if defined(RMU_RSTCAUSE_EM4RST)
180 #if defined(RMU_RSTCAUSE_EM4WURST)
183 #if defined(RMU_RSTCAUSE_BODAVDD0)
186 #if defined(RMU_RSTCAUSE_BODAVDD1)
189 #if defined(BU_PRESENT)
190 { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
191 { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
192 { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
193 { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
194 { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
202 #if defined(EMLIB_REGRESSION_TEST)
205 extern uint32_t rstCause;
225 #if defined(_RMU_CTRL_PINRMODE_MASK)
230 shift =
SL_CTZ((uint32_t)reset);
231 #if defined(_RMU_CTRL_PINRMODE_MASK)
232 val = (uint32_t)mode << shift;
233 RMU->CTRL = (
RMU->CTRL & ~reset) | val;
253 #if defined(EMU_AUXCTRL_HRCCLR)
293 #define LB_CLW0 (* ((volatile uint32_t *)(LOCKBITS_BASE) + 122))
294 #define LB_CLW0_PINRESETSOFT (1 << 2)
296 #if !defined(EMLIB_REGRESSION_TEST)
297 uint32_t rstCause =
RMU->RSTCAUSE;
299 uint32_t validRstCause = 0;
303 for (i = 0; i < NUM_RSTCAUSES; i++)
305 zeroXMask = resetCauseMasks[i].resetCauseZeroXMask;
306 #if defined( _SILICON_LABS_32B_SERIES_1 )
308 if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT))
311 switch (resetCauseMasks[i].resetCauseMask)
326 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
328 if (*(
volatile uint32_t *)(
EMU_BASE + 0x88) & (0x1 << 8))
330 zeroXMask &= ~(RMU_RSTCAUSE_DECBOD
331 | RMU_RSTCAUSE_DVDDBOD
332 | RMU_RSTCAUSE_AVDDBOD);
338 if ((rstCause & resetCauseMasks[i].resetCauseMask)
339 && !(rstCause & zeroXMask))
342 validRstCause |= resetCauseMasks[i].resetCauseMask;
345 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
349 validRstCause &= ~(RMU_RSTCAUSE_DECBOD
350 | RMU_RSTCAUSE_DVDDBOD
351 | RMU_RSTCAUSE_AVDDBOD);
354 return validRstCause;
uint32_t RMU_ResetCauseGet(void)
Get the cause of the last reset.
RAM and peripheral bit-field set and clear API.
#define RMU_RSTCAUSE_SYSREQRST
#define RMU_RSTCAUSE_EM4WURST
General purpose utilities.
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
__STATIC_INLINE void EMU_Lock(void)
Lock the EMU in order to protect its registers against unintended modification.
#define RMU_RSTCAUSE_LOCKUPRST
#define RMU_RSTCAUSE_EXTRST
#define RMU_RSTCAUSE_BODUNREGRST
void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
Disable/enable reset for various peripherals and signal sources.
#define RMU_RSTCAUSE_PORST
#define RMU_RSTCAUSE_BODREGRST
#define RMU_RSTCAUSE_BODAVDD1
#define RMU_RSTCAUSE_BODAVDD0
#define _EMU_AUXCTRL_HRCCLR_SHIFT
Reset Management Unit (RMU) peripheral API.
Energy management unit (EMU) peripheral API.
__STATIC_INLINE uint32_t SL_CTZ(uint32_t value)
Count trailing number of zeros. Use CLZ instruction if available.
#define EMU_LOCK_LOCKKEY_LOCKED
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define RMU_RSTCAUSE_EM4RST
void RMU_ResetCauseClear(void)
Clear the reset cause register.
#define RMU_RSTCAUSE_WDOGRST