34 #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
65 #define PCNT_REF_VALID(ref) ((ref) == PCNT0)
66 #elif (PCNT_COUNT == 2)
67 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
68 #elif (PCNT_COUNT == 3)
69 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
72 #error "Undefined number of pulse counters (PCNT)."
94 __STATIC_INLINE
unsigned int PCNT_Map(
PCNT_TypeDef *pcnt)
111 __STATIC_INLINE
void PCNT_Sync(
PCNT_TypeDef *pcnt, uint32_t mask)
148 EFM_ASSERT(PCNT_REF_VALID(pcnt));
186 EFM_ASSERT(PCNT_REF_VALID(pcnt));
199 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > count);
200 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > top);
207 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > count);
208 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > top);
288 EFM_ASSERT(PCNT_REF_VALID(pcnt));
299 #if defined(_PCNT_INPUT_MASK)
320 EFM_ASSERT(PCNT_REF_VALID(pcnt));
373 EFM_ASSERT(PCNT_REF_VALID(pcnt));
440 EFM_ASSERT(PCNT_REF_VALID(pcnt));
453 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->
counter);
454 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->
top);
461 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->
counter);
462 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->
top);
467 inst = PCNT_Map(pcnt);
469 #if defined(_PCNT_INPUT_MASK)
496 #if defined(PCNT_CTRL_HYST)
503 #if defined(PCNT_CTRL_S1CDIR)
511 #if defined(_PCNT_CTRL_CNTEV_SHIFT)
515 #if defined(_PCNT_CTRL_AUXCNTEV_SHIFT)
522 uint32_t auxCntEventField = 0;
648 EFM_ASSERT(PCNT_REF_VALID(pcnt));
651 inst = PCNT_Map(pcnt);
680 #if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
698 void PCNT_FilterConfiguration(
PCNT_TypeDef *pcnt,
const PCNT_Filter_TypeDef *config,
bool enable) {
701 EFM_ASSERT(PCNT_REF_VALID(pcnt));
704 ovscfg = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT)
705 | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT);
708 PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
709 pcnt->OVSCFG = ovscfg;
725 #if defined(PCNT_CTRL_TCCMODE_DEFAULT)
756 EFM_ASSERT(PCNT_REF_VALID(pcnt));
768 pcnt->
CTRL = (pcnt->
CTRL & (~mask)) | ctrl;
790 EFM_ASSERT(PCNT_REF_VALID(pcnt));
816 EFM_ASSERT(PCNT_REF_VALID(pcnt));
828 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > val);
835 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > val);
Clock management unit (CMU) API.
void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
Set counter and top values.
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
PCNT_TCCPresc_Typedef prescaler
void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode)
Set PCNT operational mode.
Emlib peripheral API "assert" implementation.
#define _PCNT_CTRL_TCCMODE_MASK
#define _PCNT_CTRL_MODE_SHIFT
RAM and peripheral bit-field set and clear API.
void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top value.
#define PCNT_CTRL_EDGE_NEG
#define PCNT_SYNCBUSY_TOPB
void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, PCNT_PRSInput_TypeDef prsInput, bool enable)
Enable/disable the selected PRS input of PCNT.
PCNT_TCCMode_TypeDef mode
#define PCNT_SYNCBUSY_CMD
Pulse Counter (PCNT) peripheral API.
PCNT_CntEvent_TypeDef cntEvent
#define _PCNT_INPUT_S1PRSSEL_SHIFT
#define _PCNT_INPUT_S1PRSEN_SHIFT
#define _PCNT_CTRL_CNTEV_SHIFT
#define _PCNT_CTRL_TCCPRESC_MASK
#define _PCNT_INPUT_S1PRSSEL_MASK
#define _PCNT_TOPB_RESETVALUE
#define _PCNT_CTRL_MODE_MASK
PCNT_CntEvent_TypeDef auxCntEvent
#define _PCNT_IEN_RESETVALUE
#define _PCNT_INPUT_S0PRSSEL_SHIFT
#define PCNT_FREEZE_REGFREEZE
void PCNT_CounterReset(PCNT_TypeDef *pcnt)
Reset PCNT counters and TOP register.
#define PCNT_CTRL_MODE_DISABLE
#define PCNT_CTRL_CNTDIR_DOWN
void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
Init pulse counter.
#define _PCNT_CTRL_TCCPRESC_SHIFT
PCNT_PRSSel_TypeDef s1PRS
#define _PCNT_CTRL_AUXCNTEV_SHIFT
PCNT_PRSSel_TypeDef s0PRS
PCNT_PRSSel_TypeDef tccPRS
void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top buffer value.
#define _PCNT_CTRL_TCCPRSPOL_SHIFT
#define _PCNT_CTRL_RSTEN_SHIFT
#define _PCNT_CTRL_RESETVALUE
#define PCNT_SYNCBUSY_CTRL
#define _PCNT_CTRL_PRSGATEEN_SHIFT
#define _PCNT_INPUT_S0PRSSEL_MASK
void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
PCNT register synchronization freeze control.
#define _PCNT_CTRL_TCCPRSPOL_MASK
#define _PCNT_CTRL_PRSGATEEN_MASK
#define _PCNT_CTRL_TCCPRSSEL_MASK
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _PCNT_CTRL_TCCCOMP_MASK
#define _PCNT_CTRL_TCCMODE_SHIFT
void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config)
Set Triggered Compare and Clear configuration.
PCNT_TCCComp_Typedef compare
#define _PCNT_CTRL_TCCCOMP_SHIFT
void PCNT_Reset(PCNT_TypeDef *pcnt)
Reset PCNT to same state as after a HW reset.
#define _PCNT_INPUT_S0PRSEN_SHIFT
#define _PCNT_CTRL_TCCPRSSEL_SHIFT