24 #define BOGUS_BYTE 0xFF
26 #define OPCODE_REG_READ 0x00
27 #define OPCODE_REG_WRITE 0x40
28 #define OPCODE_FIFO_READ 0x80
29 #define OPCODE_FIFO_WRITE 0xC0
30 #define ADDRESS_MS2B_POS 0x06
31 #define ADDRESS_SHIFT 0x02
32 #define BYTE_ENABLE 0x03
33 #define BYTE_ENABLE_SHIFT 0x02
38 #define ETH_CS_PORT gpioPortD
42 static SPIDRV_HandleData_t spiHandleData;
88 int remaining = numBytes;
118 int remaining = numBytes;
169 uint16_t value = 0x0000;
194 value = (rxBuffer[3] << 8) | rxBuffer[2];
228 txBuffer[2] = value & 0xff;
229 txBuffer[3] = (value >> 8) & 0xff;
259 EFM_ASSERT(numBytes >= 0 && numBytes < 12000);
260 EFM_ASSERT(data != NULL);
291 EFM_ASSERT(numBytes >= 0 && numBytes < 12000);
292 EFM_ASSERT(data != NULL);
SPI interface API for KSZ8851SNL Ethernet controller.
Emlib peripheral API "assert" implementation.
Ecode_t SPIDRV_MTransmitB(SPIDRV_Handle_t handle, const void *buffer, int count)
Start a SPI master blocking transmit transfer.
uint32_t dummyTxValue
The value to transmit when using SPI receive API functions.
MSB bit is transmitted first.
SPIDRV_BitOrder_t bitOrder
Bit order on SPI bus, MSB or LSB first.
Ecode_t SPIDRV_MTransferB(SPIDRV_Handle_t handle, const void *txBuffer, void *rxBuffer, int count)
Start a SPI master blocking transfer.
static void KSZ8851SNL_SPI_Transmit(int numBytes, const uint8_t *data)
Transmits a series of bytes over the spi link.
General purpose utilities.
static void KSZ8851SNL_SPI_Receive(int numBytes, uint8_t *buffer)
Receive a series of bytes over the spi link.
uint32_t bitRate
SPI bitrate.
void KSZ8851SNL_SPI_WriteFifo(int numBytes, const uint8_t *data)
Continue writing ethernet controller FIFO.
#define ECODE_EMDRV_SPIDRV_OK
Success return value.
uint16_t KSZ8851SNL_SPI_ReadRegister(uint8_t reg)
Read ethernet controller register.
void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out)
Set the mode for a GPIO pin.
General Purpose IO (GPIO) peripheral API.
#define OPCODE_FIFO_WRITE
void KSZ8851SNL_SPI_WriteFifoEnd(void)
Stop read/write the ethernet controller FIFO.
uint32_t Ecode_t
Typedef for API function error code return values.
#define BYTE_ENABLE_SHIFT
#define DMADRV_MAX_XFER_COUNT
Maximum length of one DMA transfer.
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out register to 1.
void KSZ8851SNL_SPI_ReadFifo(int numBytes, uint8_t *data)
Read data from the ethernet controller RX FIFO.
CS controlled by application.
static volatile uint8_t rxBuffer[RXBUFSIZE]
SPI mode 0: CLKPOL=0, CLKPHA=0.
void KSZ8851SNL_SPI_Init(void)
KSZ8851SNL_SPI_Init Initialize SPI interface to Ethernet controller.
Ecode_t SPIDRV_Init(SPIDRV_Handle_t handle, SPIDRV_Init_t *initData)
Initialize a SPI driver instance.
#define SL_MIN(a, b)
Macro for getting minimum value. No sideeffects, a and b are evaluated once only. ...
void KSZ8851SNL_SPI_WriteRegister(uint8_t reg, uint16_t value)
Write ethernet controller register.
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out port register to 0.
#define SPIDRV_MASTER_USART1
Configuration data for SPI master using USART1.
static void KSZ8851SNL_SPI_SetChipSelect(bool enable)
Select/deselect the ksz8851snl chip. This will clear/set the chip select GPIO pin connected to the ks...
uint32_t frameLength
SPI framelength, valid numbers are 4..16.
void KSZ8851SNL_SPI_WriteFifoBegin(void)
Start writing to the ethernet controller FIFO.
SPIDRV_CsControl_t csControl
Select master mode chip select (CS) control scheme.
SPIDRV_ClockMode_t clockMode
SPI mode, CLKPOL/CLKPHASE setting.
Ecode_t SPIDRV_MReceiveB(SPIDRV_Handle_t handle, void *buffer, int count)
Start a SPI master blocking receive transfer.