37 #if defined( EMU_PRESENT )
60 #if defined( _EMU_EM4CONF_OSC_MASK )
65 emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
67 emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
69 emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
73 #if defined( _EMU_BUCTRL_PROBE_MASK )
78 emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
80 emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
82 emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN,
84 emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT
88 #if defined( _EMU_PWRCONF_PWRRES_MASK )
93 emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
95 emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
97 emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
99 emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
100 } EMU_Resistor_TypeDef;
103 #if defined( BU_PRESENT )
108 emuPower_None = EMU_BUINACT_PWRCON_NONE,
111 emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
114 emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
116 emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
129 #if defined( _EMU_EM4CTRL_EM4STATE_MASK )
134 emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
136 emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,
137 } EMU_EM4State_TypeDef;
141 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
145 emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
147 emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
150 emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
151 } EMU_EM4PinRetention_TypeDef;
162 #if defined( _EMU_DCDCCTRL_MASK )
167 emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
169 emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
170 #if defined(_EMU_DCDCLPEM01CFG_MASK)
172 emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER,
174 } EMU_DcdcMode_TypeDef;
177 #if defined( _EMU_DCDCCTRL_MASK )
183 emuDcdcConductionMode_ContinuousLN,
186 emuDcdcConductionMode_DiscontinuousLN,
187 } EMU_DcdcConductionMode_TypeDef;
190 #if defined( _EMU_PWRCTRL_MASK )
195 emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
197 emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
198 } EMU_DcdcAnaPeripheralPower_TypeDef;
201 #if defined( _EMU_DCDCMISCCTRL_MASK )
203 typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
206 #define emuDcdcLnHighEfficiency -1
209 #define emuDcdcLnFastTransient 160
213 #if defined( _EMU_DCDCCTRL_MASK )
218 emuDcdcLnRcoBand_3MHz = 0,
220 emuDcdcLnRcoBand_4MHz = 1,
222 emuDcdcLnRcoBand_5MHz = 2,
224 emuDcdcLnRcoBand_6MHz = 3,
226 emuDcdcLnRcoBand_7MHz = 4,
228 emuDcdcLnRcoBand_8MHz = 5,
230 emuDcdcLnRcoBand_9MHz = 6,
232 emuDcdcLnRcoBand_10MHz = 7,
233 } EMU_DcdcLnRcoBand_TypeDef;
237 #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz
238 #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz
239 #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz
240 #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz
241 #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz
242 #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz
243 #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz
244 #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz
249 #if defined( _EMU_DCDCCTRL_MASK )
254 emuDcdcLnCompCtrl_1u0F,
256 emuDcdcLnCompCtrl_4u7F,
257 } EMU_DcdcLnCompCtrl_TypeDef;
261 #if defined( EMU_STATUS_VMONRDY )
266 emuVmonChannel_ALTAVDD,
268 emuVmonChannel_IOVDD0
269 } EMU_VmonChannel_TypeDef;
272 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
278 emuBiasMode_Continuous
279 } EMU_BiasMode_TypeDef;
282 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
287 emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
293 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0,
294 } EMU_VScaleEM01_TypeDef;
297 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
302 emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
306 emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
307 } EMU_VScaleEM23_TypeDef;
310 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
315 emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
319 emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
320 } EMU_VScaleEM4H_TypeDef;
323 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
327 emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK,
328 emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK,
329 emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,
330 emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK,
331 emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK,
332 emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK,
333 emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK,
334 emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK,
335 emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,
336 emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK,
337 emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK,
338 #if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
339 emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK,
340 emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK,
342 emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK,
344 emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
345 | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
346 | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
347 | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
348 | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,
349 emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
350 | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
351 | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
352 | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
353 | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
354 #if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
355 | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
356 | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
358 | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK
359 | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK,
360 emuPeripheralRetention_ALL = emuPeripheralRetention_D1
361 | emuPeripheralRetention_D2,
362 } EMU_PeripheralRetention_TypeDef;
369 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
375 bool vScaleEM01LowPowerVoltageEnable;
376 } EMU_EM01Init_TypeDef;
379 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
381 #define EMU_EM01INIT_DEFAULT \
391 #if defined( _EMU_CTRL_EM23VSCALE_MASK )
392 EMU_VScaleEM23_TypeDef vScaleEM23Voltage;
397 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
398 #define EMU_EM23INIT_DEFAULT \
401 emuVScaleEM23_FastWakeup, \
404 #define EMU_EM23INIT_DEFAULT \
410 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
414 #if defined( _EMU_EM4CONF_MASK )
418 EMU_EM4Osc_TypeDef osc;
421 #elif defined( _EMU_EM4CTRL_MASK )
426 EMU_EM4State_TypeDef em4State;
427 EMU_EM4PinRetention_TypeDef pinRetentionMode;
429 #if defined( _EMU_CTRL_EM4HVSCALE_MASK )
430 EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;
432 } EMU_EM4Init_TypeDef;
435 #if defined( _EMU_EM4CONF_MASK )
437 #define EMU_EM4INIT_DEFAULT \
446 #elif defined( _EMU_CTRL_EM4HVSCALE_MASK )
448 #define EMU_EM4INIT_DEFAULT \
454 emuPinRetentionDisable, \
455 emuVScaleEM4H_FastWakeup, \
458 #elif defined( _EMU_EM4CTRL_MASK )
460 #define EMU_EM4INIT_DEFAULT \
466 emuPinRetentionDisable, \
470 #if defined( BU_PRESENT )
477 EMU_Probe_TypeDef probe;
481 bool statusPinEnable;
485 EMU_Resistor_TypeDef resistor;
493 EMU_Power_TypeDef inactivePower;
495 EMU_Power_TypeDef activePower;
498 } EMU_BUPDInit_TypeDef;
501 #define EMU_BUPDINIT_DEFAULT \
518 #if defined( _EMU_DCDCCTRL_MASK )
524 EMU_DcdcMode_TypeDef dcdcMode;
526 uint16_t em01LoadCurrent_mA;
530 uint16_t em234LoadCurrent_uA;
534 uint16_t maxCurrent_mA;
537 EMU_DcdcAnaPeripheralPower_TypeDef
539 EMU_DcdcLnReverseCurrentControl_TypeDef
540 reverseCurrentControl;
545 EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl;
546 } EMU_DCDCInit_TypeDef;
549 #if defined( _EFM_DEVICE )
550 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
551 #define EMU_DCDCINIT_DEFAULT \
553 emuPowerConfig_DcdcToDvdd, \
554 emuDcdcMode_LowNoise, \
560 emuDcdcAnaPeripheralPower_DCDC, \
561 emuDcdcLnHighEfficiency, \
562 emuDcdcLnCompCtrl_1u0F, \
565 #define EMU_DCDCINIT_DEFAULT \
567 emuPowerConfig_DcdcToDvdd, \
568 emuDcdcMode_LowPower, \
574 emuDcdcAnaPeripheralPower_DCDC, \
575 emuDcdcLnHighEfficiency, \
576 emuDcdcLnCompCtrl_4u7F, \
581 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
582 #define EMU_DCDCINIT_DEFAULT \
584 emuPowerConfig_DcdcToDvdd, \
585 emuDcdcMode_LowNoise, \
591 emuDcdcAnaPeripheralPower_DCDC, \
593 emuDcdcLnCompCtrl_1u0F, \
596 #define EMU_DCDCINIT_DEFAULT \
598 emuPowerConfig_DcdcToDvdd, \
599 emuDcdcMode_LowNoise, \
605 emuDcdcAnaPeripheralPower_DCDC, \
607 emuDcdcLnCompCtrl_4u7F, \
613 #if defined( EMU_STATUS_VMONRDY )
617 EMU_VmonChannel_TypeDef channel;
623 } EMU_VmonInit_TypeDef;
626 #define EMU_VMONINIT_DEFAULT \
628 emuVmonChannel_AVDD, \
639 EMU_VmonChannel_TypeDef channel;
645 } EMU_VmonHystInit_TypeDef;
648 #define EMU_VMONHYSTINIT_DEFAULT \
650 emuVmonChannel_AVDD, \
663 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
664 void EMU_EM01Init(
const EMU_EM01Init_TypeDef *em01Init);
667 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
668 void EMU_EM4Init(
const EMU_EM4Init_TypeDef *em4Init);
674 #if defined( _EMU_EM4CTRL_MASK )
675 void EMU_EnterEM4H(
void);
676 void EMU_EnterEM4S(
void);
680 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
681 void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask,
bool enable);
684 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
685 void EMU_VScaleEM01ByClock(uint32_t clockFrequency,
bool wait);
686 void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage,
bool wait);
688 #if defined( BU_PRESENT )
689 void EMU_BUPDInit(
const EMU_BUPDInit_TypeDef *bupdInit);
693 #if defined( _EMU_DCDCCTRL_MASK )
694 bool EMU_DCDCInit(
const EMU_DCDCInit_TypeDef *dcdcInit);
702 #if defined( EMU_STATUS_VMONRDY )
703 void EMU_VmonInit(
const EMU_VmonInit_TypeDef *vmonInit);
704 void EMU_VmonHystInit(
const EMU_VmonHystInit_TypeDef *vmonInit);
705 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel,
bool enable);
706 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
716 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
721 #if defined( _EMU_STATUS_VSCALE_MASK )
726 __STATIC_INLINE
void EMU_VScaleWait(
void)
732 #if defined( _EMU_STATUS_VSCALE_MASK )
740 __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(
void)
743 return (EMU_VScaleEM01_TypeDef)((
EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
744 >> _EMU_STATUS_VSCALE_SHIFT);
748 #if defined( _EMU_STATUS_VMONRDY_MASK )
757 __STATIC_INLINE
bool EMU_VmonStatusGet(
void)
763 #if defined( _EMU_IF_MASK )
772 __STATIC_INLINE
void EMU_IntClear(uint32_t flags)
786 __STATIC_INLINE
void EMU_IntDisable(uint32_t flags)
805 __STATIC_INLINE
void EMU_IntEnable(uint32_t flags)
822 __STATIC_INLINE uint32_t EMU_IntGet(
void)
842 __STATIC_INLINE uint32_t EMU_IntGetEnabled(
void)
847 return EMU->IF & ien;
859 __STATIC_INLINE
void EMU_IntSet(uint32_t flags)
866 #if defined( _EMU_EM4CONF_LOCKCONF_MASK )
873 __STATIC_INLINE
void EMU_EM4Lock(
bool enable)
879 #if defined( _EMU_STATUS_BURDY_MASK )
884 __STATIC_INLINE
void EMU_BUReady(
void)
886 while(!(
EMU->STATUS & EMU_STATUS_BURDY))
891 #if defined( _EMU_ROUTE_BUVINPEN_MASK )
898 __STATIC_INLINE
void EMU_BUPinEnable(
bool enable)
932 #if defined( _EMU_PWRLOCK_MASK )
938 __STATIC_INLINE
void EMU_PowerLock(
void)
940 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
949 __STATIC_INLINE
void EMU_PowerUnlock(
void)
951 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
974 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
983 __STATIC_INLINE
void EMU_UnlatchPinRetention(
void)
985 EMU->CMD = EMU_CMD_EM4UNLATCH;
989 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
990 void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit)
Configure DCDC regulator.
bool EMU_DCDCPowerOff(void)
Power off the DCDC regulator.
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
RAM and peripheral bit-field set and clear API.
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage)
Set DCDC output voltage.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
#define EMU_LOCK_LOCKKEY_LOCK
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
__STATIC_INLINE void EMU_Lock(void)
Lock the EMU in order to protect its registers against unintended modification.
void EMU_Restore(void)
Restore CMU HF clock select state, oscillator enable and voltage scaling (if available) after EMU_Ent...
void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrent_mA)
Optimize DCDC slice count based on the estimated average load current in EM0.
#define EMU_LOCK_LOCKKEY_UNLOCK
#define _EMU_CTRL_EM2BLOCK_SHIFT
void EMU_RamPowerDown(uint32_t start, uint32_t end)
Power down RAM memory blocks.
__STATIC_INLINE void EMU_EnterEM1(void)
Enter energy mode 1 (EM1).
void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
Set DCDC Low-noise RCO band.
void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet)
Set DCDC LN regulator conduction mode.
__STATIC_INLINE void EMU_EM2UnBlock(void)
Unblock entering EM2 or higher number energy modes.
void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
Set DCDC regulator operating mode.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
__STATIC_INLINE void EMU_EM2Block(void)
Block entering EM2 or higher number energy modes.