34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
66 uint32_t ctrl =
EBI->CTRL;
68 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
83 EBI_BankPolaritySet(ebiInit->
banks, ebiLineBL, ebiInit->blPolarity);
98 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
105 | _EBI_CTRL_NOIDLE_MASK
110 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
111 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
119 ctrl &= ~(_EBI_CTRL_BL1_MASK
120 | _EBI_CTRL_MODE1_MASK
121 | _EBI_CTRL_ARDY1EN_MASK
122 | _EBI_CTRL_ARDYTO1DIS_MASK
123 | _EBI_CTRL_NOIDLE1_MASK
125 ctrl |= (ebiInit->
mode << _EBI_CTRL_MODE1_SHIFT);
126 ctrl |= (ebiInit->
ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
128 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
129 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
137 ctrl &= ~(_EBI_CTRL_BL2_MASK
138 | _EBI_CTRL_MODE2_MASK
139 | _EBI_CTRL_ARDY2EN_MASK
140 | _EBI_CTRL_ARDYTO2DIS_MASK
141 | _EBI_CTRL_NOIDLE2_MASK
143 ctrl |= (ebiInit->
mode << _EBI_CTRL_MODE2_SHIFT);
144 ctrl |= (ebiInit->
ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
146 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
147 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
155 ctrl &= ~(_EBI_CTRL_BL3_MASK
156 | _EBI_CTRL_MODE3_MASK
157 | _EBI_CTRL_ARDY3EN_MASK
158 | _EBI_CTRL_ARDYTO3DIS_MASK
159 | _EBI_CTRL_NOIDLE3_MASK
161 ctrl |= (ebiInit->
mode << _EBI_CTRL_MODE3_SHIFT);
162 ctrl |= (ebiInit->
ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
164 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
165 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
198 ctrl |= ebiInit->
mode;
204 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
205 EBI_BankReadTimingSet(ebiInit->
banks,
209 EBI_BankReadTimingConfig(ebiInit->
banks,
210 ebiInit->readPageMode,
211 ebiInit->readPrefetch,
212 ebiInit->readHalfRE);
213 EBI_BankWriteTimingSet(ebiInit->
banks,
217 EBI_BankWriteTimingConfig(ebiInit->
banks,
218 ebiInit->writeBufferDisable,
219 ebiInit->writeHalfWE);
220 EBI_BankAddressTimingSet(ebiInit->
banks,
223 EBI_BankAddressTimingConfig(ebiInit->
banks,
224 ebiInit->addrHalfALE);
240 switch (ebiInit->
mode)
247 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
255 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
257 EBI->ROUTE = (
EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
258 EBI->ROUTE = (
EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
260 EBI->ROUTE = (
EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
263 if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
332 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
333 if(
EBI->CTRL & EBI_CTRL_ALTMAP)
437 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
441 case ebiLineTFTVSync:
444 case ebiLineTFTHSync:
447 case ebiLineTFTDataEn:
483 EFM_ASSERT(setupCycles < 4);
484 EFM_ASSERT(strobeCycles < 16);
485 EFM_ASSERT(holdCycles < 4);
493 EBI->RDTIMING = (
EBI->RDTIMING
516 uint32_t writeTiming;
519 EFM_ASSERT(setupCycles < 4);
520 EFM_ASSERT(strobeCycles < 16);
521 EFM_ASSERT(holdCycles < 4);
528 EBI->WRTIMING = (
EBI->WRTIMING
549 uint32_t addressLatchTiming;
552 EFM_ASSERT(setupCycles < 4);
553 EFM_ASSERT(holdCycles < 4);
559 EBI->ADDRTIMING = (
EBI->ADDRTIMING
562 | addressLatchTiming;
565 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
573 void EBI_TFTInit(
const EBI_TFTInit_TypeDef *ebiTFTInit)
578 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
581 EBI_TFTSizeSet(ebiTFTInit->hsize,
583 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
584 ebiTFTInit->hPorchBack,
585 ebiTFTInit->hPulseWidth);
586 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
587 ebiTFTInit->vPorchBack,
588 ebiTFTInit->vPulseWidth);
591 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
592 ebiTFTInit->startPosition,
593 ebiTFTInit->setupCycles,
594 ebiTFTInit->holdCycles);
604 ctrl = (uint32_t)ebiTFTInit->bank
605 | (uint32_t)ebiTFTInit->width
606 | (uint32_t)ebiTFTInit->colSrc
607 | (uint32_t)ebiTFTInit->interleave
608 | (uint32_t)ebiTFTInit->fbTrigger
609 | (uint32_t)(ebiTFTInit->shiftDClk ==
true
610 ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
611 | (uint32_t)ebiTFTInit->maskBlend
612 | (uint32_t)ebiTFTInit->driveMode;
617 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
619 EBI->ROUTE |= EBI_ROUTE_TFTPEN;
633 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
635 EFM_ASSERT((horizontal-1) < 1024);
636 EFM_ASSERT((vertical-1) < 1024);
638 EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
639 | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
653 void EBI_TFTHPorchSet(
int front,
int back,
int pulseWidth)
655 EFM_ASSERT(front < 256);
656 EFM_ASSERT(back < 256);
657 EFM_ASSERT((pulseWidth-1) < 128);
659 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
660 | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
661 | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
676 void EBI_TFTVPorchSet(
int front,
int back,
int pulseWidth)
678 EFM_ASSERT(front < 256);
679 EFM_ASSERT(back < 256);
680 EFM_ASSERT((pulseWidth-1) < 128);
682 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
683 | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
684 | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
704 void EBI_TFTTimingSet(
int dclkPeriod,
int start,
int setup,
int hold)
706 EFM_ASSERT(dclkPeriod < 2048);
707 EFM_ASSERT(start < 2048);
708 EFM_ASSERT(setup < 4);
709 EFM_ASSERT(hold < 4);
711 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
712 | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
713 | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
714 | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
718 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
735 void EBI_BankReadTimingConfig(uint32_t banks,
bool pageMode,
bool prefetch,
bool halfRE)
784 void EBI_BankReadTimingSet(uint32_t banks,
int setupCycles,
int strobeCycles,
int holdCycles)
789 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 |
EBI_BANK3)) == 0);
792 EFM_ASSERT(setupCycles < 4);
793 EFM_ASSERT(strobeCycles < 64);
794 EFM_ASSERT(holdCycles < 4);
801 if (banks & EBI_BANK0)
803 EBI->RDTIMING = (
EBI->RDTIMING
809 if (banks & EBI_BANK1)
811 EBI->RDTIMING1 = (
EBI->RDTIMING1
812 & ~(_EBI_RDTIMING1_RDSETUP_MASK
813 | _EBI_RDTIMING1_RDSTRB_MASK
814 | _EBI_RDTIMING1_RDHOLD_MASK))
817 if (banks & EBI_BANK2)
819 EBI->RDTIMING2 = (
EBI->RDTIMING2
820 & ~(_EBI_RDTIMING2_RDSETUP_MASK
821 | _EBI_RDTIMING2_RDSTRB_MASK
822 | _EBI_RDTIMING2_RDHOLD_MASK))
827 EBI->RDTIMING3 = (
EBI->RDTIMING3
828 & ~(_EBI_RDTIMING3_RDSETUP_MASK
829 | _EBI_RDTIMING3_RDSTRB_MASK
830 | _EBI_RDTIMING3_RDHOLD_MASK))
849 void EBI_BankWriteTimingConfig(uint32_t banks,
bool writeBufDisable,
bool halfWE)
852 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 |
EBI_BANK3)) == 0);
855 if( banks & EBI_BANK0 )
860 if( banks & EBI_BANK1 )
865 if( banks & EBI_BANK2 )
894 void EBI_BankWriteTimingSet(uint32_t banks,
int setupCycles,
int strobeCycles,
int holdCycles)
896 uint32_t writeTiming;
899 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 |
EBI_BANK3)) == 0);
902 EFM_ASSERT(setupCycles < 4);
903 EFM_ASSERT(strobeCycles < 64);
904 EFM_ASSERT(holdCycles < 4);
911 if (banks & EBI_BANK0)
913 EBI->WRTIMING = (
EBI->WRTIMING
919 if (banks & EBI_BANK1)
921 EBI->WRTIMING1 = (
EBI->WRTIMING1
922 & ~(_EBI_WRTIMING1_WRSETUP_MASK
923 | _EBI_WRTIMING1_WRSTRB_MASK
924 | _EBI_WRTIMING1_WRHOLD_MASK))
927 if (banks & EBI_BANK2)
929 EBI->WRTIMING2 = (
EBI->WRTIMING2
930 & ~(_EBI_WRTIMING2_WRSETUP_MASK
931 | _EBI_WRTIMING2_WRSTRB_MASK
932 | _EBI_WRTIMING2_WRHOLD_MASK))
937 EBI->WRTIMING3 = (
EBI->WRTIMING3
938 & ~(_EBI_WRTIMING3_WRSETUP_MASK
939 | _EBI_WRTIMING3_WRSTRB_MASK
940 | _EBI_WRTIMING3_WRHOLD_MASK))
956 void EBI_BankAddressTimingConfig(uint32_t banks,
bool halfALE)
959 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 |
EBI_BANK3)) == 0);
961 if( banks & EBI_BANK0 )
965 if( banks & EBI_BANK1 )
969 if( banks & EBI_BANK2 )
994 void EBI_BankAddressTimingSet(uint32_t banks,
int setupCycles,
int holdCycles)
996 uint32_t addressLatchTiming;
999 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 |
EBI_BANK3)) == 0);
1002 EFM_ASSERT(setupCycles < 4);
1003 EFM_ASSERT(holdCycles < 4);
1009 if (banks & EBI_BANK0)
1011 EBI->ADDRTIMING = (
EBI->ADDRTIMING
1014 | addressLatchTiming;
1016 if (banks & EBI_BANK1)
1018 EBI->ADDRTIMING1 = (
EBI->ADDRTIMING1
1019 & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
1020 | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
1021 | addressLatchTiming;
1023 if (banks & EBI_BANK2)
1025 EBI->ADDRTIMING2 = (
EBI->ADDRTIMING2
1026 & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
1027 | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
1028 | addressLatchTiming;
1032 EBI->ADDRTIMING3 = (
EBI->ADDRTIMING3
1033 & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
1034 | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
1035 | addressLatchTiming;
1056 uint32_t bankSet = 0;
1057 volatile uint32_t *polRegister = 0;
1060 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 |
EBI_BANK3)) == 0);
1064 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1065 if (banks & EBI_BANK0)
1067 polRegister = &
EBI->POLARITY;
1070 if (banks & EBI_BANK1)
1072 polRegister = &
EBI->POLARITY1;
1075 if (banks & EBI_BANK2)
1077 polRegister = &
EBI->POLARITY2;
1082 polRegister = &
EBI->POLARITY3;
1086 polRegister = &
EBI->POLARITY;
1108 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1112 case ebiLineTFTVSync:
1115 case ebiLineTFTHSync:
1118 case ebiLineTFTDataEn:
1121 case ebiLineTFTDClk:
1132 banks = banks & ~bankSet;
1148 void EBI_BankByteLaneEnable(uint32_t banks,
bool enable)
1151 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1154 if (banks & EBI_BANK0)
1158 if (banks & EBI_BANK1)
1162 if (banks & EBI_BANK2)
1166 if (banks & EBI_BANK3)
1181 void EBI_AltMapEnable(
bool enable)
#define _EBI_RDTIMING_RDHOLD_MASK
#define _EBI_CTRL_BANK3EN_MASK
#define _EBI_RDTIMING_RDHOLD_SHIFT
Emlib peripheral API "assert" implementation.
#define _EBI_CTRL_MODE_MASK
#define _EBI_ROUTE_CS3PEN_SHIFT
void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
Configure timing values of write bus accesses.
#define _EBI_CTRL_BANK2EN_MASK
#define _EBI_POLARITY_ARDYPOL_SHIFT
RAM and peripheral bit-field set and clear API.
uint32_t EBI_BankAddress(uint32_t bank)
Return base address of EBI bank.
EBI_Polarity_TypeDef csPolarity
#define _EBI_WRTIMING_WRHOLD_MASK
#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT
#define _EBI_POLARITY_REPOL_SHIFT
#define _EBI_CTRL_BANK0EN_MASK
#define _EBI_CTRL_BANK3EN_SHIFT
#define _EBI_ROUTE_RESETVALUE
void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
Configure EBI pin polarity.
#define _EBI_ROUTE_ALEPEN_SHIFT
#define _EBI_CTRL_ARDYEN_SHIFT
#define _EBI_ROUTE_CS0PEN_SHIFT
#define _EBI_POLARITY_CSPOL_SHIFT
#define _EBI_WRTIMING_WRHOLD_SHIFT
void EBI_AddressTimingSet(int setupCycles, int holdCycles)
Configure timing values of address latch bus accesses.
void EBI_BankEnable(uint32_t banks, bool enable)
Enable or disable EBI Bank.
External Bus Iterface (EBI) peripheral API.
#define _EBI_WRTIMING_WRSTRB_SHIFT
void EBI_ChipSelectEnable(uint32_t banks, bool enable)
Enable or disable EBI Chip Select.
void EBI_Init(const EBI_Init_TypeDef *ebiInit)
Configure and enable External Bus Interface.
#define _EBI_RDTIMING_RDSTRB_SHIFT
#define _EBI_POLARITY_WEPOL_SHIFT
void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
Configure timing values of read bus accesses.
#define _EBI_CTRL_BANK0EN_SHIFT
#define _EBI_ADDRTIMING_ADDRSETUP_MASK
#define _EBI_CTRL_BANK1EN_SHIFT
#define _EBI_ROUTE_CS1PEN_SHIFT
#define _EBI_ROUTE_CS2PEN_SHIFT
#define _EBI_ROUTE_EBIPEN_SHIFT
#define _EBI_ADDRTIMING_ADDRHOLD_MASK
#define _EBI_CTRL_RESETVALUE
EBI_Polarity_TypeDef rePolarity
#define _EBI_CTRL_BANK1EN_MASK
#define _EBI_WRTIMING_WRSTRB_MASK
EBI_Polarity_TypeDef alePolarity
#define _EBI_RDTIMING_RDSETUP_MASK
#define _EBI_WRTIMING_WRSETUP_SHIFT
#define _EBI_WRTIMING_WRSETUP_MASK
#define _EBI_CTRL_MODE_SHIFT
#define _EBI_CTRL_ARDYTODIS_SHIFT
#define _EBI_CTRL_ARDYEN_MASK
#define _EBI_POLARITY_ALEPOL_SHIFT
void EBI_Disable(void)
Disable External Bus Interface.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _EBI_RDTIMING_RDSTRB_MASK
#define _EBI_CTRL_BANK2EN_SHIFT
#define _EBI_ADDRTIMING_ADDRSETUP_SHIFT
EBI_Polarity_TypeDef wePolarity
#define _EBI_RDTIMING_RDSETUP_SHIFT
#define _EBI_CTRL_ARDYTODIS_MASK
EBI_Polarity_TypeDef ardyPolarity