EFM32 Gecko Software Documentation  efm32g-doc-5.1.2
efm32g_emu.h File Reference

Detailed Description

EFM32G_EMU register and bit field definitions.

Version
5.1.2

License

Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

  1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
  2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
  3. This notice may not be removed or altered from any source distribution.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

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Definition in file efm32g_emu.h.

Go to the source code of this file.

Data Structures

struct  EMU_TypeDef
 

Macros

#define _EMU_AUXCTRL_HRCCLR_DEFAULT   0x00000000UL
 
#define _EMU_AUXCTRL_HRCCLR_MASK   0x1UL
 
#define _EMU_AUXCTRL_HRCCLR_SHIFT   0
 
#define _EMU_AUXCTRL_MASK   0x00000001UL
 
#define _EMU_AUXCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_CTRL_EM2BLOCK_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM2BLOCK_MASK   0x2UL
 
#define _EMU_CTRL_EM2BLOCK_SHIFT   1
 
#define _EMU_CTRL_EM4CTRL_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM4CTRL_MASK   0xCUL
 
#define _EMU_CTRL_EM4CTRL_SHIFT   2
 
#define _EMU_CTRL_EMVREG_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EMVREG_FULL   0x00000001UL
 
#define _EMU_CTRL_EMVREG_MASK   0x1UL
 
#define _EMU_CTRL_EMVREG_REDUCED   0x00000000UL
 
#define _EMU_CTRL_EMVREG_SHIFT   0
 
#define _EMU_CTRL_MASK   0x0000000FUL
 
#define _EMU_CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _EMU_LOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _EMU_LOCK_LOCKKEY_SHIFT   0
 
#define _EMU_LOCK_LOCKKEY_UNLOCK   0x0000ADE8UL
 
#define _EMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _EMU_LOCK_MASK   0x0000FFFFUL
 
#define _EMU_LOCK_RESETVALUE   0x00000000UL
 
#define _EMU_MEMCTRL_MASK   0x00000007UL
 
#define _EMU_MEMCTRL_POWERDOWN_BLK123   0x00000007UL
 
#define _EMU_MEMCTRL_POWERDOWN_BLK23   0x00000006UL
 
#define _EMU_MEMCTRL_POWERDOWN_BLK3   0x00000004UL
 
#define _EMU_MEMCTRL_POWERDOWN_DEFAULT   0x00000000UL
 
#define _EMU_MEMCTRL_POWERDOWN_MASK   0x7UL
 
#define _EMU_MEMCTRL_POWERDOWN_SHIFT   0
 
#define _EMU_MEMCTRL_RESETVALUE   0x00000000UL
 
#define EMU_AUXCTRL_HRCCLR   (0x1UL << 0)
 
#define EMU_AUXCTRL_HRCCLR_DEFAULT   (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)
 
#define EMU_CTRL_EM2BLOCK   (0x1UL << 1)
 
#define EMU_CTRL_EM2BLOCK_DEFAULT   (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
 
#define EMU_CTRL_EM4CTRL_DEFAULT   (_EMU_CTRL_EM4CTRL_DEFAULT << 2)
 
#define EMU_CTRL_EMVREG   (0x1UL << 0)
 
#define EMU_CTRL_EMVREG_DEFAULT   (_EMU_CTRL_EMVREG_DEFAULT << 0)
 
#define EMU_CTRL_EMVREG_FULL   (_EMU_CTRL_EMVREG_FULL << 0)
 
#define EMU_CTRL_EMVREG_REDUCED   (_EMU_CTRL_EMVREG_REDUCED << 0)
 
#define EMU_LOCK_LOCKKEY_DEFAULT   (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
 
#define EMU_LOCK_LOCKKEY_LOCK   (_EMU_LOCK_LOCKKEY_LOCK << 0)
 
#define EMU_LOCK_LOCKKEY_LOCKED   (_EMU_LOCK_LOCKKEY_LOCKED << 0)
 
#define EMU_LOCK_LOCKKEY_UNLOCK   (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
 
#define EMU_LOCK_LOCKKEY_UNLOCKED   (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
 
#define EMU_MEMCTRL_POWERDOWN_BLK123   (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0)
 
#define EMU_MEMCTRL_POWERDOWN_BLK23   (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0)
 
#define EMU_MEMCTRL_POWERDOWN_BLK3   (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0)
 
#define EMU_MEMCTRL_POWERDOWN_DEFAULT   (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0)