EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
em_wdog.c
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1 /***************************************************************************/
34 #include "em_wdog.h"
35 #if defined(WDOG_COUNT) && (WDOG_COUNT > 0)
36 
37 #include "em_bus.h"
38 
39 /***************************************************************************/
44 /***************************************************************************/
54 /*******************************************************************************
55  ************************** GLOBAL FUNCTIONS *******************************
56  ******************************************************************************/
57 
58 /***************************************************************************/
75 void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
76 {
77  /* SYNCBUSY may stall when locked. */
78  if (wdog->CTRL & WDOG_CTRL_LOCK)
79  {
80  return;
81  }
82 
83  if (!enable)
84  {
85  /* If the user intends to disable and the WDOG is enabled */
87  {
88  /* Wait for any pending previous write operation to have been completed in */
89  /* low frequency domain */
90  while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
91  ;
92 
94  }
95  }
96  else
97  {
99  }
100 }
101 
102 
103 /***************************************************************************/
116 {
117  /* The watchdog should not be fed while it is disabled */
118  if (!(wdog->CTRL & WDOG_CTRL_EN))
119  {
120  return;
121  }
122 
123  /* If a previous clearing is being synchronized to LF domain, then there */
124  /* is no point in waiting for it to complete before clearing over again. */
125  /* This avoids stalling the core in the typical use case where some idle loop */
126  /* keeps clearing the watchdog. */
127  if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD)
128  {
129  return;
130  }
131  /* Before writing to the WDOG_CMD register we also need to make sure that
132  * any previous write to WDOG_CTRL is complete. */
133  while ( wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL )
134  ;
135 
136  wdog->CMD = WDOG_CMD_CLEAR;
137 }
138 
139 
140 /***************************************************************************/
158 void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init)
159 {
160  uint32_t setting;
161 
162  if (init->enable)
163  {
164  setting = WDOG_CTRL_EN;
165  }
166  else
167  {
168  setting = 0;
169  }
170 
171  if (init->debugRun)
172  {
173  setting |= WDOG_CTRL_DEBUGRUN;
174  }
175 
176  if (init->em2Run)
177  {
178  setting |= WDOG_CTRL_EM2RUN;
179  }
180 
181  if (init->em3Run)
182  {
183  setting |= WDOG_CTRL_EM3RUN;
184  }
185 
186  if (init->em4Block)
187  {
188  setting |= WDOG_CTRL_EM4BLOCK;
189  }
190  if (init->swoscBlock)
191  {
192  setting |= WDOG_CTRL_SWOSCBLOCK;
193  }
194  if (init->lock)
195  {
196  setting |= WDOG_CTRL_LOCK;
197  }
198 #if defined( _WDOG_CTRL_WDOGRSTDIS_MASK )
199  if (init->resetDisable)
200  {
201  setting |= WDOG_CTRL_WDOGRSTDIS;
202  }
203 #endif
204  setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT)
205 #if defined( _WDOG_CTRL_WARNSEL_MASK )
206  | ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT)
207 #endif
208 #if defined( _WDOG_CTRL_WINSEL_MASK )
209  | ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT)
210 #endif
211  | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
212 
213  /* Wait for any pending previous write operation to have been completed in */
214  /* low frequency domain */
215  while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
216  ;
217 
218  wdog->CTRL = setting;
219 }
220 
221 
222 /***************************************************************************/
244 {
245  /* Wait for any pending previous write operation to have been completed in */
246  /* low frequency domain */
247  while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
248  ;
249 
250  /* Disable writing to the control register */
252 }
253 
254 
257 #endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */
#define _WDOG_CTRL_LOCK_SHIFT
WDOG_ClkSel_TypeDef clkSel
Definition: em_wdog.h:145
#define _WDOG_CTRL_WARNSEL_MASK
void WDOGn_Lock(WDOG_TypeDef *wdog)
Lock the watchdog configuration.
Definition: em_wdog.c:243
#define WDOG_CTRL_EN
RAM and peripheral bit-field set and clear API.
WDOG_PeriodSel_TypeDef perSel
Definition: em_wdog.h:148
#define _WDOG_CTRL_WINSEL_MASK
#define WDOG_SYNCBUSY_CTRL
void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init)
Initialize watchdog (assuming the watchdog configuration has not been locked).
Definition: em_wdog.c:158
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
Definition: em_bus.h:187
#define WDOG_CTRL_WDOGRSTDIS
#define WDOG_CMD_CLEAR
#define _WDOG_CTRL_WINSEL_SHIFT
WDOG_WinSel_TypeDef winSel
Definition: em_wdog.h:157
void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
Enable/disable the watchdog timer.
Definition: em_wdog.c:75
#define WDOG_CTRL_DEBUGRUN
#define _WDOG_CTRL_EN_SHIFT
#define WDOG_CTRL_LOCK
__IOM uint32_t CTRL
#define WDOG_CTRL_EM3RUN
#define WDOG_CTRL_EM2RUN
WDOG_WarnSel_TypeDef warnSel
Definition: em_wdog.h:152
__IOM uint32_t CMD
#define WDOG_SYNCBUSY_CMD
#define _WDOG_CTRL_WARNSEL_SHIFT
#define WDOG_CTRL_SWOSCBLOCK
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
Watchdog (WDOG) peripheral API.
void WDOGn_Feed(WDOG_TypeDef *wdog)
Feed the watchdog.
Definition: em_wdog.c:115
#define _WDOG_CTRL_CLKSEL_SHIFT
#define WDOG_CTRL_EM4BLOCK
__IM uint32_t SYNCBUSY
#define _WDOG_CTRL_PERSEL_SHIFT