37 #if defined(SMU_COUNT) && (SMU_COUNT > 0)
81 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
122 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
160 #error "No peripherals defined for SMU for this device configuration."
168 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
169 bool privilegedACMP0 : 1;
170 bool privilegedACMP1 : 1;
171 bool privilegedADC0 : 1;
172 bool privilegedReserved0 : 1;
173 bool privilegedReserved1 : 1;
174 bool privilegedCMU : 1;
175 bool privilegedReserved2 : 1;
176 bool privilegedCRYOTIMER : 1;
177 bool privilegedCRYPTO0 : 1;
178 bool privilegedCRYPTO1 : 1;
179 bool privilegedCSEN : 1;
180 bool privilegedVDAC0 : 1;
181 bool privilegedPRS : 1;
182 bool privilegedEMU : 1;
183 bool privilegedFPUEH : 1;
184 bool privilegedReserved3 : 1;
185 bool privilegedGPCRC : 1;
186 bool privilegedGPIO : 1;
187 bool privilegedI2C0 : 1;
188 bool privilegedI2C1 : 1;
189 bool privilegedIDAC0 : 1;
190 bool privilegedMSC : 1;
191 bool privilegedLDMA : 1;
192 bool privilegedLESENSE : 1;
193 bool privilegedLETIMER0 : 1;
194 bool privilegedLEUART0 : 1;
195 bool privilegedReserved4 : 1;
196 bool privilegedPCNT0 : 1;
197 bool privilegedPCNT1 : 1;
198 bool privilegedPCNT2 : 1;
199 bool privilegedReserved5 : 1;
200 bool privilegedReserved6 : 1;
201 bool privilegedReserved7 : 1;
202 bool privilegedRMU : 1;
203 bool privilegedRTCC : 1;
204 bool privilegedSMU : 1;
205 bool privilegedReserved8 : 1;
206 bool privilegedTIMER0 : 1;
207 bool privilegedTIMER1 : 1;
208 bool privilegedTRNG0 : 1;
209 bool privilegedUSART0 : 1;
210 bool privilegedUSART1 : 1;
211 bool privilegedUSART2 : 1;
212 bool privilegedUSART3 : 1;
213 bool privilegedWDOG0 : 1;
214 bool privilegedWDOG1 : 1;
215 bool privilegedWTIMER0 : 1;
216 bool privilegedWTIMER1 : 1;
218 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
219 bool privilegedACMP0 : 1;
220 bool privilegedACMP1 : 1;
221 bool privilegedADC0 : 1;
222 bool privilegedReserved0 : 1;
223 bool privilegedReserved1 : 1;
224 bool privilegedCMU : 1;
225 bool privilegedReserved2 : 1;
226 bool privilegedCRYOTIMER : 1;
227 bool privilegedCRYPTO0 : 1;
228 bool privilegedCRYPTO1 : 1;
229 bool privilegedCSEN : 1;
230 bool privilegedVDAC0 : 1;
231 bool privilegedPRS : 1;
232 bool privilegedEMU : 1;
233 bool privilegedFPUEH : 1;
234 bool privilegedReserved3 : 1;
235 bool privilegedGPCRC : 1;
236 bool privilegedGPIO : 1;
237 bool privilegedI2C0 : 1;
238 bool privilegedI2C1 : 1;
239 bool privilegedIDAC0 : 1;
240 bool privilegedMSC : 1;
241 bool privilegedLDMA : 1;
242 bool privilegedLESENSE : 1;
243 bool privilegedLETIMER0 : 1;
244 bool privilegedLEUART0 : 1;
245 bool privilegedReserved4 : 1;
246 bool privilegedPCNT0 : 1;
247 bool privilegedReserved5 : 1;
248 bool privilegedReserved6 : 1;
249 bool privilegedReserved7 : 1;
250 bool privilegedReserved8 : 1;
251 bool privilegedRMU : 1;
252 bool privilegedRTCC : 1;
253 bool privilegedSMU : 1;
254 bool privilegedReserved9 : 1;
255 bool privilegedTIMER0 : 1;
256 bool privilegedTIMER1 : 1;
257 bool privilegedTRNG0 : 1;
258 bool privilegedUSART0 : 1;
259 bool privilegedUSART1 : 1;
260 bool privilegedUSART2 : 1;
261 bool privilegedWDOG0 : 1;
262 bool privilegedWDOG1 : 1;
263 bool privilegedWTIMER0 : 1;
266 #error "No peripherals defined for SMU for this device configuration"
283 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
285 #define SMU_INIT_DEFAULT { \
317 SMU->PPUPATD0 = init->ppu.
reg[0];
318 SMU->PPUPATD1 = init->ppu.
reg[1];
341 EFM_ASSERT(peripheral < smuPeripheralEnd);
343 if (peripheral < 32) {
443 return SMU->IF & tmp;
465 #endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
#define _SMU_PPUPATD0_LEUART0_SHIFT
#define _SMU_PPUPATD0_MSC_SHIFT
#define _SMU_PPUPATD0_PCNT0_SHIFT
#define _SMU_PPUPATD1_TRNG0_SHIFT
#define _SMU_PPUPATD1_WTIMER1_SHIFT
#define _SMU_PPUPATD1_USART1_SHIFT
#define _SMU_PPUPATD0_ACMP0_SHIFT
#define _SMU_PPUPATD1_WTIMER0_SHIFT
__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, bool privileged)
Change the access settings for a peripheral.
Emlib peripheral API "assert" implementation.
#define _SMU_PPUPATD0_IDAC0_SHIFT
#define _SMU_PPUPATD1_WDOG0_SHIFT
RAM and peripheral bit-field set and clear API.
#define _SMU_PPUPATD1_TIMER0_SHIFT
#define _SMU_PPUPATD0_CMU_SHIFT
#define _SMU_PPUPATD0_LETIMER0_SHIFT
#define _SMU_PPUPATD0_VDAC0_SHIFT
__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
Get the ID of the peripheral that caused an access fault.
#define _SMU_PPUPATD0_FPUEH_SHIFT
#define _SMU_PPUPATD1_USART0_SHIFT
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define _SMU_PPUPATD0_PRS_SHIFT
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT
__STATIC_INLINE void SMU_EnablePPU(bool enable)
Enable or disable the Peripheral Protection Unit of the SMU.
#define _SMU_PPUPATD0_ACMP1_SHIFT
#define _SMU_PPUPATD1_RMU_SHIFT
__STATIC_INLINE void SMU_IntDisable(uint32_t flags)
Disable one or more SMU interrupts.
#define _SMU_PPUPATD1_WDOG1_SHIFT
__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
Initialize the Peripheral Protection Unit of the SMU.
#define _SMU_PPUPATD0_CRYPTO0_SHIFT
#define _SMU_PPUPATD0_GPCRC_SHIFT
__STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
Get enabled and pending SMU interrupt flags. Useful for handling more interrupt sources in the same i...
#define _SMU_PPUPATD0_CSEN_SHIFT
#define _SMU_PPUPATD0_CRYPTO1_SHIFT
#define _SMU_PPUPATD0_I2C1_SHIFT
__STATIC_INLINE uint32_t SMU_IntGet(void)
Get pending SMU interrupts.
#define _SMU_PPUPATD0_PCNT2_SHIFT
#define _SMU_PPUPATD1_RTCC_SHIFT
__STATIC_INLINE void SMU_IntEnable(uint32_t flags)
Enable one or more SMU interrupts.
#define _SMU_PPUPATD0_I2C0_SHIFT
#define _SMU_PPUPATD0_PCNT1_SHIFT
__STATIC_INLINE void SMU_IntSet(uint32_t flags)
Set one or more pending SMU interrupts from SW.
#define _SMU_PPUPATD0_ADC0_SHIFT
SMU_PrivilegedAccess_TypeDef access
#define _SMU_PPUPATD1_USART2_SHIFT
#define _SMU_PPUCTRL_ENABLE_SHIFT
#define _SMU_PPUPATD0_GPIO_SHIFT
#define _SMU_PPUPATD1_TIMER1_SHIFT
__STATIC_INLINE void SMU_IntClear(uint32_t flags)
Clear one or more pending SMU interrupts.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _SMU_PPUPATD1_SMU_SHIFT
#define _SMU_PPUPATD1_USART3_SHIFT
#define _SMU_PPUPATD0_LESENSE_SHIFT
#define _SMU_PPUPATD0_LDMA_SHIFT
#define _SMU_PPUPATD0_EMU_SHIFT