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EFR32 Blue Gecko 12 Software Documentation
efr32bg12-doc-5.1.2
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EFR32 Blue Gecko 12 Software Documentation
efr32bg12-doc-5.1.2
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| #define _SMU_IEN_MASK 0x00000001UL |
Mask for SMU_IEN
Definition at line 93 of file efr32bg12p_smu.h.
| #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IEN
Definition at line 97 of file efr32bg12p_smu.h.
| #define _SMU_IEN_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line 96 of file efr32bg12p_smu.h.
| #define _SMU_IEN_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line 95 of file efr32bg12p_smu.h.
| #define _SMU_IEN_RESETVALUE 0x00000000UL |
Default value for SMU_IEN
Definition at line 92 of file efr32bg12p_smu.h.
| #define _SMU_IF_MASK 0x00000001UL |
Mask for SMU_IF
Definition at line 66 of file efr32bg12p_smu.h.
| #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IF
Definition at line 70 of file efr32bg12p_smu.h.
| #define _SMU_IF_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line 69 of file efr32bg12p_smu.h.
| #define _SMU_IF_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line 68 of file efr32bg12p_smu.h.
| #define _SMU_IF_RESETVALUE 0x00000000UL |
Default value for SMU_IF
Definition at line 65 of file efr32bg12p_smu.h.
| #define _SMU_IFC_MASK 0x00000001UL |
Mask for SMU_IFC
Definition at line 84 of file efr32bg12p_smu.h.
| #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IFC
Definition at line 88 of file efr32bg12p_smu.h.
| #define _SMU_IFC_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line 87 of file efr32bg12p_smu.h.
| #define _SMU_IFC_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line 86 of file efr32bg12p_smu.h.
| #define _SMU_IFC_RESETVALUE 0x00000000UL |
Default value for SMU_IFC
Definition at line 83 of file efr32bg12p_smu.h.
| #define _SMU_IFS_MASK 0x00000001UL |
Mask for SMU_IFS
Definition at line 75 of file efr32bg12p_smu.h.
| #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IFS
Definition at line 79 of file efr32bg12p_smu.h.
| #define _SMU_IFS_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line 78 of file efr32bg12p_smu.h.
| #define _SMU_IFS_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line 77 of file efr32bg12p_smu.h.
| #define _SMU_IFS_RESETVALUE 0x00000000UL |
Default value for SMU_IFS
Definition at line 74 of file efr32bg12p_smu.h.
| #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUCTRL
Definition at line 106 of file efr32bg12p_smu.h.
| #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL |
Bit mask for SMU_ENABLE
Definition at line 105 of file efr32bg12p_smu.h.
| #define _SMU_PPUCTRL_ENABLE_SHIFT 0 |
Shift value for SMU_ENABLE
Definition at line 104 of file efr32bg12p_smu.h.
Referenced by SMU_EnablePPU().
| #define _SMU_PPUCTRL_MASK 0x00000001UL |
Mask for SMU_PPUCTRL
Definition at line 102 of file efr32bg12p_smu.h.
| #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL |
Default value for SMU_PPUCTRL
Definition at line 101 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_MASK 0x0000007FUL |
Mask for SMU_PPUFS
Definition at line 314 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL |
Mode ACMP0 for SMU_PPUFS
Definition at line 318 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL |
Mode ACMP1 for SMU_PPUFS
Definition at line 319 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL |
Mode ADC0 for SMU_PPUFS
Definition at line 320 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL |
Mode CMU for SMU_PPUFS
Definition at line 321 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL |
Mode CRYOTIMER for SMU_PPUFS
Definition at line 322 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL |
Mode CRYPTO0 for SMU_PPUFS
Definition at line 323 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL |
Mode CRYPTO1 for SMU_PPUFS
Definition at line 324 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL |
Mode CSEN for SMU_PPUFS
Definition at line 325 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUFS
Definition at line 317 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL |
Mode EMU for SMU_PPUFS
Definition at line 328 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL |
Mode FPUEH for SMU_PPUFS
Definition at line 329 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL |
Mode GPCRC for SMU_PPUFS
Definition at line 330 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL |
Mode GPIO for SMU_PPUFS
Definition at line 331 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL |
Mode I2C0 for SMU_PPUFS
Definition at line 332 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL |
Mode I2C1 for SMU_PPUFS
Definition at line 333 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL |
Mode IDAC0 for SMU_PPUFS
Definition at line 334 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL |
Mode LDMA for SMU_PPUFS
Definition at line 336 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL |
Mode LESENSE for SMU_PPUFS
Definition at line 337 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL |
Mode LETIMER0 for SMU_PPUFS
Definition at line 338 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL |
Mode LEUART0 for SMU_PPUFS
Definition at line 339 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL |
Bit mask for SMU_PERIPHID
Definition at line 316 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL |
Mode MSC for SMU_PPUFS
Definition at line 335 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL |
Mode PCNT0 for SMU_PPUFS
Definition at line 340 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL |
Mode PCNT1 for SMU_PPUFS
Definition at line 341 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL |
Mode PCNT2 for SMU_PPUFS
Definition at line 342 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL |
Mode PRS for SMU_PPUFS
Definition at line 327 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL |
Mode RMU for SMU_PPUFS
Definition at line 343 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL |
Mode RTCC for SMU_PPUFS
Definition at line 344 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_SHIFT 0 |
Shift value for SMU_PERIPHID
Definition at line 315 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL |
Mode SMU for SMU_PPUFS
Definition at line 345 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL |
Mode TIMER0 for SMU_PPUFS
Definition at line 346 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL |
Mode TIMER1 for SMU_PPUFS
Definition at line 347 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL |
Mode TRNG0 for SMU_PPUFS
Definition at line 348 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL |
Mode USART0 for SMU_PPUFS
Definition at line 349 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL |
Mode USART1 for SMU_PPUFS
Definition at line 350 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL |
Mode USART2 for SMU_PPUFS
Definition at line 351 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL |
Mode USART3 for SMU_PPUFS
Definition at line 352 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL |
Mode VDAC0 for SMU_PPUFS
Definition at line 326 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL |
Mode WDOG0 for SMU_PPUFS
Definition at line 353 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL |
Mode WDOG1 for SMU_PPUFS
Definition at line 354 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL |
Mode WTIMER0 for SMU_PPUFS
Definition at line 355 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL |
Mode WTIMER1 for SMU_PPUFS
Definition at line 356 of file efr32bg12p_smu.h.
| #define _SMU_PPUFS_RESETVALUE 0x00000000UL |
Default value for SMU_PPUFS
Definition at line 313 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 115 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL |
Bit mask for SMU_ACMP0
Definition at line 114 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ACMP0_SHIFT 0 |
Shift value for SMU_ACMP0
Definition at line 113 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 120 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL |
Bit mask for SMU_ACMP1
Definition at line 119 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ACMP1_SHIFT 1 |
Shift value for SMU_ACMP1
Definition at line 118 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 125 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ADC0_MASK 0x4UL |
Bit mask for SMU_ADC0
Definition at line 124 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_ADC0_SHIFT 2 |
Shift value for SMU_ADC0
Definition at line 123 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 130 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CMU_MASK 0x20UL |
Bit mask for SMU_CMU
Definition at line 129 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CMU_SHIFT 5 |
Shift value for SMU_CMU
Definition at line 128 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 135 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL |
Bit mask for SMU_CRYOTIMER
Definition at line 134 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 |
Shift value for SMU_CRYOTIMER
Definition at line 133 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 140 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL |
Bit mask for SMU_CRYPTO0
Definition at line 139 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 |
Shift value for SMU_CRYPTO0
Definition at line 138 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 145 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL |
Bit mask for SMU_CRYPTO1
Definition at line 144 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 |
Shift value for SMU_CRYPTO1
Definition at line 143 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 150 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CSEN_MASK 0x400UL |
Bit mask for SMU_CSEN
Definition at line 149 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_CSEN_SHIFT 10 |
Shift value for SMU_CSEN
Definition at line 148 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 165 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_EMU_MASK 0x2000UL |
Bit mask for SMU_EMU
Definition at line 164 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_EMU_SHIFT 13 |
Shift value for SMU_EMU
Definition at line 163 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 170 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL |
Bit mask for SMU_FPUEH
Definition at line 169 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_FPUEH_SHIFT 14 |
Shift value for SMU_FPUEH
Definition at line 168 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 175 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL |
Bit mask for SMU_GPCRC
Definition at line 174 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_GPCRC_SHIFT 16 |
Shift value for SMU_GPCRC
Definition at line 173 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 180 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_GPIO_MASK 0x20000UL |
Bit mask for SMU_GPIO
Definition at line 179 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_GPIO_SHIFT 17 |
Shift value for SMU_GPIO
Definition at line 178 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 185 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_I2C0_MASK 0x40000UL |
Bit mask for SMU_I2C0
Definition at line 184 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_I2C0_SHIFT 18 |
Shift value for SMU_I2C0
Definition at line 183 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 190 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_I2C1_MASK 0x80000UL |
Bit mask for SMU_I2C1
Definition at line 189 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_I2C1_SHIFT 19 |
Shift value for SMU_I2C1
Definition at line 188 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 195 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL |
Bit mask for SMU_IDAC0
Definition at line 194 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_IDAC0_SHIFT 20 |
Shift value for SMU_IDAC0
Definition at line 193 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 205 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LDMA_MASK 0x400000UL |
Bit mask for SMU_LDMA
Definition at line 204 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LDMA_SHIFT 22 |
Shift value for SMU_LDMA
Definition at line 203 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 210 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL |
Bit mask for SMU_LESENSE
Definition at line 209 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LESENSE_SHIFT 23 |
Shift value for SMU_LESENSE
Definition at line 208 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 215 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL |
Bit mask for SMU_LETIMER0
Definition at line 214 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LETIMER0_SHIFT 24 |
Shift value for SMU_LETIMER0
Definition at line 213 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 220 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL |
Bit mask for SMU_LEUART0
Definition at line 219 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_LEUART0_SHIFT 25 |
Shift value for SMU_LEUART0
Definition at line 218 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL |
Mask for SMU_PPUPATD0
Definition at line 111 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 200 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_MSC_MASK 0x200000UL |
Bit mask for SMU_MSC
Definition at line 199 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_MSC_SHIFT 21 |
Shift value for SMU_MSC
Definition at line 198 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 225 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL |
Bit mask for SMU_PCNT0
Definition at line 224 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT0_SHIFT 27 |
Shift value for SMU_PCNT0
Definition at line 223 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 230 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL |
Bit mask for SMU_PCNT1
Definition at line 229 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT1_SHIFT 28 |
Shift value for SMU_PCNT1
Definition at line 228 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 235 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL |
Bit mask for SMU_PCNT2
Definition at line 234 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PCNT2_SHIFT 29 |
Shift value for SMU_PCNT2
Definition at line 233 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 160 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PRS_MASK 0x1000UL |
Bit mask for SMU_PRS
Definition at line 159 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_PRS_SHIFT 12 |
Shift value for SMU_PRS
Definition at line 158 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL |
Default value for SMU_PPUPATD0
Definition at line 110 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line 155 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_VDAC0_MASK 0x800UL |
Bit mask for SMU_VDAC0
Definition at line 154 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD0_VDAC0_SHIFT 11 |
Shift value for SMU_VDAC0
Definition at line 153 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_MASK 0x0000FFEEUL |
Mask for SMU_PPUPATD1
Definition at line 240 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL |
Default value for SMU_PPUPATD1
Definition at line 239 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 244 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RMU_MASK 0x2UL |
Bit mask for SMU_RMU
Definition at line 243 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RMU_SHIFT 1 |
Shift value for SMU_RMU
Definition at line 242 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 249 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RTCC_MASK 0x4UL |
Bit mask for SMU_RTCC
Definition at line 248 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_RTCC_SHIFT 2 |
Shift value for SMU_RTCC
Definition at line 247 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 254 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_SMU_MASK 0x8UL |
Bit mask for SMU_SMU
Definition at line 253 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_SMU_SHIFT 3 |
Shift value for SMU_SMU
Definition at line 252 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 259 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TIMER0_MASK 0x20UL |
Bit mask for SMU_TIMER0
Definition at line 258 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TIMER0_SHIFT 5 |
Shift value for SMU_TIMER0
Definition at line 257 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 264 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TIMER1_MASK 0x40UL |
Bit mask for SMU_TIMER1
Definition at line 263 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TIMER1_SHIFT 6 |
Shift value for SMU_TIMER1
Definition at line 262 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 269 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TRNG0_MASK 0x80UL |
Bit mask for SMU_TRNG0
Definition at line 268 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_TRNG0_SHIFT 7 |
Shift value for SMU_TRNG0
Definition at line 267 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 274 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART0_MASK 0x100UL |
Bit mask for SMU_USART0
Definition at line 273 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART0_SHIFT 8 |
Shift value for SMU_USART0
Definition at line 272 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 279 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART1_MASK 0x200UL |
Bit mask for SMU_USART1
Definition at line 278 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART1_SHIFT 9 |
Shift value for SMU_USART1
Definition at line 277 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 284 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART2_MASK 0x400UL |
Bit mask for SMU_USART2
Definition at line 283 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART2_SHIFT 10 |
Shift value for SMU_USART2
Definition at line 282 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 289 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART3_MASK 0x800UL |
Bit mask for SMU_USART3
Definition at line 288 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_USART3_SHIFT 11 |
Shift value for SMU_USART3
Definition at line 287 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 294 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL |
Bit mask for SMU_WDOG0
Definition at line 293 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WDOG0_SHIFT 12 |
Shift value for SMU_WDOG0
Definition at line 292 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 299 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL |
Bit mask for SMU_WDOG1
Definition at line 298 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WDOG1_SHIFT 13 |
Shift value for SMU_WDOG1
Definition at line 297 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 304 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL |
Bit mask for SMU_WTIMER0
Definition at line 303 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WTIMER0_SHIFT 14 |
Shift value for SMU_WTIMER0
Definition at line 302 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line 309 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL |
Bit mask for SMU_WTIMER1
Definition at line 308 of file efr32bg12p_smu.h.
| #define _SMU_PPUPATD1_WTIMER1_SHIFT 15 |
Shift value for SMU_WTIMER1
Definition at line 307 of file efr32bg12p_smu.h.
| #define SMU_IEN_PPUPRIV (0x1UL << 0) |
PPUPRIV Interrupt Enable
Definition at line 94 of file efr32bg12p_smu.h.
| #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IEN
Definition at line 98 of file efr32bg12p_smu.h.
| #define SMU_IF_PPUPRIV (0x1UL << 0) |
PPU Privilege Interrupt Flag
Definition at line 67 of file efr32bg12p_smu.h.
| #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IF
Definition at line 71 of file efr32bg12p_smu.h.
| #define SMU_IFC_PPUPRIV (0x1UL << 0) |
Clear PPUPRIV Interrupt Flag
Definition at line 85 of file efr32bg12p_smu.h.
| #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IFC
Definition at line 89 of file efr32bg12p_smu.h.
| #define SMU_IFS_PPUPRIV (0x1UL << 0) |
Set PPUPRIV Interrupt Flag
Definition at line 76 of file efr32bg12p_smu.h.
| #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IFS
Definition at line 80 of file efr32bg12p_smu.h.
| #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUCTRL
Definition at line 107 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) |
Shifted mode ACMP0 for SMU_PPUFS
Definition at line 358 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) |
Shifted mode ACMP1 for SMU_PPUFS
Definition at line 359 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) |
Shifted mode ADC0 for SMU_PPUFS
Definition at line 360 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) |
Shifted mode CMU for SMU_PPUFS
Definition at line 361 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) |
Shifted mode CRYOTIMER for SMU_PPUFS
Definition at line 362 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) |
Shifted mode CRYPTO0 for SMU_PPUFS
Definition at line 363 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) |
Shifted mode CRYPTO1 for SMU_PPUFS
Definition at line 364 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) |
Shifted mode CSEN for SMU_PPUFS
Definition at line 365 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUFS
Definition at line 357 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) |
Shifted mode EMU for SMU_PPUFS
Definition at line 368 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) |
Shifted mode FPUEH for SMU_PPUFS
Definition at line 369 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) |
Shifted mode GPCRC for SMU_PPUFS
Definition at line 370 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) |
Shifted mode GPIO for SMU_PPUFS
Definition at line 371 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) |
Shifted mode I2C0 for SMU_PPUFS
Definition at line 372 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) |
Shifted mode I2C1 for SMU_PPUFS
Definition at line 373 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) |
Shifted mode IDAC0 for SMU_PPUFS
Definition at line 374 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) |
Shifted mode LDMA for SMU_PPUFS
Definition at line 376 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) |
Shifted mode LESENSE for SMU_PPUFS
Definition at line 377 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) |
Shifted mode LETIMER0 for SMU_PPUFS
Definition at line 378 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) |
Shifted mode LEUART0 for SMU_PPUFS
Definition at line 379 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) |
Shifted mode MSC for SMU_PPUFS
Definition at line 375 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) |
Shifted mode PCNT0 for SMU_PPUFS
Definition at line 380 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) |
Shifted mode PCNT1 for SMU_PPUFS
Definition at line 381 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) |
Shifted mode PCNT2 for SMU_PPUFS
Definition at line 382 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) |
Shifted mode PRS for SMU_PPUFS
Definition at line 367 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) |
Shifted mode RMU for SMU_PPUFS
Definition at line 383 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) |
Shifted mode RTCC for SMU_PPUFS
Definition at line 384 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) |
Shifted mode SMU for SMU_PPUFS
Definition at line 385 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) |
Shifted mode TIMER0 for SMU_PPUFS
Definition at line 386 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) |
Shifted mode TIMER1 for SMU_PPUFS
Definition at line 387 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) |
Shifted mode TRNG0 for SMU_PPUFS
Definition at line 388 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) |
Shifted mode USART0 for SMU_PPUFS
Definition at line 389 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) |
Shifted mode USART1 for SMU_PPUFS
Definition at line 390 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) |
Shifted mode USART2 for SMU_PPUFS
Definition at line 391 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) |
Shifted mode USART3 for SMU_PPUFS
Definition at line 392 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) |
Shifted mode VDAC0 for SMU_PPUFS
Definition at line 366 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) |
Shifted mode WDOG0 for SMU_PPUFS
Definition at line 393 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) |
Shifted mode WDOG1 for SMU_PPUFS
Definition at line 394 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) |
Shifted mode WTIMER0 for SMU_PPUFS
Definition at line 395 of file efr32bg12p_smu.h.
| #define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) |
Shifted mode WTIMER1 for SMU_PPUFS
Definition at line 396 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_ACMP0 (0x1UL << 0) |
Analog Comparator 0 access control bit
Definition at line 112 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 116 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_ACMP1 (0x1UL << 1) |
Analog Comparator 1 access control bit
Definition at line 117 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 121 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_ADC0 (0x1UL << 2) |
Analog to Digital Converter 0 access control bit
Definition at line 122 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 126 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CMU (0x1UL << 5) |
Clock Management Unit access control bit
Definition at line 127 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 131 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) |
CryoTimer access control bit
Definition at line 132 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 136 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) |
Advanced Encryption Standard Accelerator 0 access control bit
Definition at line 137 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 141 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) |
Advanced Encryption Standard Accelerator 1 access control bit
Definition at line 142 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 146 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CSEN (0x1UL << 10) |
Capacitive touch sense module access control bit
Definition at line 147 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 151 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_EMU (0x1UL << 13) |
Energy Management Unit access control bit
Definition at line 162 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 166 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_FPUEH (0x1UL << 14) |
FPU Exception Handler access control bit
Definition at line 167 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 171 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_GPCRC (0x1UL << 16) |
General Purpose CRC access control bit
Definition at line 172 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 176 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_GPIO (0x1UL << 17) |
General purpose Input/Output access control bit
Definition at line 177 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 181 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_I2C0 (0x1UL << 18) |
I2C 0 access control bit
Definition at line 182 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 186 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_I2C1 (0x1UL << 19) |
I2C 1 access control bit
Definition at line 187 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 191 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_IDAC0 (0x1UL << 20) |
Current Digital to Analog Converter 0 access control bit
Definition at line 192 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 196 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LDMA (0x1UL << 22) |
Linked Direct Memory Access Controller access control bit
Definition at line 202 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 206 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LESENSE (0x1UL << 23) |
Low Energy Sensor Interface access control bit
Definition at line 207 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 211 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) |
Low Energy Timer 0 access control bit
Definition at line 212 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 216 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LEUART0 (0x1UL << 25) |
Low Energy UART 0 access control bit
Definition at line 217 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 221 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_MSC (0x1UL << 21) |
Memory System Controller access control bit
Definition at line 197 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 201 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PCNT0 (0x1UL << 27) |
Pulse Counter 0 access control bit
Definition at line 222 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 226 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PCNT1 (0x1UL << 28) |
Pulse Counter 1 access control bit
Definition at line 227 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 231 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PCNT2 (0x1UL << 29) |
Pulse Counter 2 access control bit
Definition at line 232 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 236 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PRS (0x1UL << 12) |
Peripheral Reflex System access control bit
Definition at line 157 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 161 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_VDAC0 (0x1UL << 11) |
Digital to Analog Converter 0 access control bit
Definition at line 152 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line 156 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_RMU (0x1UL << 1) |
Reset Management Unit access control bit
Definition at line 241 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 245 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_RTCC (0x1UL << 2) |
Real-Time Counter and Calendar access control bit
Definition at line 246 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 250 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_SMU (0x1UL << 3) |
Security Management Unit access control bit
Definition at line 251 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 255 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_TIMER0 (0x1UL << 5) |
Timer 0 access control bit
Definition at line 256 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 260 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_TIMER1 (0x1UL << 6) |
Timer 1 access control bit
Definition at line 261 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 265 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_TRNG0 (0x1UL << 7) |
True Random Number Generator 0 access control bit
Definition at line 266 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 270 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART0 (0x1UL << 8) |
Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit
Definition at line 271 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 275 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART1 (0x1UL << 9) |
Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit
Definition at line 276 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 280 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART2 (0x1UL << 10) |
Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit
Definition at line 281 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 285 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART3 (0x1UL << 11) |
Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit
Definition at line 286 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 290 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WDOG0 (0x1UL << 12) |
Watchdog 0 access control bit
Definition at line 291 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 295 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WDOG1 (0x1UL << 13) |
Watchdog 1 access control bit
Definition at line 296 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 300 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) |
Wide Timer 0 access control bit
Definition at line 301 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 305 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) |
Wide Timer 1 access control bit
Definition at line 306 of file efr32bg12p_smu.h.
| #define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line 310 of file efr32bg12p_smu.h.
1.8.10 
