34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
66 uint32_t ctrl =
EBI->CTRL;
68 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
98 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
198 ctrl |= ebiInit->
mode;
204 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
240 switch (ebiInit->
mode)
247 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
255 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
332 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
437 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
483 EFM_ASSERT(setupCycles < 4);
484 EFM_ASSERT(strobeCycles < 16);
485 EFM_ASSERT(holdCycles < 4);
493 EBI->RDTIMING = (
EBI->RDTIMING
516 uint32_t writeTiming;
519 EFM_ASSERT(setupCycles < 4);
520 EFM_ASSERT(strobeCycles < 16);
521 EFM_ASSERT(holdCycles < 4);
528 EBI->WRTIMING = (
EBI->WRTIMING
549 uint32_t addressLatchTiming;
552 EFM_ASSERT(setupCycles < 4);
553 EFM_ASSERT(holdCycles < 4);
559 EBI->ADDRTIMING = (
EBI->ADDRTIMING
562 | addressLatchTiming;
565 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
604 ctrl = (uint32_t)ebiTFTInit->
bank
605 | (uint32_t)ebiTFTInit->
width
606 | (uint32_t)ebiTFTInit->
colSrc
609 | (uint32_t)(ebiTFTInit->
shiftDClk ==
true
635 EFM_ASSERT((horizontal-1) < 1024);
636 EFM_ASSERT((vertical-1) < 1024);
655 EFM_ASSERT(front < 256);
656 EFM_ASSERT(back < 256);
657 EFM_ASSERT((pulseWidth-1) < 128);
678 EFM_ASSERT(front < 256);
679 EFM_ASSERT(back < 256);
680 EFM_ASSERT((pulseWidth-1) < 128);
706 EFM_ASSERT(dclkPeriod < 2048);
707 EFM_ASSERT(start < 2048);
708 EFM_ASSERT(setup < 4);
709 EFM_ASSERT(hold < 4);
718 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
792 EFM_ASSERT(setupCycles < 4);
793 EFM_ASSERT(strobeCycles < 64);
794 EFM_ASSERT(holdCycles < 4);
803 EBI->RDTIMING = (
EBI->RDTIMING
811 EBI->RDTIMING1 = (
EBI->RDTIMING1
819 EBI->RDTIMING2 = (
EBI->RDTIMING2
827 EBI->RDTIMING3 = (
EBI->RDTIMING3
896 uint32_t writeTiming;
902 EFM_ASSERT(setupCycles < 4);
903 EFM_ASSERT(strobeCycles < 64);
904 EFM_ASSERT(holdCycles < 4);
913 EBI->WRTIMING = (
EBI->WRTIMING
921 EBI->WRTIMING1 = (
EBI->WRTIMING1
929 EBI->WRTIMING2 = (
EBI->WRTIMING2
937 EBI->WRTIMING3 = (
EBI->WRTIMING3
996 uint32_t addressLatchTiming;
1002 EFM_ASSERT(setupCycles < 4);
1003 EFM_ASSERT(holdCycles < 4);
1011 EBI->ADDRTIMING = (
EBI->ADDRTIMING
1014 | addressLatchTiming;
1018 EBI->ADDRTIMING1 = (
EBI->ADDRTIMING1
1021 | addressLatchTiming;
1025 EBI->ADDRTIMING2 = (
EBI->ADDRTIMING2
1028 | addressLatchTiming;
1032 EBI->ADDRTIMING3 = (
EBI->ADDRTIMING3
1035 | addressLatchTiming;
1056 uint32_t bankSet = 0;
1057 volatile uint32_t *polRegister = 0;
1064 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1067 polRegister = &
EBI->POLARITY;
1072 polRegister = &
EBI->POLARITY1;
1077 polRegister = &
EBI->POLARITY2;
1082 polRegister = &
EBI->POLARITY3;
1086 polRegister = &
EBI->POLARITY;
1108 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1132 banks = banks & ~bankSet;
#define _EBI_POLARITY_WEPOL_SHIFT
#define _EBI_TFTHPORCH_HFPORCH_SHIFT
#define _EBI_TFTHPORCH_HBPORCH_SHIFT
#define _EBI_ADDRTIMING3_ADDRSETUP_MASK
void EBI_BankWriteTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles)
Configure timing values of write bus accesses.
#define _EBI_WRTIMING_WRHOLD_MASK
void EBI_AltMapEnable(bool enable)
Configure Alternate Address Map support Enables or disables 256MB address range for all banks...
#define _EBI_WRTIMING_WRSTRB_MASK
#define _EBI_WRTIMING_HALFWE_SHIFT
#define _EBI_CTRL_MODE_MASK
#define _EBI_WRTIMING_WRSETUP_MASK
#define _EBI_WRTIMING_WBUFDIS_SHIFT
#define _EBI_CTRL_ARDY1EN_MASK
#define _EBI_ADDRTIMING2_ADDRHOLD_MASK
#define _EBI_ROUTE_ALEPEN_SHIFT
#define _EBI_RDTIMING2_RDHOLD_MASK
#define _EBI_POLARITY_BLPOL_SHIFT
EBI_Polarity_TypeDef dclkPolarity
#define _EBI_RDTIMING2_RDSTRB_MASK
#define _EBI_CTRL_NOIDLE1_MASK
#define _EBI_CTRL_MODE3_SHIFT
Emlib peripheral API "assert" implementation.
#define _EBI_ROUTE_BLPEN_SHIFT
#define _EBI_RDTIMING_RDHOLD_SHIFT
void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
Configure timing values of write bus accesses.
#define _EBI_WRTIMING1_WRSTRB_MASK
EBI_TFTMaskBlend_TypeDef maskBlend
#define _EBI_TFTPOLARITY_CSPOL_SHIFT
#define _EBI_ADDRTIMING3_ADDRHOLD_MASK
#define _EBI_CTRL_ARDYTO2DIS_MASK
RAM and peripheral bit-field set and clear API.
uint32_t EBI_BankAddress(uint32_t bank)
Return base address of EBI bank.
EBI_Polarity_TypeDef csPolarity
#define _EBI_CTRL_BANK2EN_MASK
EBI_Polarity_TypeDef vsyncPolarity
#define _EBI_CTRL_NOIDLE3_MASK
#define _EBI_CTRL_NOIDLE2_MASK
#define _EBI_TFTTIMING_TFTSETUP_SHIFT
#define _EBI_CTRL_ARDYTODIS_MASK
#define _EBI_CTRL_BANK0EN_MASK
#define _EBI_ADDRTIMING2_ADDRSETUP_MASK
void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
Configure and initialize Horizontal Porch Settings.
__STATIC_INLINE void EBI_TFTFrameBaseSet(uint32_t address)
Configure frame buffer pointer.
EBI_Polarity_TypeDef csPolarity
#define _EBI_RDTIMING1_RDSTRB_MASK
#define _EBI_ROUTE_LOCATION_MASK
EBI_TFTFrameBufTrigger_TypeDef fbTrigger
void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
Configure EBI pin polarity.
#define _EBI_CTRL_BANK0EN_SHIFT
EBI_TFTDDMode_TypeDef driveMode
#define _EBI_TFTPOLARITY_DCLKPOL_SHIFT
#define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT
#define _EBI_TFTSIZE_VSZ_SHIFT
EBI_Location_TypeDef location
#define _EBI_CTRL_ALTMAP_SHIFT
#define _EBI_CTRL_MODE2_SHIFT
#define _EBI_WRTIMING1_WRHOLD_MASK
#define _EBI_CTRL_ARDYTO3DIS_SHIFT
#define _EBI_WRTIMING2_WRSTRB_MASK
EBI_Polarity_TypeDef hsyncPolarity
#define _EBI_TFTTIMING_DCLKPERIOD_SHIFT
#define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT
#define _EBI_CTRL_MODE_SHIFT
#define _EBI_CTRL_ARDY1EN_SHIFT
#define _EBI_ADDRTIMING1_ADDRSETUP_MASK
#define _EBI_POLARITY_REPOL_SHIFT
#define _EBI_ROUTE_APEN_MASK
#define _EBI_RDTIMING1_RDHOLD_MASK
#define _EBI_ROUTE_EBIPEN_SHIFT
#define _EBI_CTRL_NOIDLE_MASK
#define _EBI_CTRL_ARDYEN_SHIFT
#define _EBI_CTRL_ARDYTO1DIS_MASK
#define _EBI_CTRL_MODE2_MASK
void EBI_AddressTimingSet(int setupCycles, int holdCycles)
Configure timing values of address latch bus accesses.
void EBI_BankEnable(uint32_t banks, bool enable)
Enable or disable EBI Bank.
#define _EBI_CTRL_NOIDLE3_SHIFT
EBI_TFTColorSrc_TypeDef colSrc
#define _EBI_ROUTE_CS0PEN_SHIFT
#define _EBI_CTRL_ARDY3EN_MASK
External Bus Iterface (EBI) peripheral API.
#define _EBI_ROUTE_CS1PEN_SHIFT
#define _EBI_CTRL_ARDY3EN_SHIFT
#define _EBI_CTRL_BANK2EN_SHIFT
#define _EBI_WRTIMING3_WRSTRB_MASK
#define _EBI_TFTPOLARITY_DATAENPOL_SHIFT
#define _EBI_ROUTE_CS3PEN_SHIFT
EBI_TFTInterleave_TypeDef interleave
#define _EBI_RDTIMING_RDSETUP_SHIFT
EBI_TFTWidth_TypeDef width
#define _EBI_RDTIMING_PREFETCH_SHIFT
void EBI_BankByteLaneEnable(uint32_t bank, bool enable)
Configure Byte Lane Enable for select banks timing support.
void EBI_ChipSelectEnable(uint32_t banks, bool enable)
Enable or disable EBI Chip Select.
#define _EBI_RDTIMING2_RDSETUP_MASK
#define _EBI_RDTIMING_RDSTRB_SHIFT
void EBI_BankReadTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles)
Configure timing values of read bus accesses.
#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT
#define _EBI_CTRL_ARDY2EN_SHIFT
#define _EBI_WRTIMING2_WRSETUP_MASK
#define _EBI_WRTIMING3_WRSETUP_MASK
#define _EBI_CTRL_ARDYTO3DIS_MASK
#define _EBI_TFTVPORCH_VBPORCH_SHIFT
void EBI_Init(const EBI_Init_TypeDef *ebiInit)
Configure and enable External Bus Interface.
#define _EBI_CTRL_MODE1_SHIFT
#define _EBI_CTRL_BL_SHIFT
#define _EBI_CTRL_BL2_SHIFT
#define _EBI_RDTIMING_RDSETUP_MASK
void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
Configure timing values of read bus accesses.
#define _EBI_ADDRTIMING1_ADDRHOLD_MASK
void EBI_BankWriteTimingConfig(uint32_t bank, bool writeBufDisable, bool halfWE)
Configure write operation parameters for selected bank.
#define _EBI_CTRL_NOIDLE1_SHIFT
#define _EBI_ADDRTIMING_ADDRHOLD_MASK
#define _EBI_CTRL_ARDYEN_MASK
EBI_Polarity_TypeDef blPolarity
#define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT
#define _EBI_CTRL_BANK1EN_SHIFT
#define _EBI_CTRL_ARDYTO1DIS_SHIFT
#define _EBI_TFTVPORCH_VFPORCH_SHIFT
#define _EBI_POLARITY_ARDYPOL_SHIFT
#define _EBI_CTRL_BANK3EN_MASK
#define _EBI_CTRL_NOIDLE_SHIFT
#define _EBI_ADDRTIMING_HALFALE_SHIFT
#define _EBI_ROUTE_RESETVALUE
#define _EBI_CTRL_BL1_MASK
#define _EBI_WRTIMING1_WRSETUP_MASK
EBI_Polarity_TypeDef rePolarity
#define _EBI_POLARITY_ALEPOL_SHIFT
#define _EBI_CTRL_BL1_SHIFT
#define _EBI_RDTIMING1_RDSETUP_MASK
#define _EBI_TFTSIZE_HSZ_SHIFT
#define _EBI_TFTHPORCH_HSYNC_SHIFT
#define _EBI_CTRL_MODE1_MASK
#define _EBI_RDTIMING_RDHOLD_MASK
#define _EBI_CTRL_BL_MASK
#define _EBI_ROUTE_ALB_MASK
#define _EBI_CTRL_BANK3EN_SHIFT
EBI_Polarity_TypeDef alePolarity
#define _EBI_WRTIMING3_WRHOLD_MASK
#define _EBI_ROUTE_CS2PEN_SHIFT
#define _EBI_TFTTIMING_TFTHOLD_SHIFT
#define _EBI_RDTIMING3_RDSTRB_MASK
#define _EBI_CTRL_RESETVALUE
#define _EBI_CTRL_NOIDLE2_SHIFT
#define _EBI_WRTIMING_WRSETUP_SHIFT
void EBI_BankPolaritySet(uint32_t bank, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
Configure EBI pin polarity for selected bank(s) for devices with individual timing support...
#define _EBI_CTRL_MODE3_MASK
#define _EBI_CTRL_BL3_SHIFT
void EBI_Disable(void)
Disable External Bus Interface.
#define _EBI_POLARITY_CSPOL_SHIFT
void EBI_BankAddressTimingSet(uint32_t bank, int setupCycles, int holdCycles)
Configure timing values of address latch bus accesses.
#define _EBI_CTRL_BANK1EN_MASK
#define _EBI_CTRL_ARDYTODIS_SHIFT
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
EBI_Polarity_TypeDef dataenPolarity
#define _EBI_RDTIMING_RDSTRB_MASK
#define _EBI_RDTIMING_PAGEMODE_SHIFT
#define _EBI_ADDRTIMING_ADDRSETUP_MASK
#define _EBI_CTRL_ARDYTO2DIS_SHIFT
void EBI_BankReadTimingConfig(uint32_t bank, bool pageMode, bool prefetch, bool halfRE)
Configure read operation parameters for selected bank.
#define _EBI_CTRL_BL3_MASK
#define _EBI_RDTIMING3_RDHOLD_MASK
void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
Configure and initialize TFT size settings.
#define _EBI_CTRL_ARDY2EN_MASK
void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
Configure TFT Direct Drive Timing Settings.
#define _EBI_WRTIMING_WRHOLD_SHIFT
void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
Configure Vertical Porch Settings.
#define _EBI_TFTTIMING_TFTSTART_SHIFT
#define _EBI_TFTVPORCH_VSYNC_SHIFT
#define _EBI_ADDRTIMING_ADDRSETUP_SHIFT
EBI_Polarity_TypeDef wePolarity
void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
Configure and initialize TFT Direct Drive.
EBI_Polarity_TypeDef ardyPolarity
#define _EBI_RDTIMING_HALFRE_SHIFT
#define _EBI_WRTIMING_WRSTRB_SHIFT
#define _EBI_CTRL_BL2_MASK
#define _EBI_RDTIMING3_RDSETUP_MASK
void EBI_BankAddressTimingConfig(uint32_t bank, bool halfALE)
Configure address operation parameters for selected bank.
#define _EBI_WRTIMING2_WRHOLD_MASK