EFM32 Giant Gecko Software Documentation  efm32gg-doc-5.1.2
tftspi.c
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1 /**************************************************************************/
18 #include "em_device.h"
19 #include "em_usart.h"
20 #include "em_gpio.h"
21 #include "em_cmu.h"
22 #include "tftspi.h"
23 
26 { usartEnable, /* Enable RX/TX when init completed. */
27  48000000, /* Use 48MHz reference clock */
28  1000000, /* 7 Mbits/s. */
29  usartDatabits9, /* 9 databits. */
30  true, /* Master mode. */
31  true, /* Send most significant bit first. */
32  usartClockMode3, /* Clock idle low, sample on rising edge. */
33  false,
35  false };
36 
37 
38 /**************************************************************************/
45 void SPI_TFT_Init(void)
46 {
47  /* Enabling clock to USART */
51 
52  /* IO configuration (USART 1, Location #1) */
53  GPIO_PinModeSet(gpioPortD, 0, gpioModePushPull, 0); /* TX - MOSI */
54  GPIO_PinModeSet(gpioPortD, 1, gpioModeInput, 0); /* RX - MISO */
55  GPIO_PinModeSet(gpioPortD, 2, gpioModePushPull, 0); /* CLK */
56  GPIO_PinModeSet(gpioPortD, 3, gpioModePushPull, 1); /* CS */
57 
58  /* Ensure out of reset configuration */
60 
61  /* Initialize USART1, in SPI master mode. */
62  USART_InitSync(USART1, &inittft);
63 
64  USART1->ROUTE =
69 }
70 
71 
72 /**************************************************************************/
82 void SPI_TFT_WriteRegister(uint8_t reg, uint16_t data)
83 {
84  /* Enable chip select */
85  GPIO_PinOutClear(gpioPortD, 3);
86 
87  /* Select register first */
88  USART1->CTRL = USART1->CTRL & ~USART_CTRL_BIT8DV;
89 
90  USART_Tx(USART1, reg & 0xFF);
92 
93  /* Write data */
94  USART1->CTRL = USART1->CTRL | USART_CTRL_BIT8DV;
95  USART_Tx(USART1, (data & 0xff00) >> 8);
97  USART_Tx(USART1, (data & 0x00ff));
99 
100  /* Clear chip select */
101  GPIO_PinOutSet(gpioPortD, 3);
102 }
Clock management unit (CMU) API.
#define USART1
void SPI_TFT_WriteRegister(uint8_t reg, uint16_t data)
SPI_TFT_Write Write registers/data to SSD2119 controller.
Definition: tftspi.c:82
void USART_Tx(USART_TypeDef *usart, uint8_t data)
Transmit one 4-9 bit frame.
Definition: em_usart.c:1084
EFM32GG_DK3750, SPI controller API for SSD2119 display interface when using Generic/Direct Drive mode...
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
Init USART for synchronous mode.
Definition: em_usart.c:640
uint8_t USART_Rx(USART_TypeDef *usart)
Receive one 4-8 bit frame, (or part of 10-16 bit frame).
Definition: em_usart.c:923
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
Universal synchronous/asynchronous receiver/transmitter (USART/UART) peripheral API.
#define USART_ROUTE_TXPEN
void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out)
Set the mode for a GPIO pin.
Definition: em_gpio.c:269
General Purpose IO (GPIO) peripheral API.
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out register to 1.
Definition: em_gpio.h:856
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
Definition: em_cmu.c:1453
void USART_Reset(USART_TypeDef *usart)
Reset USART/UART to same state as after a HW reset.
Definition: em_usart.c:856
void SPI_TFT_Init(void)
SPI_TFT_Init Initialize SPI interface to TFT-LCD SSD2119 controller.
Definition: tftspi.c:45
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out port register to 0.
Definition: em_gpio.h:811
#define USART_ROUTE_RXPEN
#define USART_ROUTE_LOCATION_LOC1
static const USART_InitSync_TypeDef inittft
Definition: tftspi.c:25
#define USART_CTRL_BIT8DV
#define USART_ROUTE_CLKPEN