EFM32 Giant Gecko Software Documentation  efm32gg-doc-5.1.2
em_gpio.c
Go to the documentation of this file.
1 /***************************************************************************/
35 #include "em_gpio.h"
36 
37 #if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
38 
39 /***************************************************************************/
44 /***************************************************************************/
55 /*******************************************************************************
56  ******************************* DEFINES ***********************************
57  ******************************************************************************/
58 
62 #define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3)
63 #define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \
64  ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
65  | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
66 
69 /*******************************************************************************
70  ************************** GLOBAL FUNCTIONS *******************************
71  ******************************************************************************/
72 
73 /***************************************************************************/
83 void GPIO_DbgLocationSet(unsigned int location)
84 {
85 #if defined ( _GPIO_ROUTE_SWLOCATION_MASK )
86  EFM_ASSERT(location < AFCHANLOC_MAX);
87 
88  GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) |
89  (location << _GPIO_ROUTE_SWLOCATION_SHIFT);
90 #else
91  (void)location;
92 #endif
93 }
94 
95 #if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)
96 /***************************************************************************/
107 {
108  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode));
109 
110  GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK))
111  | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT);
112 }
113 #endif
114 
115 #if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK)
116 /***************************************************************************/
126 void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
127  GPIO_DriveStrength_TypeDef strength)
128 {
129  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGHT_VALID(strength));
130  BUS_RegMaskedWrite(&GPIO->P[port].CTRL,
131  _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK,
132  strength);
133 }
134 #endif
135 
136 /***************************************************************************/
182  unsigned int pin,
183  unsigned int intNo,
184  bool risingEdge,
185  bool fallingEdge,
186  bool enable)
187 {
188  uint32_t tmp = 0;
189 #if !defined(_GPIO_EXTIPINSELL_MASK)
190  (void)pin;
191 #endif
192 
193  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
194 #if defined(_GPIO_EXTIPINSELL_MASK)
195  EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin));
196 #endif
197 
198  /* There are two registers controlling the interrupt configuration:
199  * The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
200  * pins 8-15. */
201  if (intNo < 8)
202  {
203  BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
205  << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo),
206  port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo));
207  }
208  else
209  {
210  tmp = intNo - 8;
211  BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
214  port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp));
215  }
216 
217 #if defined(_GPIO_EXTIPINSELL_MASK)
218  /* There are two registers controlling the interrupt/pin number mapping:
219  * The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls
220  * interrupt 8-15. */
221  if (intNo < 8)
222  {
223  BUS_RegMaskedWrite(&GPIO->EXTIPINSELL,
224  _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK
225  << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo),
226  ((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)
227  << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo));
228  }
229  else
230  {
231  BUS_RegMaskedWrite(&GPIO->EXTIPINSELH,
232  _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK
233  << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp),
234  ((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK)
236  }
237 #endif
238 
239  /* Enable/disable rising edge */
240  BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge);
241 
242  /* Enable/disable falling edge */
243  BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge);
244 
245  /* Clear any pending interrupt */
246  GPIO->IFC = 1 << intNo;
247 
248  /* Finally enable/disable interrupt */
249  BUS_RegBitWrite(&(GPIO->IEN), intNo, enable);
250 }
251 
252 /***************************************************************************/
270  unsigned int pin,
271  GPIO_Mode_TypeDef mode,
272  unsigned int out)
273 {
274  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
275 
276  /* If disabling pin, do not modify DOUT in order to reduce chance for */
277  /* glitch/spike (may not be sufficient precaution in all use cases) */
278  if (mode != gpioModeDisabled)
279  {
280  if (out)
281  {
282  GPIO_PinOutSet(port, pin);
283  }
284  else
285  {
286  GPIO_PinOutClear(port, pin);
287  }
288  }
289 
290  /* There are two registers controlling the pins for each port. The MODEL
291  * register controls pins 0-7 and MODEH controls pins 8-15. */
292  if (pin < 8)
293  {
294  GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4)))
295  | (mode << (pin * 4));
296  }
297  else
298  {
299  GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4)))
300  | (mode << ((pin - 8) * 4));
301  }
302 
303  if (mode == gpioModeDisabled)
304  {
305  if (out)
306  {
307  GPIO_PinOutSet(port, pin);
308  }
309  else
310  {
311  GPIO_PinOutClear(port, pin);
312  }
313  }
314 }
315 
316 /***************************************************************************/
330  unsigned int pin)
331 {
332  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
333 
334  if (pin < 8)
335  {
336  return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF);
337  }
338  else
339  {
340  return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF);
341  }
342 }
343 
344 #if defined( _GPIO_EM4WUEN_MASK )
345 /**************************************************************************/
361 void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
362 {
363  EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
364 
365 #if defined( _GPIO_EM4WUPOL_MASK )
366  EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
367  GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */
368  GPIO->EM4WUPOL |= pinmask & polaritymask;
369 #elif defined( _GPIO_EXTILEVEL_MASK )
370  EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);
371  GPIO->EXTILEVEL &= ~pinmask;
372  GPIO->EXTILEVEL |= pinmask & polaritymask;
373 #endif
374  GPIO->EM4WUEN |= pinmask; /* Enable wakeup */
375 
376  GPIO_EM4SetPinRetention(true); /* Enable pin retention */
377 
378 #if defined( _GPIO_CMD_EM4WUCLR_MASK )
379  GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */
380 #elif defined( _GPIO_IFC_EM4WU_MASK )
381  GPIO_IntClear(pinmask);
382 #endif
383 }
384 #endif
385 
389 #endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */
#define _GPIO_P_CTRL_DRIVEMODE_MASK
Definition: efm32gg_gpio.h:74
#define GPIO_CMD_EM4WUCLR
#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK
Definition: efm32gg_gpio.h:722
GPIO_Port_TypeDef
Definition: em_gpio.h:345
#define _GPIO_P_CTRL_DRIVEMODE_SHIFT
Definition: efm32gg_gpio.h:73
__STATIC_INLINE void GPIO_IntClear(uint32_t flags)
Clear one or more pending GPIO interrupts.
Definition: em_gpio.h:674
GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, unsigned int pin)
Get the mode for a GPIO pin.
Definition: em_gpio.c:329
void GPIO_DbgLocationSet(unsigned int location)
Sets the pin location of the debug pins (Serial Wire interface).
Definition: em_gpio.c:83
#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT
Definition: efm32gg_gpio.h:737
void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
Enable GPIO pin wake-up from EM4. When the function exits, EM4 mode can be safely entered...
Definition: em_gpio.c:361
#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK
Definition: efm32gg_gpio.h:854
#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT
Definition: efm32gg_gpio.h:869
void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, unsigned int pin, unsigned int intNo, bool risingEdge, bool fallingEdge, bool enable)
Configure GPIO external pin interrupt.
Definition: em_gpio.c:181
GPIO_Mode_TypeDef
Definition: em_gpio.h:421
void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode)
Sets the drive mode for a GPIO port.
Definition: em_gpio.c:106
void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out)
Set the mode for a GPIO pin.
Definition: em_gpio.c:269
General Purpose IO (GPIO) peripheral API.
#define _GPIO_EM4WUEN_MASK
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out register to 1.
Definition: em_gpio.h:856
#define GPIO
#define _GPIO_EM4WUPOL_MASK
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
Definition: em_bus.h:288
#define _GPIO_ROUTE_SWLOCATION_MASK
GPIO_DriveMode_TypeDef
Definition: em_gpio.h:384
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out port register to 0.
Definition: em_gpio.h:811
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
#define _GPIO_ROUTE_SWLOCATION_SHIFT
__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable)
Enable GPIO pin retention of output enable, output value, pull enable and pull direction in EM4...
Definition: em_gpio.h:616