EFM32 Giant Gecko Software Documentation  efm32gg-doc-5.1.2
bsp_dk_3201.c
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1 /***************************************************************************/
18 #include "em_device.h"
19 #include "em_cmu.h"
20 #include "em_ebi.h"
21 #include "em_gpio.h"
22 #include "em_usart.h"
23 #include "bsp_dk_bcreg_3201.h"
24 #include "bsp.h"
25 
26 #if defined( BSP_DK_BRD3201 )
27 
29 /* USART used for SPI access */
30 #define BSP_SPI_USART_USED USART2
31 #define BSP_SPI_USART_CLK cmuClock_USART2
33 /* GPIO pins used fotr SPI pins, please refer to DK user guide. */
34 #define BSP_PORT_SPI_TX gpioPortC
35 #define BSP_PIN_SPI_TX 2
36 #define BSP_PORT_SPI_RX gpioPortC
37 #define BSP_PIN_SPI_RX 3
38 #define BSP_PORT_SPI_CLK gpioPortC
39 #define BSP_PIN_SPI_CLK 4
40 #define BSP_PORT_SPI_CS gpioPortC
41 #define BSP_PIN_SPI_CS 5
44 typedef enum
45 {
46  BSP_SPI_Audio,
47  BSP_SPI_Ethernet,
48  BSP_SPI_Display,
49  BSP_SPI_OFF,
50 } BSP_SpiControl_TypeDef;
51 
53 typedef enum
54 {
55  BSP_Init_EBI,
56  BSP_Init_SPI,
57  BSP_Init_DIRECT,
58  BSP_Init_OFF,
59 } BSP_Init_TypeDef;
60 
61 static bool EbiInit(void);
62 static void EbiDisable(void);
63 static uint16_t SpiBcAccess(uint8_t addr, uint8_t rw, uint16_t data);
64 static void SpiBcInit(void);
65 static void SpiControl(BSP_SpiControl_TypeDef device);
66 static void SpiBcDisable(void);
67 static bool SpiInit(void);
68 static uint16_t SpiRegisterRead(volatile uint16_t *addr);
69 static void SpiRegisterWrite(volatile uint16_t *addr, uint16_t data);
70 
71 /* Keep intialization mode */
72 static uint32_t bspOperationMode;
73 static BSP_BusControl_TypeDef busMode = BSP_BusControl_Undefined;
74 static volatile const uint16_t *lastAddr = 0;
75 static uint16_t bcFwVersion;
76 
79 /***************************************************************************/
84 /***************************************************************************/
89 /**************************************************************************/
97 int BSP_Disable(void)
98 {
99  if (bspOperationMode == BSP_INIT_DK_EBI)
100  {
101  EbiDisable();
102  }
103  if (bspOperationMode == BSP_INIT_DK_SPI)
104  {
105  SpiBcDisable();
106  }
107  BSP_BusControlModeSet(BSP_BusControl_OFF);
108 
109  return BSP_STATUS_OK;
110 }
111 
112 /**************************************************************************/
127 int BSP_Init(uint32_t flags)
128 {
129  bool ret = false;
130 
131  if (flags & BSP_INIT_DK_EBI)
132  {
133  bspOperationMode = BSP_INIT_DK_EBI;
134  BSP_BusControlModeSet(BSP_BusControl_EBI);
135  ret = EbiInit();
136  }
137  if (flags & BSP_INIT_DK_SPI)
138  {
139  bspOperationMode = BSP_INIT_DK_SPI;
140  BSP_BusControlModeSet(BSP_BusControl_SPI);
141  ret = SpiInit();
142  }
143 
144  if (ret == false)
145  {
146  /* Unable to access board control, this is an abornomal situation. */
147  /* Try to restart kit and reprogram EFM32 with a standard example */
148  /* as this is most likely caused by a peripheral misconfiguration. */
149  while (1) ;
150  }
151 
152  /* Inform AEM application that we are in Energy Mode 0 by default */
153  BSP_RegisterWrite(&BC_REGISTER->EM, 0);
154 
155  /* Read out BC firmware version */
156  bcFwVersion = BSP_RegisterRead(&BC_REGISTER->FW_VERSION);
157 
158  return BSP_STATUS_OK;
159 }
162 /***************************************************************************/
167 /**************************************************************************/
173 BSP_BusControl_TypeDef BSP_BusControlModeGet( void )
174 {
175  return busMode;
176 }
177 
178 /**************************************************************************/
187 int BSP_BusControlModeSet(BSP_BusControl_TypeDef mode)
188 {
189  int retVal = BSP_STATUS_OK;
190 
191  /* Configure GPIO pins for Board Bus mode */
192  /* Note: Inverter on GPIO lines to BC, so signals are active low */
193  CMU_ClockEnable(cmuClock_GPIO, true);
194 
195  busMode = mode;
196 
197  switch (mode)
198  {
199  case BSP_BusControl_OFF:
200  /* Configure board for OFF mode on PB15 MCU_EBI_CONNECT */
201  GPIO_PinModeSet(gpioPortB, 15, gpioModePushPull, 1);
202  /* Configure board for OFF mode on PD13 MCU_SPI_CONNECT */
203  GPIO_PinModeSet(gpioPortD, 13, gpioModePushPull, 1);
204  break;
205 
206  case BSP_BusControl_DIRECT:
207  /* Configure board for DIRECT on PB15 MCU_EBI_CONNECT */
208  GPIO_PinModeSet(gpioPortB, 15, gpioModePushPull, 0);
209  /* Configure board for DIRECT on PD13 MCU_SPI_CONNECT */
210  GPIO_PinModeSet(gpioPortD, 13, gpioModePushPull, 0);
211  break;
212 
213  case BSP_BusControl_SPI:
214  /* Configure board for SPI mode on PB15 MCU_EBI_CONNECT */
215  GPIO_PinModeSet(gpioPortB, 15, gpioModePushPull, 1);
216  /* Configure board for SPI mode on PD13 MCU_SPI_CONNECT */
217  GPIO_PinModeSet(gpioPortD, 13, gpioModePushPull, 0);
218  break;
219 
220  case BSP_BusControl_EBI:
221  /* Configure board for EBI mode on PB15 MCU_EBI_CONNECT */
222  GPIO_PinModeSet(gpioPortB, 15, gpioModePushPull, 0);
223  /* Configure board for EBI mode on PD13 MCU_SPI_CONNECT */
224  GPIO_PinModeSet(gpioPortD, 13, gpioModePushPull, 1);
225  break;
226 
227  default:
228  retVal = BSP_STATUS_ILLEGAL_PARAM;
229  break;
230  }
231  return retVal;
232 }
233 
234 /**************************************************************************/
238 uint32_t BSP_DipSwitchGet(void)
239 {
240  return BSP_RegisterRead(&BC_REGISTER->UIF_DIP) & 0x000f;
241 }
242 
243 /**************************************************************************/
251 int BSP_DisplayControl(BSP_Display_TypeDef option)
252 {
253  uint16_t tmp;
254 
255  switch (option)
256  {
257  case BSP_Display_EBI:
258  BSP_RegisterWrite(&BC_REGISTER->ARB_CTRL, BC_ARB_CTRL_EBI);
259  break;
260 
261  case BSP_Display_SPI:
262  BSP_RegisterWrite(&BC_REGISTER->ARB_CTRL, BC_ARB_CTRL_SPI);
263  break;
264 
265  case BSP_Display_BC:
266  BSP_RegisterWrite(&BC_REGISTER->ARB_CTRL, BC_ARB_CTRL_BC);
267  break;
268 
269  case BSP_Display_PowerEnable:
270  tmp = BSP_RegisterRead(&BC_REGISTER->DISPLAY_CTRL);
271  tmp |= (BC_DISPLAY_CTRL_POWER_ENABLE);
272  BSP_RegisterWrite(&BC_REGISTER->DISPLAY_CTRL, tmp);
273  break;
274 
275  case BSP_Display_PowerDisable:
276  tmp = BSP_RegisterRead(&BC_REGISTER->DISPLAY_CTRL);
277  tmp &= ~(BC_DISPLAY_CTRL_POWER_ENABLE);
278  BSP_RegisterWrite(&BC_REGISTER->DISPLAY_CTRL, tmp);
279  break;
280 
281  case BSP_Display_ResetAssert:
282  tmp = BSP_RegisterRead(&BC_REGISTER->DISPLAY_CTRL);
283  tmp |= (BC_DISPLAY_CTRL_RESET);
284  BSP_RegisterWrite(&BC_REGISTER->DISPLAY_CTRL, tmp);
285  break;
286 
287  case BSP_Display_ResetRelease:
288  tmp = BSP_RegisterRead(&BC_REGISTER->DISPLAY_CTRL);
289  tmp &= ~(BC_DISPLAY_CTRL_RESET);
290  BSP_RegisterWrite(&BC_REGISTER->DISPLAY_CTRL, tmp);
291  break;
292 
293  case BSP_Display_Mode8080:
294  tmp = BSP_RegisterRead(&BC_REGISTER->DISPLAY_CTRL);
295  tmp &= ~(BC_DISPLAY_CTRL_MODE_GENERIC);
296  BSP_RegisterWrite(&BC_REGISTER->DISPLAY_CTRL, tmp);
297  break;
298 
299  case BSP_Display_ModeGeneric:
300  tmp = BSP_RegisterRead(&BC_REGISTER->DISPLAY_CTRL);
301  tmp |= (BC_DISPLAY_CTRL_MODE_GENERIC);
302  BSP_RegisterWrite(&BC_REGISTER->DISPLAY_CTRL, tmp);
303  break;
304 
305  default:
306  /* Unknown command */
307  while (1);
308  }
309 
310  return BSP_STATUS_OK;
311 }
312 
313 /**************************************************************************/
323 int BSP_EbiExtendedAddressRange(bool enable)
324 {
325  if (enable)
326  {
327  BSP_RegisterWrite(&BC_REGISTER->EBI_CTRL, BC_EBI_CTRL_EXTADDR_MASK);
328  }
329  else
330  {
331  BSP_RegisterWrite(&BC_REGISTER->EBI_CTRL, 0);
332  }
333  return BSP_STATUS_OK;
334 }
335 
336 
337 /**************************************************************************/
344 int BSP_EnergyModeSet(uint16_t energyMode)
345 {
346  BSP_RegisterWrite(&BC_REGISTER->EM, energyMode);
347  return BSP_STATUS_OK;
348 }
349 
350 /**************************************************************************/
357 int BSP_InterruptDisable(uint16_t flags)
358 {
359  uint16_t tmp;
360 
361  /* Clear flags from interrupt enable register */
362  tmp = BSP_RegisterRead(&BC_REGISTER->INTEN);
363  flags = ~(flags);
364  tmp &= flags;
365  BSP_RegisterWrite(&BC_REGISTER->INTEN, tmp);
366  return BSP_STATUS_OK;
367 }
368 
369 /**************************************************************************/
376 int BSP_InterruptEnable(uint16_t flags)
377 {
378  uint16_t tmp;
379 
380  /* Add flags to interrupt enable register */
381  tmp = BSP_RegisterRead(&BC_REGISTER->INTEN);
382  tmp |= flags;
383  BSP_RegisterWrite(&BC_REGISTER->INTEN, tmp);
384  return BSP_STATUS_OK;
385 }
386 
387 /**************************************************************************/
394 int BSP_InterruptFlagsClear(uint16_t flags)
395 {
396  uint16_t intFlags;
397 
398  /* Board control firmware version 257 and higher has a new interrupt architecture */
399  if (bcFwVersion < 257)
400  {
401  intFlags = BSP_RegisterRead(&BC_REGISTER->INTFLAG);
402  intFlags &= ~(flags);
403  BSP_RegisterWrite(&BC_REGISTER->INTFLAG, intFlags);
404  }
405  else
406  {
407  BSP_RegisterWrite(&BC_REGISTER->INTCLEAR, flags);
408  }
409  return BSP_STATUS_OK;
410 }
411 
412 /**************************************************************************/
419 int BSP_InterruptFlagsSet(uint16_t flags)
420 {
421  BSP_RegisterWrite(&BC_REGISTER->INTSET, flags);
422  return BSP_STATUS_OK;
423 }
424 
425 /**************************************************************************/
430 uint16_t BSP_InterruptFlagsGet(void)
431 {
432  return BSP_RegisterRead(&BC_REGISTER->INTFLAG);
433 }
434 
435 /**************************************************************************/
440 uint16_t BSP_JoystickGet(void)
441 {
442  return ~(BSP_RegisterRead(&BC_REGISTER->UIF_JOYSTICK)) & 0x001f;
443 }
444 
445 /**************************************************************************/
461 int BSP_PeripheralAccess(BSP_Peripheral_TypeDef perf, bool enable)
462 {
463  uint16_t perfControl;
464 
465  perfControl = BSP_RegisterRead(&BC_REGISTER->PERICON);
466 
467  /* Enable or disable the specified peripheral by setting board control switch */
468  if (enable)
469  {
470  switch (perf)
471  {
472  case BSP_RS232_SHUTDOWN:
473  perfControl |= (1 << BC_PERICON_RS232_SHUTDOWN_SHIFT);
474  break;
475 
476  case BSP_RS232_UART:
477  perfControl &= ~(1 << BC_PERICON_RS232_SHUTDOWN_SHIFT);
478  perfControl &= ~(1 << BC_PERICON_RS232_LEUART_SHIFT);
479  perfControl |= (1 << BC_PERICON_RS232_UART_SHIFT);
480  break;
481 
482  case BSP_RS232_LEUART:
483  perfControl &= ~(1 << BC_PERICON_RS232_SHUTDOWN_SHIFT);
484  perfControl &= ~(1 << BC_PERICON_RS232_UART_SHIFT);
485  perfControl |= (1 << BC_PERICON_RS232_LEUART_SHIFT);
486  break;
487 
488  case BSP_I2C:
489  perfControl |= (1 << BC_PERICON_I2C_SHIFT);
490  break;
491 
492  case BSP_ETH:
493  /* Enable SPI interface */
494  SpiControl(BSP_SPI_Ethernet);
495 
496  /* Enable Ethernet analog switches */
497  perfControl |= (1 << BC_PERICON_I2S_ETH_SHIFT);
498  perfControl |= (1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
499 
500  /* Disable Analog Diff Input - pins PD0 and PD1 is shared */
501  perfControl &= ~(1 << BC_PERICON_ANALOG_DIFF_SHIFT);
502  /* Disable Touch Inputs - pin PD3 is shared */
503  perfControl &= ~(1 << BC_PERICON_TOUCH_SHIFT);
504  /* Disable Analog SE Input - pin PD2 is shared */
505  perfControl &= ~(1 << BC_PERICON_ANALOG_SE_SHIFT);
506  break;
507 
508  case BSP_I2S:
509  /* Direct SPI interface to I2S DAC */
510  SpiControl(BSP_SPI_Audio);
511 
512  /* Also make surea Audio out is connected for I2S operation */
513  perfControl |= (1 << BC_PERICON_AUDIO_OUT_SHIFT);
514  perfControl |= (1 << BC_PERICON_AUDIO_OUT_SEL_SHIFT);
515  perfControl |= (1 << BC_PERICON_I2S_ETH_SHIFT);
516  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
517 
518  /* Disable Analog Diff Input - pins PD0 and PD1 is shared */
519  perfControl &= ~(1 << BC_PERICON_ANALOG_DIFF_SHIFT);
520  /* Disable Touch Inputs - pin PD3 is shared */
521  perfControl &= ~(1 << BC_PERICON_TOUCH_SHIFT);
522  /* Disable Analog SE Input - pin PD2 is shared */
523  perfControl &= ~(1 << BC_PERICON_ANALOG_SE_SHIFT);
524  break;
525 
526  case BSP_TRACE:
527  #if defined(ETM_PRESENT)
528  perfControl |= (1 << BC_PERICON_TRACE_SHIFT);
529  break;
530  #else
531  /* TRACE is not available on EFM32G890F128, application error */
532  while (1) ;
533  #endif
534 
535  case BSP_TOUCH:
536  perfControl |= (1 << BC_PERICON_TOUCH_SHIFT);
537  /* Disconnect SPI switch, pin PD3 is shared */
538  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SHIFT);
539  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
540  SpiControl(BSP_SPI_OFF);
541  break;
542 
543  case BSP_AUDIO_IN:
544  perfControl |= (1 << BC_PERICON_AUDIO_IN_SHIFT);
545  break;
546 
547  case BSP_AUDIO_OUT:
548  perfControl &= ~(1 << BC_PERICON_AUDIO_OUT_SEL_SHIFT);
549  perfControl |= (1 << BC_PERICON_AUDIO_OUT_SHIFT);
550  break;
551 
552  case BSP_ANALOG_DIFF:
553  perfControl |= (1 << BC_PERICON_ANALOG_DIFF_SHIFT);
554  /* Disconnect SPI switch, pin PD0 and PD1 is shared */
555  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SHIFT);
556  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
557  SpiControl(BSP_SPI_OFF);
558  break;
559 
560  case BSP_ANALOG_SE:
561  perfControl |= (1 << BC_PERICON_ANALOG_SE_SHIFT);
562  /* Disconnect SPI switch, pin PD2 is shared */
563  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SHIFT);
564  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
565  SpiControl(BSP_SPI_OFF);
566  break;
567 
568  case BSP_MICROSD:
569  perfControl |= (1 << BC_PERICON_SPI_SHIFT);
570  break;
571 
572  case BSP_TFT:
573  /* Enable SPI to SSD2119 */
574  SpiControl(BSP_SPI_Display);
575  /* Enable SPI analog switch */
576  perfControl |= (1 << BC_PERICON_I2S_ETH_SHIFT);
577  /* Disable Analog Diff Input - pins D0 and D1 is shared */
578  perfControl &= ~(1 << BC_PERICON_ANALOG_DIFF_SHIFT);
579  /* Disable Touch Inputs - pin D3 is shared */
580  perfControl &= ~(1 << BC_PERICON_TOUCH_SHIFT);
581  /* Disable Analog SE Input - pin D2 is shared */
582  perfControl &= ~(1 << BC_PERICON_ANALOG_SE_SHIFT);
583  break;
584  }
585  }
586  else
587  {
588  switch (perf)
589  {
590  case BSP_RS232_SHUTDOWN:
591  perfControl &= ~(1 << BC_PERICON_RS232_SHUTDOWN_SHIFT);
592  break;
593 
594  case BSP_RS232_UART:
595  perfControl |= (1 << BC_PERICON_RS232_SHUTDOWN_SHIFT);
596  perfControl &= ~(1 << BC_PERICON_RS232_UART_SHIFT);
597  break;
598 
599  case BSP_RS232_LEUART:
600  perfControl |= (1 << BC_PERICON_RS232_SHUTDOWN_SHIFT);
601  perfControl &= ~(1 << BC_PERICON_RS232_LEUART_SHIFT);
602  break;
603 
604  case BSP_I2C:
605  perfControl &= ~(1 << BC_PERICON_I2C_SHIFT);
606  break;
607 
608  case BSP_ETH:
609  /* Disable SPI interface */
610  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SHIFT);
611  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
612  SpiControl(BSP_SPI_OFF);
613  break;
614 
615  case BSP_I2S:
616  /* Disable SPI interface and audio out */
617  perfControl &= ~(1 << BC_PERICON_AUDIO_OUT_SHIFT);
618  perfControl &= ~(1 << BC_PERICON_AUDIO_OUT_SEL_SHIFT);
619  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SHIFT);
620  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
621  SpiControl(BSP_SPI_OFF);
622  break;
623 
624  case BSP_TRACE:
625  #if defined(ETM_PRESENT)
626  perfControl &= ~(1 << BC_PERICON_TRACE_SHIFT);
627  break;
628  #else
629  /* TRACE is not available on EFM32G890F128, application error */
630  while (1) ;
631  #endif
632 
633  case BSP_TOUCH:
634  perfControl &= ~(1 << BC_PERICON_TOUCH_SHIFT);
635  break;
636 
637  case BSP_AUDIO_IN:
638  perfControl &= ~(1 << BC_PERICON_AUDIO_IN_SHIFT);
639  break;
640 
641  case BSP_AUDIO_OUT:
642  perfControl &= ~(1 << BC_PERICON_AUDIO_OUT_SEL_SHIFT);
643  perfControl &= ~(1 << BC_PERICON_AUDIO_OUT_SHIFT);
644  break;
645 
646  case BSP_ANALOG_DIFF:
647  perfControl &= ~(1 << BC_PERICON_ANALOG_DIFF_SHIFT);
648  break;
649 
650  case BSP_ANALOG_SE:
651  perfControl &= ~(1 << BC_PERICON_ANALOG_SE_SHIFT);
652  break;
653 
654  case BSP_MICROSD:
655  perfControl &= ~(1 << BC_PERICON_SPI_SHIFT);
656  break;
657 
658  case BSP_TFT:
659  /* Disable SPI interface */
660  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SHIFT);
661  perfControl &= ~(1 << BC_PERICON_I2S_ETH_SEL_SHIFT);
662  SpiControl(BSP_SPI_OFF);
663  break;
664  }
665  }
666  /* Write back register */
667  BSP_RegisterWrite(&BC_REGISTER->PERICON, perfControl);
668 
669  return BSP_STATUS_OK;
670 }
671 
672 /**************************************************************************/
677 uint16_t BSP_PushButtonsGet(void)
678 {
679  return (~BSP_RegisterRead(&BC_REGISTER->UIF_PB)) & 0x000F;
680 }
681 
682 /**************************************************************************/
687 uint16_t BSP_RegisterRead(volatile uint16_t *addr)
688 {
689  if (bspOperationMode == BSP_INIT_DK_EBI)
690  {
691  return *addr;
692  }
693  else
694  {
695  return SpiRegisterRead(addr);
696  }
697 }
698 
699 /**************************************************************************/
704 int BSP_RegisterWrite(volatile uint16_t *addr, uint16_t data)
705 {
706  if (bspOperationMode == BSP_INIT_DK_EBI)
707  {
708  *addr = data;
709  }
710  else
711  {
712  SpiRegisterWrite(addr, data);
713  }
714  return BSP_STATUS_OK;
715 }
721 static void EbiDisable(void)
722 {
723 #if defined(_EFM32_GECKO_FAMILY)
724 
725  /* Configure GPIO pins as disabled */
726  GPIO_PinModeSet( gpioPortA, 0, gpioModeDisabled, 0 );
727  GPIO_PinModeSet( gpioPortA, 1, gpioModeDisabled, 0 );
728  GPIO_PinModeSet( gpioPortA, 2, gpioModeDisabled, 0 );
729  GPIO_PinModeSet( gpioPortA, 3, gpioModeDisabled, 0 );
730  GPIO_PinModeSet( gpioPortA, 4, gpioModeDisabled, 0 );
731  GPIO_PinModeSet( gpioPortA, 5, gpioModeDisabled, 0 );
732  GPIO_PinModeSet( gpioPortA, 6, gpioModeDisabled, 0 );
733 
734  GPIO_PinModeSet( gpioPortA, 15, gpioModeDisabled, 0 );
735 
736  GPIO_PinModeSet( gpioPortD, 9, gpioModeDisabled, 0 );
737  GPIO_PinModeSet( gpioPortD, 10, gpioModeDisabled, 0 );
738  GPIO_PinModeSet( gpioPortD, 11, gpioModeDisabled, 0 );
739  GPIO_PinModeSet( gpioPortD, 12, gpioModeDisabled, 0 );
740 
741  GPIO_PinModeSet( gpioPortE, 8, gpioModeDisabled, 0 );
742  GPIO_PinModeSet( gpioPortE, 9, gpioModeDisabled, 0 );
743  GPIO_PinModeSet( gpioPortE, 10, gpioModeDisabled, 0 );
744  GPIO_PinModeSet( gpioPortE, 11, gpioModeDisabled, 0 );
745  GPIO_PinModeSet( gpioPortE, 12, gpioModeDisabled, 0 );
746  GPIO_PinModeSet( gpioPortE, 13, gpioModeDisabled, 0 );
747  GPIO_PinModeSet( gpioPortE, 14, gpioModeDisabled, 0 );
748  GPIO_PinModeSet( gpioPortE, 15, gpioModeDisabled, 0 );
749 
750  GPIO_PinModeSet( gpioPortF, 2, gpioModeDisabled, 0 );
751  GPIO_PinModeSet( gpioPortF, 3, gpioModeDisabled, 0 );
752  GPIO_PinModeSet( gpioPortF, 4, gpioModeDisabled, 0 );
753  GPIO_PinModeSet( gpioPortF, 5, gpioModeDisabled, 0 );
754 
755  /* EBI Byte Lane 0 support BL0/BL1 */
756  GPIO_PinModeSet( gpioPortF, 6, gpioModeDisabled, 0 );
757  GPIO_PinModeSet( gpioPortF, 7, gpioModeDisabled, 0 );
758 
759 #else
760 
761  /* Configure GPIO pins as disabled */
762  /* EBI AD9..15 */
763  GPIO_PinModeSet( gpioPortA, 0, gpioModeDisabled, 0 );
764  GPIO_PinModeSet( gpioPortA, 1, gpioModeDisabled, 0 );
765  GPIO_PinModeSet( gpioPortA, 2, gpioModeDisabled, 0 );
766  GPIO_PinModeSet( gpioPortA, 3, gpioModeDisabled, 0 );
767  GPIO_PinModeSet( gpioPortA, 4, gpioModeDisabled, 0 );
768  GPIO_PinModeSet( gpioPortA, 5, gpioModeDisabled, 0 );
769  GPIO_PinModeSet( gpioPortA, 6, gpioModeDisabled, 0 );
770 
771  /* EBI AD8 */
772  GPIO_PinModeSet( gpioPortA, 15, gpioModeDisabled, 0 );
773 
774  /* EBI A16-A22 */
775  GPIO_PinModeSet( gpioPortB, 0, gpioModeDisabled, 0 );
776  GPIO_PinModeSet( gpioPortB, 1, gpioModeDisabled, 0 );
777  GPIO_PinModeSet( gpioPortB, 2, gpioModeDisabled, 0 );
778  GPIO_PinModeSet( gpioPortB, 3, gpioModeDisabled, 0 );
779  GPIO_PinModeSet( gpioPortB, 4, gpioModeDisabled, 0 );
780  GPIO_PinModeSet( gpioPortB, 5, gpioModeDisabled, 0 );
781  GPIO_PinModeSet( gpioPortB, 6, gpioModeDisabled, 0 );
782 
783  /* EBI CS0-CS3 */
784  GPIO_PinModeSet( gpioPortD, 9, gpioModeDisabled, 0 );
785  GPIO_PinModeSet( gpioPortD, 10, gpioModeDisabled, 0 );
786  GPIO_PinModeSet( gpioPortD, 11, gpioModeDisabled, 0 );
787  GPIO_PinModeSet( gpioPortD, 12, gpioModeDisabled, 0 );
788 
789  /* EBI AD0..7 */
790  GPIO_PinModeSet( gpioPortE, 8, gpioModeDisabled, 0 );
791  GPIO_PinModeSet( gpioPortE, 9, gpioModeDisabled, 0 );
792  GPIO_PinModeSet( gpioPortE, 10, gpioModeDisabled, 0 );
793  GPIO_PinModeSet( gpioPortE, 11, gpioModeDisabled, 0 );
794  GPIO_PinModeSet( gpioPortE, 12, gpioModeDisabled, 0 );
795  GPIO_PinModeSet( gpioPortE, 13, gpioModeDisabled, 0 );
796  GPIO_PinModeSet( gpioPortE, 14, gpioModeDisabled, 0 );
797  GPIO_PinModeSet( gpioPortE, 15, gpioModeDisabled, 0 );
798 
799  /* EBI ARDY/WEN/REN/ALE */
800  GPIO_PinModeSet( gpioPortF, 2, gpioModeDisabled, 0 );
801  GPIO_PinModeSet( gpioPortF, 8, gpioModeDisabled, 0 );
802  GPIO_PinModeSet( gpioPortF, 9, gpioModeDisabled, 0 );
803  GPIO_PinModeSet( gpioPortC, 11, gpioModeDisabled, 0 );
804 
805  /* EBI Byte Lane 0 support BL0/BL1 */
806  GPIO_PinModeSet( gpioPortF, 6, gpioModeDisabled, 0 );
807  GPIO_PinModeSet( gpioPortF, 7, gpioModeDisabled, 0 );
808 
809 #endif
810 
811  /* Reset EBI configuration */
812  EBI_Disable();
813 
814  /* Turn off EBI clock */
815  CMU_ClockEnable(cmuClock_EBI, false);
816 }
817 
818 /**************************************************************************/
826 static bool EbiInit(void)
827 {
828  EBI_Init_TypeDef ebiConfig = EBI_INIT_DEFAULT;
829 
830  /* Enable clocks */
831  CMU_ClockEnable(cmuClock_EBI, true);
832  CMU_ClockEnable(cmuClock_GPIO, true);
833 
834 #if defined(_EFM32_GECKO_FAMILY)
835 
836  /* Configure LCD_SELECT (EBI and LCD cannot be shared) */
837  GPIO_PinModeSet( gpioPortC, 12, gpioModePushPull, 1 );
838 
839  /* Configure GPIO pins as push pull */
840  /* EBI AD9..15 */
841  GPIO_PinModeSet( gpioPortA, 0, gpioModePushPull, 0 );
842  GPIO_PinModeSet( gpioPortA, 1, gpioModePushPull, 0 );
843  GPIO_PinModeSet( gpioPortA, 2, gpioModePushPull, 0 );
844  GPIO_PinModeSet( gpioPortA, 3, gpioModePushPull, 0 );
845  GPIO_PinModeSet( gpioPortA, 4, gpioModePushPull, 0 );
846  GPIO_PinModeSet( gpioPortA, 5, gpioModePushPull, 0 );
847  GPIO_PinModeSet( gpioPortA, 6, gpioModePushPull, 0 );
848 
849  /* EBI AD8 */
850  GPIO_PinModeSet( gpioPortA, 15, gpioModePushPull, 0 );
851 
852  /* EBI CS0-CS3 */
853  GPIO_PinModeSet( gpioPortD, 9, gpioModePushPull, 1 );
854  GPIO_PinModeSet( gpioPortD, 10, gpioModePushPull, 1 );
855  GPIO_PinModeSet( gpioPortD, 11, gpioModePushPull, 1 );
856  GPIO_PinModeSet( gpioPortD, 12, gpioModePushPull, 1 );
857 
858  /* EBI AD0..7 */
859  GPIO_PinModeSet( gpioPortE, 8, gpioModePushPull, 0 );
860  GPIO_PinModeSet( gpioPortE, 9, gpioModePushPull, 0 );
861  GPIO_PinModeSet( gpioPortE, 10, gpioModePushPull, 0 );
862  GPIO_PinModeSet( gpioPortE, 11, gpioModePushPull, 0 );
863  GPIO_PinModeSet( gpioPortE, 12, gpioModePushPull, 0 );
864  GPIO_PinModeSet( gpioPortE, 13, gpioModePushPull, 0 );
865  GPIO_PinModeSet( gpioPortE, 14, gpioModePushPull, 0 );
866  GPIO_PinModeSet( gpioPortE, 15, gpioModePushPull, 0 );
867 
868  /* EBI ARDY/ALEN/Wen/Ren */
869  GPIO_PinModeSet( gpioPortF, 2, gpioModeInput, 0 );
870  GPIO_PinModeSet( gpioPortF, 3, gpioModePushPull, 0 );
871  GPIO_PinModeSet( gpioPortF, 4, gpioModePushPull, 1 );
872  GPIO_PinModeSet( gpioPortF, 5, gpioModePushPull, 1 );
873 
874  /* Byte Lanes */
875  GPIO_PinModeSet( gpioPortF, 6, gpioModePushPull, 0 );
876  GPIO_PinModeSet( gpioPortF, 7, gpioModePushPull, 0 );
877 
878  /* Configure EBI controller, changing default values */
879  ebiConfig.mode = ebiModeD16A16ALE;
880 
881  /* --------------------------------------------------------- */
882  /* Board Control Registers, Bank 0, Base Address 0x80000000 */
883  /* FPGA Xilinx Spartan XC6SLX9 CSG324 */
884  /* --------------------------------------------------------- */
885 
886  /* ----------------------------------------------------- */
887  /* TFT-LCD Registers, Bank1, Base Address 0x84000000 */
888  /* URT USMH_8252MD_320X240_RGB */
889  /* Solomon Systech SSD 2119 */
890  /* ----------------------------------------------------- */
891 
892  /* ---------------------------------------------------- */
893  /* External 4MB PSRAM, Bank 2, Base Address 0x88000000 */
894  /* Micron MT45W2MW16PGA-70 IT, 32Mb Cellular RAM */
895  /* ---------------------------------------------------- */
896 
897  /* ----------------------------------------- */
898  /* NOR Flash, Bank3, Base Address 0x8c000000 */
899  /* Spansion flash S29GLxxx_FBGA */
900  /* ----------------------------------------- */
901 
902  ebiConfig.banks = EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3;
903  ebiConfig.csLines = EBI_CS0 | EBI_CS1 | EBI_CS2 | EBI_CS3;
904 
905  /* Address Setup and hold time */
906  ebiConfig.addrHoldCycles = 3;
907  ebiConfig.addrSetupCycles = 3;
908 
909  /* Read cycle times */
910  ebiConfig.readStrobeCycles = 7;
911  ebiConfig.readHoldCycles = 3;
912  ebiConfig.readSetupCycles = 3;
913 
914  /* Write cycle times */
915  ebiConfig.writeStrobeCycles = 7;
916  ebiConfig.writeHoldCycles = 3;
917  ebiConfig.writeSetupCycles = 3;
918 
919  /* Address Latch Enable polarity is active high */
920  ebiConfig.alePolarity = ebiActiveHigh;
921 
922  /* Configure EBI */
923  EBI_Init(&ebiConfig);
924 
925 #else
926 
927  /* Giant or Leopard family. */
928 
929  /* Configure GPIO pins as push pull */
930  /* EBI AD9..15 */
931  GPIO_PinModeSet( gpioPortA, 0, gpioModePushPull, 0 );
932  GPIO_PinModeSet( gpioPortA, 1, gpioModePushPull, 0 );
933  GPIO_PinModeSet( gpioPortA, 2, gpioModePushPull, 0 );
934  GPIO_PinModeSet( gpioPortA, 3, gpioModePushPull, 0 );
935  GPIO_PinModeSet( gpioPortA, 4, gpioModePushPull, 0 );
936  GPIO_PinModeSet( gpioPortA, 5, gpioModePushPull, 0 );
937  GPIO_PinModeSet( gpioPortA, 6, gpioModePushPull, 0 );
938 
939  /* EBI AD8 */
940  GPIO_PinModeSet( gpioPortA, 15, gpioModePushPull, 0 );
941 
942  /* EBI A16-A22 */
943  GPIO_PinModeSet( gpioPortB, 0, gpioModePushPull, 0 );
944  GPIO_PinModeSet( gpioPortB, 1, gpioModePushPull, 0 );
945  GPIO_PinModeSet( gpioPortB, 2, gpioModePushPull, 0 );
946  GPIO_PinModeSet( gpioPortB, 3, gpioModePushPull, 0 );
947  GPIO_PinModeSet( gpioPortB, 4, gpioModePushPull, 0 );
948  GPIO_PinModeSet( gpioPortB, 5, gpioModePushPull, 0 );
949  GPIO_PinModeSet( gpioPortB, 6, gpioModePushPull, 0 );
950 
951  /* EBI CS0-CS3 */
952  GPIO_PinModeSet( gpioPortD, 9, gpioModePushPull, 1 );
953  GPIO_PinModeSet( gpioPortD, 10, gpioModePushPull, 1 );
954  GPIO_PinModeSet( gpioPortD, 11, gpioModePushPull, 1 );
955  GPIO_PinModeSet( gpioPortD, 12, gpioModePushPull, 1 );
956 
957  /* EBI AD0..7 */
958  GPIO_PinModeSet( gpioPortE, 8, gpioModePushPull, 0 );
959  GPIO_PinModeSet( gpioPortE, 9, gpioModePushPull, 0 );
960  GPIO_PinModeSet( gpioPortE, 10, gpioModePushPull, 0 );
961  GPIO_PinModeSet( gpioPortE, 11, gpioModePushPull, 0 );
962  GPIO_PinModeSet( gpioPortE, 12, gpioModePushPull, 0 );
963  GPIO_PinModeSet( gpioPortE, 13, gpioModePushPull, 0 );
964  GPIO_PinModeSet( gpioPortE, 14, gpioModePushPull, 0 );
965  GPIO_PinModeSet( gpioPortE, 15, gpioModePushPull, 0 );
966 
967  /* EBI ARDY/WEN/REN/ALE */
968  GPIO_PinModeSet( gpioPortF, 2, gpioModeInput, 0 );
969  GPIO_PinModeSet( gpioPortF, 8, gpioModePushPull, 0 );
970  GPIO_PinModeSet( gpioPortF, 9, gpioModePushPull, 0 );
971  GPIO_PinModeSet( gpioPortC, 11, gpioModePushPull, 0 );
972 
973  /* EBI Byte Lane 0 support BL0/BL1 */
974  GPIO_PinModeSet( gpioPortF, 6, gpioModePushPull, 0 );
975  GPIO_PinModeSet( gpioPortF, 7, gpioModePushPull, 0 );
976 
977  /* ---------------------------------------------------- */
978  /* External 4MB PSRAM, Bank 2, Base Address 0x88000000 */
979  /* Micron MT45W2MW16PGA-70 IT, 32Mb Cellular RAM */
980  /* ---------------------------------------------------- */
981  ebiConfig.banks = EBI_BANK2;
982  ebiConfig.csLines = EBI_CS2;
983  ebiConfig.mode = ebiModeD16A16ALE;
984  ebiConfig.alePolarity = ebiActiveHigh;
985  ebiConfig.blEnable = true;
986  ebiConfig.noIdle = true;
987  ebiConfig.ardyEnable = false;
988  ebiConfig.addrHalfALE = true;
989  ebiConfig.readPrefetch = true;
990  ebiConfig.aLow = ebiALowA16;
991  ebiConfig.aHigh = ebiAHighA23;
992  ebiConfig.location = ebiLocation1;
993 
994  /* Address Setup and hold time */
995  ebiConfig.addrHoldCycles = 0;
996  ebiConfig.addrSetupCycles = 0;
997 
998  /* Read cycle times */
999  ebiConfig.readStrobeCycles = 4;
1000  ebiConfig.readHoldCycles = 0;
1001  ebiConfig.readSetupCycles = 0;
1002 
1003  /* Write cycle times */
1004  ebiConfig.writeStrobeCycles = 2;
1005  ebiConfig.writeHoldCycles = 0;
1006  ebiConfig.writeSetupCycles = 0;
1007 
1008  /* Configure EBI bank 2 - external PSRAM */
1009  EBI_Init(&ebiConfig);
1010 
1011  /* --------------------------------------------------------- */
1012  /* Board Control Registers, Bank 0, Base Address 0x80000000 */
1013  /* FPGA Xilinx Spartan XC6SLX9 CSG324 */
1014  /* --------------------------------------------------------- */
1015  ebiConfig.banks = EBI_BANK0;
1016  ebiConfig.csLines = EBI_CS0;
1017  ebiConfig.mode = ebiModeD16A16ALE;;
1018  ebiConfig.alePolarity = ebiActiveHigh;
1019  /* keep blEnable */
1020  ebiConfig.blEnable = false;
1021  ebiConfig.addrHalfALE = true;
1022  ebiConfig.readPrefetch = false;
1023  ebiConfig.noIdle = true;
1024 
1025  /* keep alow/ahigh configuration */
1026  /* ebiConfig.aLow = ebiALowA0; - needs to be set for PSRAM */
1027  /* ebiConfig.aHigh = ebiAHighA0; - needs to be set for PSRAM */
1028 
1029  /* Address Setup and hold time */
1030  ebiConfig.addrHoldCycles = 3;
1031  ebiConfig.addrSetupCycles = 3;
1032 
1033  /* Read cycle times */
1034  ebiConfig.readStrobeCycles = 7;
1035  ebiConfig.readHoldCycles = 3;
1036  ebiConfig.readSetupCycles = 3;
1037 
1038  /* Write cycle times */
1039  ebiConfig.writeStrobeCycles = 7;
1040  ebiConfig.writeHoldCycles = 3;
1041  ebiConfig.writeSetupCycles = 3;
1042 
1043  /* Configure EBI bank 0 */
1044  EBI_Init(&ebiConfig);
1045 
1046  /* ----------------------------------------------------- */
1047  /* TFT-LCD Registers, Bank1, Base Address 0x84000000 */
1048  /* URT USMH_8252MD_320X240_RGB */
1049  /* Solomon Systech SSD 2119 */
1050  /* ----------------------------------------------------- */
1051  ebiConfig.banks = EBI_BANK1;
1052  ebiConfig.csLines = EBI_CS1;
1053 
1054  /* Address Setup and hold time */
1055  ebiConfig.addrHoldCycles = 1;
1056  ebiConfig.addrSetupCycles = 1;
1057 
1058  /* Read cycle times */
1059  ebiConfig.readStrobeCycles = 7;
1060  ebiConfig.readHoldCycles = 3;
1061  ebiConfig.readSetupCycles = 3;
1062 
1063  /* Write cycle times */
1064  ebiConfig.writeStrobeCycles = 2;
1065  ebiConfig.writeHoldCycles = 1;
1066  ebiConfig.writeSetupCycles = 1;
1067 
1068  /* Configure EBI bank 1 */
1069  EBI_Init(&ebiConfig);
1070 
1071  /* ----------------------------------------- */
1072  /* NOR Flash, Bank3, Base Address 0x8c000000 */
1073  /* Spansion flash S29GLxxx_FBGA */
1074  /* ----------------------------------------- */
1075  ebiConfig.banks = EBI_BANK3;
1076  ebiConfig.csLines = EBI_CS3;
1077  ebiConfig.mode = ebiModeD16A16ALE;
1078  ebiConfig.alePolarity = ebiActiveHigh;
1079 
1080  /* keep blEnable */
1081  ebiConfig.blEnable = true;
1082  ebiConfig.addrHalfALE = true;
1083  ebiConfig.readPrefetch = false;
1084  ebiConfig.noIdle = true;
1085 
1086  /* Address Setup and hold time */
1087  ebiConfig.addrHoldCycles = 0;
1088  ebiConfig.addrSetupCycles = 0;
1089 
1090  /* Read cycle times */
1091  ebiConfig.readStrobeCycles = 6;
1092  ebiConfig.readHoldCycles = 0;
1093  ebiConfig.readSetupCycles = 0;
1094 
1095  /* Write cycle times */
1096  ebiConfig.writeStrobeCycles = 5;
1097  ebiConfig.writeHoldCycles = 0;
1098  ebiConfig.writeSetupCycles = 0;
1099 
1100  /* Configure EBI bank 3 */
1101  EBI_Init(&ebiConfig);
1102 
1103  /* Enable extended address range */
1104  BSP_EbiExtendedAddressRange(true);
1105 #endif
1106 
1107  /* Verify connectivity to Board Control registers */
1108  if (BC_REGISTER->MAGIC != 0xef32)
1109  {
1110  return false;
1111  }
1112  else
1113  {
1114  return true;
1115  }
1116 }
1117 
1118 static uint16_t SpiBcAccess(uint8_t addr, uint8_t rw, uint16_t data)
1119 {
1120  uint16_t tmp;
1121 
1122  /* Enable CS */
1123  GPIO_PinOutClear(BSP_PORT_SPI_CS, BSP_PIN_SPI_CS);
1124 
1125  /* Write SPI address MSB */
1126  USART_Tx(BSP_SPI_USART_USED, (addr & 0x3) | rw << 3);
1127  /* Just ignore data read back */
1128  USART_Rx(BSP_SPI_USART_USED);
1129 
1130  /* Write SPI address LSB */
1131  USART_Tx(BSP_SPI_USART_USED, data & 0xFF);
1132 
1133  tmp = (uint16_t) USART_Rx(BSP_SPI_USART_USED);
1134 
1135  /* SPI data MSB */
1136  USART_Tx(BSP_SPI_USART_USED, data >> 8);
1137  tmp |= (uint16_t) USART_Rx(BSP_SPI_USART_USED) << 8;
1138 
1139  /* Disable CS */
1140  GPIO_PinOutSet(BSP_PORT_SPI_CS, BSP_PIN_SPI_CS);
1141 
1142  return tmp;
1143 }
1144 
1145 static void SpiBcDisable(void)
1146 {
1147  /* Restore and disable USART */
1148  USART_Reset(BSP_SPI_USART_USED);
1149 
1150  GPIO_PinModeSet(BSP_PORT_SPI_TX, BSP_PIN_SPI_TX, gpioModeDisabled, 0);
1151  GPIO_PinModeSet(BSP_PORT_SPI_RX, BSP_PIN_SPI_RX, gpioModeDisabled, 0);
1152  GPIO_PinModeSet(BSP_PORT_SPI_CLK, BSP_PIN_SPI_CLK, gpioModeDisabled, 0);
1153  GPIO_PinModeSet(BSP_PORT_SPI_CS, BSP_PIN_SPI_CS, gpioModeDisabled, 0);
1154 
1155  /* Disable USART clock - we can't disable GPIO or HFPER as we don't know who else
1156  * might be using it */
1157  CMU_ClockEnable(BSP_SPI_USART_CLK, false);
1158 }
1159 
1160 static void SpiBcInit(void)
1161 {
1162  USART_InitSync_TypeDef bcinit = USART_INITSYNC_DEFAULT;
1163 
1164  /* Enable module clocks */
1165  CMU_ClockEnable(BSP_SPI_USART_CLK, true);
1166 
1167  /* Configure SPI pins */
1168  GPIO_PinModeSet(BSP_PORT_SPI_TX, BSP_PIN_SPI_TX, gpioModePushPull, 0);
1169  GPIO_PinModeSet(BSP_PORT_SPI_RX, BSP_PIN_SPI_RX, gpioModeInput, 0);
1170  GPIO_PinModeSet(BSP_PORT_SPI_CLK, BSP_PIN_SPI_CLK, gpioModePushPull, 0);
1171 
1172  /* Keep CS high to not activate slave */
1173  GPIO_PinModeSet(BSP_PORT_SPI_CS, BSP_PIN_SPI_CS, gpioModePushPull, 1);
1174 
1175  /* Configure to use SPI master with manual CS */
1176  /* For now, configure SPI for worst case 48/32MHz clock in order to work */
1177  /* for all configurations. */
1178 
1179  #if defined(_EFM32_GECKO_FAMILY)
1180  bcinit.refFreq = 32000000;
1181  #else
1182  bcinit.refFreq = 48000000;
1183  #endif
1184  bcinit.baudrate = 7000000;
1185 
1186  /* Initialize USART */
1187  USART_InitSync(BSP_SPI_USART_USED, &bcinit);
1188 
1189  /* Enable pins at default location */
1190  BSP_SPI_USART_USED->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN;
1191 }
1192 
1193 static void SpiControl(BSP_SpiControl_TypeDef device)
1194 {
1195  switch (device)
1196  {
1197  case BSP_SPI_Audio:
1198  BSP_RegisterWrite(&BC_REGISTER->SPI_DEMUX, BC_SPI_DEMUX_SLAVE_AUDIO);
1199  break;
1200 
1201  case BSP_SPI_Ethernet:
1202  BSP_RegisterWrite(&BC_REGISTER->SPI_DEMUX, BC_SPI_DEMUX_SLAVE_ETHERNET);
1203  break;
1204 
1205  case BSP_SPI_Display:
1206  BSP_RegisterWrite(&BC_REGISTER->SPI_DEMUX, BC_SPI_DEMUX_SLAVE_DISPLAY);
1207  break;
1208 
1209  case BSP_SPI_OFF:
1210  USART_Reset(USART1);
1211  CMU_ClockEnable(cmuClock_USART1, false);
1212  break;
1213  }
1214 }
1215 
1216 static bool SpiInit(void)
1217 {
1218  uint16_t bcMagic;
1219 
1220  /* Enable HF and GPIO clocks */
1221  CMU_ClockEnable(cmuClock_HFPER, true);
1222  CMU_ClockEnable(cmuClock_GPIO, true);
1223 
1224  SpiBcInit();
1225  /* Read "board control Magic" register to verify SPI is up and running */
1226  /* if not FPGA is configured to be in EBI mode */
1227  bcMagic = SpiRegisterRead(&BC_REGISTER->MAGIC);
1228  if (bcMagic != BC_MAGIC_VALUE)
1229  {
1230  return false;
1231  }
1232  else
1233  {
1234  return true;
1235  }
1236 }
1237 
1238 static uint16_t SpiRegisterRead(volatile uint16_t *addr)
1239 {
1240  uint16_t data;
1241 
1242  if (addr != lastAddr)
1243  {
1244  SpiBcAccess(0x00, 0, 0xFFFF & ((uint32_t) addr)); /* LSBs of address */
1245  SpiBcAccess(0x01, 0, 0xFF & ((uint32_t) addr >> 16)); /* MSBs of address */
1246  SpiBcAccess(0x02, 0, (0x0C000000 & (uint32_t) addr) >> 26); /* Chip select */
1247  }
1248  /* Read twice; when register address has changed we need two SPI transfer
1249  * to clock out valid data through board controller FIFOs */
1250  data = SpiBcAccess(0x03, 1, 0);
1251  data = SpiBcAccess(0x03, 1, 0);
1252 
1253  lastAddr = addr;
1254  return data;
1255 }
1256 
1257 static void SpiRegisterWrite(volatile uint16_t *addr, uint16_t data)
1258 {
1259  if (addr != lastAddr)
1260  {
1261  SpiBcAccess(0x00, 0, 0xFFFF & ((uint32_t) addr)); /* LSBs of address */
1262  SpiBcAccess(0x01, 0, 0xFF & ((uint32_t) addr >> 16)); /* MSBs of address */
1263  SpiBcAccess(0x02, 0, (0x0C000000 & (uint32_t) addr) >> 26); /* Chip select */
1264  }
1265  SpiBcAccess(0x03, 0, data); /* Data */
1266  lastAddr = addr;
1267 }
1268 
1270 #endif /* BSP_DK_BRD3201 */
EBI_Init_TypeDef::addrSetupCycles
int addrSetupCycles
Definition: em_ebi.h:345
em_cmu.h
Clock management unit (CMU) API.
BC_PERICON_AUDIO_IN_SHIFT
#define BC_PERICON_AUDIO_IN_SHIFT
Definition: bsp_dk_bcreg_3201.h:199
USART1
#define USART1
Definition: efm32gg995f1024.h:395
EBI_Init_TypeDef::readStrobeCycles
int readStrobeCycles
Definition: em_ebi.h:355
BC_SPI_DEMUX_SLAVE_ETHERNET
#define BC_SPI_DEMUX_SLAVE_ETHERNET
Definition: bsp_dk_bcreg_3201.h:209
EBI_Init_TypeDef::readSetupCycles
int readSetupCycles
Definition: em_ebi.h:353
USART_Tx
void USART_Tx(USART_TypeDef *usart, uint8_t data)
Transmit one 4-9 bit frame.
Definition: em_usart.c:1084
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uint16_t BSP_PushButtonsGet(void)
Get status of the pushbutton switches on the DK.
Definition: bsp_dk_3201.c:677
EBI_BANK1
#define EBI_BANK1
Definition: em_ebi.h:76
bsp.h
Board support package API definitions.
USART_InitSync_TypeDef::baudrate
uint32_t baudrate
Definition: em_usart.h:430
BC_PERICON_RS232_SHUTDOWN_SHIFT
#define BC_PERICON_RS232_SHUTDOWN_SHIFT
Definition: bsp_dk_bcreg_3201.h:191
USART_InitSync
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
Init USART for synchronous mode.
Definition: em_usart.c:640
BC_SPI_DEMUX_SLAVE_AUDIO
#define BC_SPI_DEMUX_SLAVE_AUDIO
Definition: bsp_dk_bcreg_3201.h:208
BSP_EnergyModeSet
int BSP_EnergyModeSet(uint16_t energyMode)
Inform board controller about current energy mode.
Definition: bsp_dk_3201.c:344
EBI_Init_TypeDef::aLow
EBI_ALow_TypeDef aLow
Definition: em_ebi.h:378
BC_PERICON_I2C_SHIFT
#define BC_PERICON_I2C_SHIFT
Definition: bsp_dk_bcreg_3201.h:194
USART_InitSync_TypeDef
Definition: em_usart.h:418
BSP_RS232_LEUART
Definition: bsp.h:121
BSP_BusControlModeSet
int BSP_BusControlModeSet(BSP_BusControl_TypeDef mode)
Configure Board Controller bus decode logic.
Definition: bsp_dk_3201.c:187
EBI_Init_TypeDef::ardyEnable
bool ardyEnable
Definition: em_ebi.h:337
BC_EBI_CTRL_EXTADDR_MASK
#define BC_EBI_CTRL_EXTADDR_MASK
Definition: bsp_dk_bcreg_3201.h:167
USART_Rx
uint8_t USART_Rx(USART_TypeDef *usart)
Receive one 4-8 bit frame, (or part of 10-16 bit frame).
Definition: em_usart.c:923
BC_MAGIC_VALUE
#define BC_MAGIC_VALUE
Definition: bsp_dk_bcreg_3200.h:92
BSP_ANALOG_DIFF
Definition: bsp.h:129
ebiModeD16A16ALE
Definition: em_ebi.h:95
BC_PERICON_SPI_SHIFT
#define BC_PERICON_SPI_SHIFT
Definition: bsp_dk_bcreg_3201.h:204
USART_InitSync_TypeDef::refFreq
uint32_t refFreq
Definition: em_usart.h:427
BSP_TFT
Definition: bsp.h:132
BC_PERICON_TRACE_SHIFT
#define BC_PERICON_TRACE_SHIFT
Definition: bsp_dk_bcreg_3201.h:197
EBI_Init_TypeDef::readHoldCycles
int readHoldCycles
Definition: em_ebi.h:357
em_device.h
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
EBI_Init_TypeDef::mode
EBI_Mode_TypeDef mode
Definition: em_ebi.h:317
cmuClock_EBI
Definition: em_cmu.h:728
BSP_I2S
Definition: bsp.h:124
cmuClock_GPIO
Definition: em_cmu.h:618
BC_DISPLAY_CTRL_RESET
#define BC_DISPLAY_CTRL_RESET
Definition: bsp_dk_bcreg_3201.h:160
EBI_Init_TypeDef::writeHoldCycles
int writeHoldCycles
Definition: em_ebi.h:371
BSP_ETH
Definition: bsp.h:123
em_usart.h
Universal synchronous/asynchronous receiver/transmitter (USART/UART) peripheral API.
BSP_InterruptEnable
int BSP_InterruptEnable(uint16_t flags)
Enable interrupts from board controller.
Definition: bsp_dk_3201.c:376
EBI_CS1
#define EBI_CS1
Definition: em_ebi.h:81
BSP_InterruptFlagsSet
int BSP_InterruptFlagsSet(uint16_t flags)
Set board controller interrupt flags.
Definition: bsp_dk_3201.c:419
EBI_Init_TypeDef::noIdle
bool noIdle
Definition: em_ebi.h:334
BSP_Display_BC
Definition: bsp.h:67
EBI_Init_TypeDef::location
EBI_Location_TypeDef location
Definition: em_ebi.h:382
BC_PERICON_ANALOG_DIFF_SHIFT
#define BC_PERICON_ANALOG_DIFF_SHIFT
Definition: bsp_dk_bcreg_3201.h:202
BSP_MICROSD
Definition: bsp.h:131
BC_PERICON_ANALOG_SE_SHIFT
#define BC_PERICON_ANALOG_SE_SHIFT
Definition: bsp_dk_bcreg_3201.h:203
EBI_Init_TypeDef::csLines
uint32_t csLines
Definition: em_ebi.h:343
BSP_STATUS_OK
#define BSP_STATUS_OK
Definition: bsp.h:45
BSP_RegisterRead
uint16_t BSP_RegisterRead(volatile uint16_t *addr)
Read from a board controller register.
Definition: bsp_dk_3201.c:687
EBI_BANK2
#define EBI_BANK2
Definition: em_ebi.h:77
BSP_InterruptDisable
int BSP_InterruptDisable(uint16_t flags)
Disable interrupts from board controller.
Definition: bsp_dk_3201.c:357
BC_ARB_CTRL_BC
#define BC_ARB_CTRL_BC
Definition: bsp_dk_bcreg_3201.h:171
BSP_INIT_DK_SPI
#define BSP_INIT_DK_SPI
Definition: bsp.h:52
EBI_CS2
#define EBI_CS2
Definition: em_ebi.h:82
BC_ARB_CTRL_SPI
#define BC_ARB_CTRL_SPI
Definition: bsp_dk_bcreg_3201.h:173
BC_PERICON_AUDIO_OUT_SHIFT
#define BC_PERICON_AUDIO_OUT_SHIFT
Definition: bsp_dk_bcreg_3201.h:201
BSP_I2C
Definition: bsp.h:122
ebiLocation1
Definition: em_ebi.h:218
BSP_Display_ResetAssert
Definition: bsp.h:70
EBI_BANK3
#define EBI_BANK3
Definition: em_ebi.h:78
em_ebi.h
External Bus Iterface (EBI) peripheral API.
ebiAHighA23
Definition: em_ebi.h:200
USART_ROUTE_TXPEN
#define USART_ROUTE_TXPEN
Definition: efm32gg_usart.h:1029
BSP_InterruptFlagsClear
int BSP_InterruptFlagsClear(uint16_t flags)
Clear board controller interrupt flags.
Definition: bsp_dk_3201.c:394
BSP_ANALOG_SE
Definition: bsp.h:130
GPIO_PinModeSet
void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out)
Set the mode for a GPIO pin.
Definition: em_gpio.c:269
BSP_Display_PowerDisable
Definition: bsp.h:69
BC_DISPLAY_CTRL_POWER_ENABLE
#define BC_DISPLAY_CTRL_POWER_ENABLE
Definition: bsp_dk_bcreg_3201.h:161
BSP_TOUCH
Definition: bsp.h:126
BSP_BusControl_TypeDef
BSP_BusControl_TypeDef
Definition: bsp.h:77
BSP_EbiExtendedAddressRange
int BSP_EbiExtendedAddressRange(bool enable)
Extended the EBI addressing range by enabling address lines A16-A22. On Gxxx_DK's this functions is a...
Definition: bsp_dk_3201.c:323
em_gpio.h
General Purpose IO (GPIO) peripheral API.
EBI_Init_TypeDef::readPrefetch
bool readPrefetch
Definition: em_ebi.h:362
EBI_BANK0
#define EBI_BANK0
Definition: em_ebi.h:75
gpioModeDisabled
Definition: em_gpio.h:424
BSP_Display_ModeGeneric
Definition: bsp.h:73
EBI_Init_TypeDef::writeSetupCycles
int writeSetupCycles
Definition: em_ebi.h:367
BSP_BusControl_EBI
Definition: bsp.h:83
EBI_Init_TypeDef::addrHoldCycles
int addrHoldCycles
Definition: em_ebi.h:347
BSP_BusControl_SPI
Definition: bsp.h:82
GPIO_PinOutSet
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out register to 1.
Definition: em_gpio.h:856
EBI_Init
void EBI_Init(const EBI_Init_TypeDef *ebiInit)
Configure and enable External Bus Interface.
Definition: em_ebi.c:64
EBI_CS3
#define EBI_CS3
Definition: em_ebi.h:83
BSP_AUDIO_OUT
Definition: bsp.h:128
BSP_AUDIO_IN
Definition: bsp.h:127
CMU_ClockEnable
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
Definition: em_cmu.c:1453
EBI_Init_TypeDef::aHigh
EBI_AHigh_TypeDef aHigh
Definition: em_ebi.h:380
BSP_DipSwitchGet
uint32_t BSP_DipSwitchGet(void)
Get status of the DIP switches on the DK.
Definition: bsp_dk_3201.c:238
BSP_STATUS_ILLEGAL_PARAM
#define BSP_STATUS_ILLEGAL_PARAM
Definition: bsp.h:46
BSP_RS232_UART
Definition: bsp.h:120
BC_PERICON_RS232_UART_SHIFT
#define BC_PERICON_RS232_UART_SHIFT
Definition: bsp_dk_bcreg_3201.h:192
BSP_RS232_SHUTDOWN
Definition: bsp.h:119
EBI_Init_TypeDef::addrHalfALE
bool addrHalfALE
Definition: em_ebi.h:350
BSP_Display_EBI
Definition: bsp.h:65
EBI_Init_TypeDef::writeStrobeCycles
int writeStrobeCycles
Definition: em_ebi.h:369
gpioModePushPull
Definition: em_gpio.h:432
BSP_InterruptFlagsGet
uint16_t BSP_InterruptFlagsGet(void)
Get board controller interrupt flags.
Definition: bsp_dk_3201.c:430
BC_DISPLAY_CTRL_MODE_GENERIC
#define BC_DISPLAY_CTRL_MODE_GENERIC
Definition: bsp_dk_bcreg_3201.h:164
BSP_Display_SPI
Definition: bsp.h:66
USART_Reset
void USART_Reset(USART_TypeDef *usart)
Reset USART/UART to same state as after a HW reset.
Definition: em_usart.c:856
BC_PERICON_I2S_ETH_SHIFT
#define BC_PERICON_I2S_ETH_SHIFT
Definition: bsp_dk_bcreg_3201.h:196
BSP_Peripheral_TypeDef
BSP_Peripheral_TypeDef
Definition: bsp.h:117
BSP_Init
int BSP_Init(uint32_t flags)
Initialize board support package functionality.
Definition: bsp_dk_3201.c:127
BSP_Display_TypeDef
BSP_Display_TypeDef
Definition: bsp.h:63
EBI_Init_TypeDef::alePolarity
EBI_Polarity_TypeDef alePolarity
Definition: em_ebi.h:321
ebiActiveHigh
Definition: em_ebi.h:110
BSP_Display_ResetRelease
Definition: bsp.h:71
BSP_Display_PowerEnable
Definition: bsp.h:68
BSP_PeripheralAccess
int BSP_PeripheralAccess(BSP_Peripheral_TypeDef perf, bool enable)
DK Peripheral Access Control Enable or disable access to on-board peripherals through switches and SP...
Definition: bsp_dk_3201.c:461
BC_PERICON_AUDIO_OUT_SEL_SHIFT
#define BC_PERICON_AUDIO_OUT_SEL_SHIFT
Definition: bsp_dk_bcreg_3201.h:200
cmuClock_HFPER
Definition: em_cmu.h:401
BC_PERICON_RS232_LEUART_SHIFT
#define BC_PERICON_RS232_LEUART_SHIFT
Definition: bsp_dk_bcreg_3201.h:193
bsp_dk_bcreg_3201.h
Board Control register definitions.
BSP_BusControl_Undefined
Definition: bsp.h:79
BSP_RegisterWrite
int BSP_RegisterWrite(volatile uint16_t *addr, uint16_t data)
Write to a board controller register.
Definition: bsp_dk_3201.c:704
EBI_Disable
void EBI_Disable(void)
Disable External Bus Interface.
Definition: em_ebi.c:280
BC_ARB_CTRL_EBI
#define BC_ARB_CTRL_EBI
Definition: bsp_dk_bcreg_3201.h:172
BSP_Disable
int BSP_Disable(void)
Deinitialize board support package functionality. Reverse actions performed by BSP_Init(). This function is a dummy on STK's.
Definition: bsp_dk_3201.c:97
BC_PERICON_TOUCH_SHIFT
#define BC_PERICON_TOUCH_SHIFT
Definition: bsp_dk_bcreg_3201.h:198
cmuClock_USART1
Definition: em_cmu.h:437
GPIO_PinOutClear
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out port register to 0.
Definition: em_gpio.h:811
BSP_BusControl_OFF
Definition: bsp.h:80
BSP_BusControlModeGet
BSP_BusControl_TypeDef BSP_BusControlModeGet(void)
Get current board controller bus decode logic configuration.
Definition: bsp_dk_3201.c:173
USART_ROUTE_RXPEN
#define USART_ROUTE_RXPEN
Definition: efm32gg_usart.h:1024
BSP_DisplayControl
int BSP_DisplayControl(BSP_Display_TypeDef option)
Configure display control.
Definition: bsp_dk_3201.c:251
ebiALowA16
Definition: em_ebi.h:153
USART_INITSYNC_DEFAULT
#define USART_INITSYNC_DEFAULT
Definition: em_usart.h:484
BC_SPI_DEMUX_SLAVE_DISPLAY
#define BC_SPI_DEMUX_SLAVE_DISPLAY
Definition: bsp_dk_bcreg_3201.h:210
BSP_Display_Mode8080
Definition: bsp.h:72
BSP_INIT_DK_EBI
#define BSP_INIT_DK_EBI
Definition: bsp.h:53
gpioModeInput
Definition: em_gpio.h:426
BC_PERICON_I2S_ETH_SEL_SHIFT
#define BC_PERICON_I2S_ETH_SEL_SHIFT
Definition: bsp_dk_bcreg_3201.h:195
EBI_Init_TypeDef::blEnable
bool blEnable
Definition: em_ebi.h:332
BC_REGISTER
#define BC_REGISTER
Definition: bsp_dk_bcreg_3201.h:125
EBI_INIT_DEFAULT
#define EBI_INIT_DEFAULT
Definition: em_ebi.h:390
EBI_Init_TypeDef
Definition: em_ebi.h:314
BSP_BusControl_DIRECT
Definition: bsp.h:81
BSP_JoystickGet
uint16_t BSP_JoystickGet(void)
Get status of joystick on the DK.
Definition: bsp_dk_3201.c:440
EBI_CS0
#define EBI_CS0
Definition: em_ebi.h:80
BSP_TRACE
Definition: bsp.h:125
EBI_Init_TypeDef::banks
uint32_t banks
Definition: em_ebi.h:341
USART_ROUTE_CLKPEN
#define USART_ROUTE_CLKPEN
Definition: efm32gg_usart.h:1039