26 #error "lwiopts.h for EFM32 are not included"
61 #define KSZ8851SNL_CHIP_ID 0x8870
62 #define CHIP_ID_MASK 0xFFF0
63 #define ONE_FRAME_THRES 0x0001
64 #define FD_PTR_AUTO_INC 0x4000
65 #define CLEAR_INT 0xFFFF
67 #define TX_MEM_AVAIL_MASK 0x1FFF
68 #define FRAME_ID_MASK 0x003F
69 #define CHECKSUM_VALID_FRAME_MASK 0x3C17
73 #define VALID_FRAME_MASK 0x8000
76 #define RX_BYTE_CNT_MASK 0x0FFF
77 #define LSB_MASK 0x00FF
78 #define MSB_POS 0x0008
79 #define TX_INT_on_COMPLETION 0x8000
80 #define WORD_SIZE 0x0004
81 #define EXTRA_SIZE 0x0008
82 #define BLOCKING_RECEIVE 0
83 #define WATERMARK_6KB 0x0600
84 #define WATERMARK_4KB 0x0400
86 #define HIGH_QMU_MAC_H 0x00
87 #define HIGH_QMU_MAC_L 0x0B
88 #define MID_QMU_MAC_H 0x57
89 #define BYTE_MASK 0x00FF
90 #define BYTE_SIZE 0x0008
95 #define TX_FLOW_CTRL_ICMP_CHECKSUM 0x0100
97 #define TX_FLOW_CTRL_TCP_CHECKSUM 0x0040
99 #define TX_FLOW_CTRL_IP_CHECKSUM 0x0020
101 #define TX_FLOW_CTRL_FLUSH_QUEUE 0x0010
103 #define TX_FLOW_CTRL_FLOW_ENABLE 0x0008
105 #define TX_FLOW_CTRL_PAD_ENABLE 0x0004
107 #define TX_FLOW_CTRL_CRC_ENABLE 0x0002
109 #define TX_FLOW_CTRL_ENABLE 0x0001
112 #define TX_FLOW_CTRL_CONFIG (TX_FLOW_CTRL_ICMP_CHECKSUM | \
113 TX_FLOW_CTRL_TCP_CHECKSUM | \
114 TX_FLOW_CTRL_IP_CHECKSUM | \
115 TX_FLOW_CTRL_FLOW_ENABLE | \
116 TX_FLOW_CTRL_PAD_ENABLE | \
117 TX_FLOW_CTRL_CRC_ENABLE)
121 #define TXQ_AUTO_ENQUEUE 0x0004
123 #define TXQ_MEM_AVAILABLE_INT 0x0002
125 #define TXQ_ENQUEUE 0x0001
130 #define RX_FLOW_CTRL_FLUSH_QUEUE 0x8000
132 #define RX_FLOW_CTRL_UDP_CHECKSUM 0x4000
134 #define RX_FLOW_CTRL_TCP_CHECKSUM 0x2000
136 #define RX_FLOW_CTRL_IP_CHECKSUM 0x1000
138 #define RX_FLOW_CTRL_MAC_FILTER 0x0800
140 #define RX_FLOW_CTRL_FLOW_ENENABLE 0x0400
142 #define RX_FLOW_CTRL_BAD_PACKET 0x0200
144 #define RX_FLOW_CTRL_BROADCAST_ENABLE 0x0080
146 #define RX_FLOW_CTRL_MULTICAST_ENABLE 0x0040
148 #define RX_FLOW_CTRL_UNICAST_ENABLE 0x0020
150 #define RX_FLOW_CTRL_PROMISCUOUS_MODE 0x0012
152 #define RX_FLOW_CTRL_RX_ALL 0x0010
154 #define RX_FLOW_CTRL_INVERSE_FILTER 0x0002
156 #define RX_FLOW_CTRL_RX_ENABLE 0x0001
159 #define RX_FLOW_CTRL1_CONFIG (RX_FLOW_CTRL_UDP_CHECKSUM | \
160 RX_FLOW_CTRL_TCP_CHECKSUM | \
161 RX_FLOW_CTRL_IP_CHECKSUM | \
162 RX_FLOW_CTRL_MAC_FILTER | \
163 RX_FLOW_CTRL_FLOW_ENENABLE | \
164 RX_FLOW_CTRL_BROADCAST_ENABLE | \
165 RX_FLOW_CTRL_UNICAST_ENABLE)
170 #define RX_FLOW_CTRL_BURST_LEN_MASK 0x00E0
172 #define RX_FLOW_CTRL_BURST_LEN_4 0x0000
174 #define RX_FLOW_CTRL_BURST_LEN_8 0x0020
176 #define RX_FLOW_CTRL_BURST_LEN_16 0x0040
178 #define RX_FLOW_CTRL_BURST_LEN_32 0x0060
180 #define RX_FLOW_CTRL_BURST_LEN_FRAME 0x0080
182 #define RX_FLOW_CTRL_IPV6_UDP_FRAG_PASS 0x0010
184 #define RX_FLOW_CTRL_IPV6_UDP_ZERO_PASS 0x0008
186 #define RX_FLOW_CTRL_UDP_LITE_CHECKSUM 0x0004
188 #define RX_FLOW_CTRL_ICMP_CHECKSUM 0x0002
190 #define RX_FLOW_CTRL_BLOCK_MAC 0x0001
193 #define RX_FLOW_CTRL2_CONFIG (RX_FLOW_CTRL_IPV6_UDP_FRAG_PASS | \
194 RX_FLOW_CTRL_UDP_LITE_CHECKSUM | \
195 RX_FLOW_CTRL_ICMP_CHECKSUM | \
196 RX_FLOW_CTRL_BURST_LEN_FRAME)
200 #define RXQ_ON_TIME_INT 0x1000
202 #define RXQ_ON_BYTE_CNT_INT 0x0800
204 #define RXQ_ON_FRAME_CNT_INT 0x0400
206 #define RXQ_TWOBYTE_OFFSET 0x0200
208 #define RXQ_EN_ON_TIME_INT 0x0080
210 #define RXQ_EN_ON_BYTE_CNT_INT 0x0040
212 #define RXQ_EN_ON_FRAME_CNT_INT 0x0020
214 #define RXQ_AUTO_DEQUEUE 0x0010
216 #define RXQ_START_DMA 0x0008
218 #define RXQ_RELEASE_ERROR_FRAME 0x0001
221 #define RXQ_CMD_CONFIG (RXQ_EN_ON_FRAME_CNT_INT | \
226 #define PORT1_AN_DONE 0x0040
228 #define PORT1_LINK_GOOD 0x0020
232 #define PORT1_LED_OFF 0x8000
234 #define PORT1_TX_DISABLE 0x4000
236 #define PORT1_AUTO_NEG_RESTART 0x2000
238 #define PORT1_POWER_DOWN 0x0800
240 #define PORT1_AUTO_MDIX_DISABLE 0x0400
242 #define PORT1_FORCE_MDIX 0x0200
244 #define PORT1_AUTO_NEG_ENABLE 0x0080
246 #define PORT1_FORCE_100_MBIT 0x0040
248 #define PORT1_FORCE_FULL_DUPLEX 0x0020
250 #define PORT1_AUTO_NEG_FLOW_CTRL 0x0010
252 #define PORT1_AUTO_NEG_100BTX_FD 0x0008
254 #define PORT1_AUTO_NEG_100BTX 0x0004
256 #define PORT1_AUTO_NEG_10BT_FD 0x0002
258 #define PORT1_AUTO_NEG_10BT 0x0001
261 #define PORT1_CONFIG (PORT1_AUTO_NEG_ENABLE | \
262 PORT1_FORCE_100_MBIT | \
263 PORT1_FORCE_FULL_DUPLEX | \
264 PORT1_AUTO_NEG_FLOW_CTRL | \
265 PORT1_AUTO_NEG_100BTX_FD | \
266 PORT1_AUTO_NEG_100BTX | \
267 PORT1_AUTO_NEG_10BT_FD | \
268 PORT1_AUTO_NEG_10BT )
272 #define QMU_MODULE_SOFT_RESET 0x0002
274 #define GLOBAL_SOFT_RESET 0x0001
277 #define PHY_RESET 0x0001
281 #define DIGITAL_LOOPBACK 0x4000
283 #define FORCE_100 0x2000
285 #define AUTO_NEG 0x1000
287 #define RESTART_AUTO_NEG 0x0200
289 #define FORCE_FULL_DUPLEX 0x0100
292 #define TX_MEMORY_WAIT_MS 500
295 #define FRAME_COUNT_THRESHOLD 1
298 #define MIB_MASK 0x1C00
299 #define MIB_RxByte 0x00
301 #define MIB_RxUndersizePkt 0x02
302 #define MIB_RxFragments 0x03
303 #define MIB_RxOversize 0x04
304 #define MIB_RxJabbers 0x05
305 #define MIB_RxSymbolError 0x06
306 #define MIB_RxCRCError 0x07
307 #define MIB_RxAlignmentError 0x08
308 #define MIB_RxControl8808Pkts 0x09
309 #define MIB_RxPausePkts 0x0A
310 #define MIB_RxBroadcast 0x0B
311 #define MIB_RxMulticast 0x0C
312 #define MIB_RxUnicast 0x0D
313 #define MIB_Rx64Octets 0x0E
314 #define MIB_Rx65to127Octets 0x0F
315 #define MIB_Rx128to255Octets 0x10
316 #define MIB_Rx256to511Octets 0x11
317 #define MIB_Rx512to1023Octets 0x12
318 #define MIB_Rx1024to1521Octets 0x13
319 #define MIB_Rx1522to2000Octets 0x14
320 #define MIB_TxByte 0x15
321 #define MIB_TxLateCollision 0x16
322 #define MIB_TxPausePkts 0x17
323 #define MIB_TxBroadcastPkts 0x18
324 #define MIB_TxMulticastPkts 0x19
325 #define MIB_TxUnicastPkts 0x1A
326 #define MIB_TxDeferred 0x1B
327 #define MIB_TxTotalCollision 0x1C
328 #define MIB_TxExcessiveCollision 0x1D
329 #define MIB_TxSingleCollision 0x1E
330 #define MIB_TxMultipleCollision 0x1F
333 #define READ_UNSAFE_REGISTERS 0
335 static uint16_t frameId = 0;
336 static uint8_t macAddress[6];
337 static uint16_t rxFrameCount;
338 static uint32_t interruptCnt = 0;
411 printf(
"####################### MIB COUNTER DUMP ########################\n");
415 printf(
"MIB_RxOversizeCnt = %lu\n", mibCounters.
RxOversizeCnt);
416 printf(
"MIB_RxJabbersCnt = %lu\n", mibCounters.
RxJabbersCnt);
418 printf(
"MIB_RxCRCErrorCnt = %lu\n", mibCounters.
RxCRCErrorCnt);
422 printf(
"MIB_RxUnicastCnt = %lu\n", mibCounters.
RxUnicastCnt);
423 printf(
"MIB_TxByteCnt = %lu\n", mibCounters.
TxByteCnt);
428 printf(
"MIB_TxDeferredCnt = %lu\n", mibCounters.
TxDeferredCnt);
430 printf(
"#################################################################\n");
439 printf(
"###################### ALL REGISTER DUMP ########################\n");
441 for (i = 0x00; i < 0xFF; i += 0x02)
443 if ((i % 8 == 0) && (i > 0))
450 printf(
"#################################################################\n");
459 printf(
"##################### SPECIAL REGISTER DUMP ######################\n");
469 #if (READ_UNSAFE_REGISTERS)
479 #if (READ_UNSAFE_REGISTERS)
486 printf(
"#################################################################\n");
498 if (interruptCnt == 0)
563 rxFrameCount = rxftr >>
MSB_POS;
744 uint16_t data, reqSize;
760 reqSize = length + 12;
762 LWIP_DEBUGF(NETIF_DEBUG, (
"KSZ8851SNL_LongTransmitInit: txmir =%hu reqSize = %hu \n", txmir, reqSize));
767 LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_LEVEL_WARNING, (
"Not enough TXQ Memory, available=%u required=%u\n", txmir, reqSize));
771 LWIP_DEBUGF(NETIF_DEBUG, (
"KSZ8851SNL_LongTransmitInit: Memory available > txmir =%hu reqSize = %hu \n", txmir, reqSize));
807 EFM_ASSERT(buffer != NULL);
827 uint8_t dummy[4] = {0x00};
832 padding = 4 - (length % 4);
883 uint16_t rxPacketLength;
884 uint16_t frameLength;
885 uint16_t bytesToRead;
887 EFM_ASSERT(buffer != NULL);
889 while (rxFrameCount > 0)
909 bytesToRead = 4 * ((rxPacketLength + 3) >> 2);
910 LWIP_DEBUGF(NETIF_DEBUG, (
"KSZ8851SNL_Receive: rxPacketLength=%u, bytesToRead=%u \n", rxPacketLength, bytesToRead));
911 if ((bytesToRead > length) || (rxPacketLength <= 4))
937 frameLength = rxPacketLength - 4;
958 EFM_ASSERT(macAddress != NULL);
966 for (i = 0; i < 3; i++)
968 macAddress[5 - i] = (
DEVINFO->UNIQUEL & (BYTE_MASK << i * BYTE_SIZE)) >> i *
BYTE_SIZE;
#define RX_FLOW_CTRL_RX_ENABLE
void KSZ8851SNL_Enable(void)
Enable RX and TX.
static uint32_t MIBCountersRead(uint16_t offset)
helper function for KSZ8851SNL_UpdateMIBCounters
#define KSZ8851SNL_CHIP_ID
static void ReleaseIncosistentFrame(void)
Release the current frame if it is inconsistent.
SPI interface API for KSZ8851SNL Ethernet controller.
Emlib peripheral API "assert" implementation.
static KSZ8851SLN_mib_t mibCounters
Copy of the current MIB counters values from the ksz8851snl. This is updated by calling KSZ8851SNL_MI...
void KSZ8851SNL_IntDisable(void)
disables the chip interrupts
void KSZ8851SNL_MacAddressGet(uint8_t *macAddress)
Get the MAC address of the current board.
#define MIB_TxMulticastPkts
void KSZ8851SNL_IntClear(uint16_t flags)
Clear interrupt flags.
#define CHECKSUM_VALID_FRAME_MASK
#define MIB_TxUnicastPkts
#define RXQ_RELEASE_ERROR_FRAME
uint32_t TxMulticastPktsCnt
void KSZ8851SNL_RxQueueReset(void)
Reset RxQueue.
void KSZ8851SNL_Init(void)
Initialize the registers of the ethernet controller.
#define TX_FLOW_CTRL_CONFIG
#define PORT1_AUTO_NEG_RESTART
void KSZ8851SNL_TxQueueReset(void)
Reset TxQueue.
void KSZ8851SNL_SPI_WriteFifo(int numBytes, const uint8_t *data)
Continue writing ethernet controller FIFO.
void KSZ8851SNL_AllRegistersDump(void)
Prints the value of the registers of the ethernet controller.
uint32_t RxUndersizePktCnt
#define MIB_RxUndersizePkt
#define MIB_RxSymbolError
#define RX_FLOW_CTRL2_CONFIG
uint32_t TxBroadcastPktsCnt
uint16_t KSZ8851SNL_SPI_ReadRegister(uint8_t reg)
Read ethernet controller register.
#define GLOBAL_SOFT_RESET
uint16_t KSZ8851SNL_PHYStatusGet(void)
Get the PHY status.
#define RX_FLOW_CTRL1_CONFIG
Driver for Micrel KSZ8851SNL Ethernet controller.
void KSZ8851SNL_FrameCounterSet(void)
FrameCounter.
uint32_t TxUnicastPktsCnt
bool KSZ8851SNL_TransmitBegin(uint16_t length)
Prepares for a transmission of an ethernet frame over the network.
uint16_t KSZ8851SNL_FrameCounterGet(void)
FrameCounter.
void KSZ8851SNL_SPI_WriteFifoEnd(void)
Stop read/write the ethernet controller FIFO.
void KSZ8851SNL_MIBCountersDump(void)
Dumps the Management Information Base Counters.
void KSZ8851SNL_RegistersDump(void)
Prints the value of the registers of the ethernet controller.
void KSZ8851SNL_MIBCountersUpdate(void)
Update the Management Information Base Counters.
void KSZ8851SNL_TransmitEnd(uint16_t length)
Ends a transmission of an ethernet frame to the ethernet controller.
uint16_t KSZ8851SNL_Receive(uint16_t length, uint8_t *buffer)
Performs the actual receive of a raw frame over the network.
#define TX_FLOW_CTRL_FLUSH_QUEUE
#define MIB_TxBroadcastPkts
#define TX_MEM_AVAIL_MASK
void KSZ8851SNL_SPI_ReadFifo(int numBytes, uint8_t *data)
Read data from the ethernet controller RX FIFO.
#define RX_FLOW_CTRL_FLUSH_QUEUE
uint32_t RxSymbolErrorCnt
#define MIB_TxTotalCollision
void KSZ8851SNL_Transmit(uint16_t length, const uint8_t *buffer)
Transmit a chunk of data to the ethernet controller. The chunk can be either a full ethernet frame or...
#define TX_FLOW_CTRL_ENABLE
uint16_t KSZ8851SNL_RXQCRGet(void)
Get RXQCR register.
void KSZ8851SNL_IntEnable(void)
enables the chip interrupts
uint32_t TxTotalCollisionCnt
void KSZ8851SNL_SPI_Init(void)
KSZ8851SNL_SPI_Init Initialize SPI interface to Ethernet controller.
void KSZ8851SNL_PMECRStatusClear(uint16_t flags)
Clear PMECR (Power Management Event Control Register) flags.
void KSZ8851SNL_SPI_WriteRegister(uint8_t reg, uint16_t value)
Write ethernet controller register.
#define KSZ8851SNL_INT_ENABLE_MASK
uint16_t KSZ8851SNL_IntGet(void)
Get interrupt flags.
The MIB (Management Information Base) Counters that the ksz8851snl device expose to the host...
void KSZ8851SNL_SPI_WriteFifoBegin(void)
Start writing to the ethernet controller FIFO.
#define FRAME_COUNT_THRESHOLD