72 #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY)
75 volatile uint32_t *reg;
77 rev = *(
volatile uint32_t *)(0x0FE081FC);
81 reg = (
volatile uint32_t *)0x400CA00C;
84 reg = (
volatile uint32_t *)0x400C6020;
85 *reg &= ~(0xE0000000UL);
91 reg = (
volatile uint32_t *)0x400C6020;
92 *reg &= ~(0x00001F80UL);
94 reg = (
volatile uint32_t *)0x400C8040;
96 reg = (
volatile uint32_t *)0x400C8044;
98 reg = (
volatile uint32_t *)0x400C8058;
100 reg = (
volatile uint32_t *)0x400C8060;
102 reg = (
volatile uint32_t *)0x400C8078;
107 if (chipRev.
major == 0x01)
111 if (chipRev.
minor == 00)
113 reg = (
volatile uint32_t *)0x400C8040;
120 if (chipRev.
minor <= 0x01)
122 reg = (
volatile uint32_t *)0x400C8044;
127 rev = *(
volatile uint32_t *)0x0FE081F0;
128 if (rev < 0x4C8ABA00)
133 reg = (
volatile uint32_t *)0x400C8044UL;
134 *reg |= (1 << 14 | 1 << 11);
137 cal = ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
140 cal |= ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
143 cal |= ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
146 cal |= ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
150 reg = (
volatile uint32_t *)0x40002034UL;
154 reg = (
volatile uint32_t *)(0x4000402CUL);
155 cal = *(
volatile uint32_t *)0x0FE081C8UL;
159 reg = (
volatile uint32_t *)0x400C8044UL;
160 *reg &= ~(1 << 14 | 1 << 11);
164 #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY)
175 if ((prodRev >= 16) && (chipRev.
minor >= 3))
178 *(
volatile uint32_t*)0x400C80C0 =
179 ( *(
volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
183 #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY)
192 *(
volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
194 *(
volatile uint32_t*)(0x400C80E4) &= ~(1 << 24);
198 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
207 const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
208 | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
210 & ~(_GPIO_P_CTRL_SLEWRATE_MASK
211 | _GPIO_P_CTRL_SLEWRATEALT_MASK);
223 clkEn =
CMU->HFBUSCLKEN0;
224 CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO;
227 for(port = 0; port <= GPIO_PORT_MAX; port++)
229 GPIO->P[port].CTRL = setVal | resetVal;
233 CMU->HFBUSCLKEN0 = clkEn;
240 CMU->HFXOSTARTUPCTRL =
241 (
CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
242 | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
245 if (chipRev.
major == 0x01)
248 *(
volatile uint32_t *)(
EMU_BASE + 0x164) |= 0x4;
252 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
259 *(
volatile uint32_t *)(
EMU_BASE + 0x190) = 0x0000ADE8UL;
260 *(
volatile uint32_t *)(
EMU_BASE + 0x198) |= (0x1 << 2);
261 *(
volatile uint32_t *)(
EMU_BASE + 0x190) = 0x0;
265 *(
volatile uint32_t *)(
EMU_BASE + 0x164) |= (0x1 << 13);
269 CMU->LFRCOCTRL = (
CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK)
270 | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
271 | CMU_LFRCOCTRL_ENVREF;
274 #if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84)
275 MSC->CTRL |= 0x1 << 8;
RAM and peripheral bit-field set and clear API.
void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
Get chip major/minor revision.
__STATIC_INLINE void CHIP_Init(void)
Chip initialization routine for revision errata workarounds. This function must be called immediately...
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
__STATIC_INLINE uint8_t SYSTEM_GetProdRev(void)
Get the production revision for this part.
General Purpose IO (GPIO) peripheral API.
#define _GPIO_P_CTRL_RESETVALUE