sl_iec60730.h

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/***************************************************************************/ 
#ifndef SL_IEC60730_H
#define SL_IEC60730_H
 
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
 
#include "sl_iec60730_config.h"
#include "sl_iec60730_toolchain.h"
#include "em_device.h"
#include "em_core.h"
#include "em_gpcrc.h"
#include SL_IEC60730_BOARD_HEADER
 
#define IE60730_LIBRARY_VERSION { 2, 0, 0 }
 
#ifdef DOXYGEN
#define SL_IEC60730_BOARD_HEADER
 
#else
#define IEC60370_CM4  0
#define IEC60370_CM33 1
#if defined(__CM4_REV)
#define IEC60370_CPU IEC60370_CM4
#elif defined(__CM33_REV)
#define IEC60370_CPU IEC60370_CM33
#else
#error "Unknown Core type!"
#endif
 
#endif /* DOXYGEN */
 
/**************************************************************************/ 
typedef struct {
  uint8_t major;    
  uint8_t minor;    
  uint8_t revision; 
} sl_iec60730_library_version_t;
 
extern const sl_iec60730_library_version_t SL_IEC60730_LIBRARY_VERSION;
 
typedef enum {
  SL_IEC60730_TEST_FAILED      = 0, 
  SL_IEC60730_TEST_PASSED      = 1, 
  SL_IEC60730_TEST_IN_PROGRESS = 2, 
} sl_iec60730_test_result_t;
 
typedef enum {
  SL_IEC60730_NO_FAILURE           = 0, 
  SL_IEC60730_TEST_VERIFY          = 1, 
  SL_IEC60730_WATCHDOG_POST_FAIL   = 2, 
  SL_IEC60730_VMC_FAIL             = 3, 
  SL_IEC60730_IMC_FAIL             = 4, 
  SL_IEC60730_CPU_REGISTERS_FAIL   = 5, 
  SL_IEC60730_CLOCK_FAIL           = 6, 
  SL_IEC60730_INTERRUPT_FAIL       = 7, 
  SL_IEC60730_PROGRAM_COUNTER_FAIL = 8, 
  SL_IEC60730_GPIO_FAIL            = 9, 
  SL_IEC60730_ANALOG_FAIL          = 10, 
  SL_IEC60730_CS0_FAIL             = 11, 
  SL_IEC60730_LESENSE0_FAIL        = 12, 
  SL_IEC60730_RADIO_FAIL           = 13, 
  SL_IEC60730_I2C0_FAIL            = 14, 
  SL_IEC60730_I2C1_FAIL            = 15, 
  SL_IEC60730_USART0_FAIL          = 16, 
  SL_IEC60730_USART1_FAIL          = 17, 
  SL_IEC60730_USART2_FAIL          = 18, 
  SL_IEC60730_USART3_FAIL          = 19, 
  SL_IEC60730_LEUART0_FAIL         = 20, 
  SL_IEC60730_EUART0_FAIL          = 21, 
  SL_IEC60730_PDM0_FAIL            = 22, 
  SL_IEC60730_OEM_FAIL_1           = 23, 
  SL_IEC60730_OEM_FAIL_2           = 24, 
  SL_IEC60730_OEM_FAIL_3           = 25, 
  SL_IEC60730_OEM_FAIL_4           = 26, 
  SL_IEC60730_SAFETY_CHECK_FAIL    = 0XFF, 
} sl_iec60730_test_failure_t;
 
#ifndef UNUSED_VAR
#define UNUSED_VAR(x) (void) (x)
#endif /* UNUSED_VAR */
 
#ifndef __CONCAT
#define __CONCAT(x, y) x##y
#endif
 
#define CONCAT(x, y) __CONCAT(x, y)
 
#define STR(x)  #x
#define XSTR(x) STR(x)
 
#ifndef LABEL_DEF
#define LABEL_DEF(NAME) LB_ASM volatile(LB_XSTR(NAME))
#endif /* LABEL_DEF */
 
#ifdef DOXYGEN
#define __no_init
#else // !DOXYGEN
#ifndef __no_init
#define __no_init
#endif /* __no_init */
#endif // DOXYGEN
 
#define DEC_CLASSB_VARS(vartype, name) \
  __no_init vartype name __CLASSB_RAM; \
  __no_init vartype CONCAT(name, _inv) __CLASSB_RAM
 
#define EXTERN_DEC_CLASSB_VARS(vartype, name) \
  extern __no_init vartype name __CLASSB_RAM; \
  extern __no_init vartype CONCAT(name, _inv) __CLASSB_RAM
 
#define sl_static_dec_classb_vars(vartype, name) \
  static __no_init vartype name __CLASSB_RAM;    \
  static __no_init vartype CONCAT(name, _inv) __CLASSB_RAM
 
#define INV_CLASSB_VAR(vartype, name) \
  CONCAT(name, _inv) = (vartype) (~(vartype) name)
 
#define INV_CLASSB_PVAR(vartype, name) \
  CONCAT(name, _inv) = (vartype *) (~(vartype) name)
 
#if ((defined UNIT_TEST_IEC60730_VARIABLE_MEMORY_ENABLE) || defined (UNIT_TEST_IEC60730_INVARIABLE_MEMORY_ENABLE))
#define CHECK_INTEGRITY(vartype, x)  unit_test_mock_check_integrity()
#else
#define CHECK_INTEGRITY(vartype, x) \
  ((vartype) - 1 == ((vartype) x ^ (vartype) CONCAT(x, _inv)))
#endif // (UNIT_TEST_IEC60730_VARIABLE_MEMORY_ENABLE || UNIT_TEST_IEC60730_INVARIABLE_MEMORY_ENABLE)
 
/**************************************************************************/ 
#ifdef DOXYGEN
#define sl_iec60730_crc_t
 
#define SL_IEC60730_INVAR_BLOCKS_PER_BIST
 
#else // !DOXYGEN
 
#if (SL_IEC60730_USE_CRC_32_ENABLE == 1)
typedef uint32_t sl_iec60730_crc_t;
#else /* !SL_IEC60730_USE_CRC_32_ENABLE */
typedef uint16_t sl_iec60730_crc_t;
#endif /* SL_IEC60730_USE_CRC_32_ENABLE */
 
#endif // DOXYGEN
 
extern sl_iec60730_crc_t check_sum;
 
#define SL_IEC60730_ROM_SIZE          ((uint32_t) SL_IEC60730_ROM_END - (uint32_t) SL_IEC60730_ROM_START)
 
#define STEPS_NUMBER                  ((uint32_t) SL_IEC60730_ROM_SIZE / SL_IEC60730_FLASH_BLOCK)
 
#define SL_IEC60730_ROM_SIZE_INWORDS  ((uint32_t) SL_IEC60730_ROM_SIZE / 4U)
 
#define SL_IEC60730_FLASH_BLOCK_WORDS ((uint32_t) (SL_IEC60730_ROM_SIZE_INWORDS / STEPS_NUMBER))
 
#define SL_IEC60730_ROM_SIZE_TEST(start, end) \
  ((uint32_t) end - (uint32_t) start)
 
#define STEPS_NUMBER_TEST(start, end) \
  ((uint32_t) SL_IEC60730_ROM_SIZE_TEST(start, end) / SL_IEC60730_FLASH_BLOCK)
 
#define SL_IEC60730_ROM_SIZE_INWORDS_TEST(start, end)  ((uint32_t) SL_IEC60730_ROM_SIZE_TEST(start, end) / 4U)
 
#define SL_IEC60730_FLASH_BLOCK_WORDS_TEST(start, end) ((uint32_t) (SL_IEC60730_ROM_SIZE_INWORDS_TEST(start, end) / STEPS_NUMBER_TEST(start, end)))
 
#ifndef SL_IEC60730_REF_CRC
#define SL_IEC60730_REF_CRC (check_sum)
#endif
 
/**************************************************************************/ 
#define BLOCKSIZE         (4)
 
#define RT_BLOCK_OVERLAP  (1)
 
#define RT_BLOCKSIZE      (BLOCKSIZE + (RT_BLOCK_OVERLAP << 1))
 
#ifndef BACKGROUND
#define BACKGROUND        ((uint32_t) 0x00000000uL)
#endif
 
/**************************************************************************/ 
/**************************************************************************/ 
void sl_iec60730_safe_state(sl_iec60730_test_failure_t failure);
/**************************************************************************/ 
extern uint16_t sl_iec60730_program_counter_check;
 
#define IEC60730_VMC_COMPLETE         (1 << 0)
#define IEC60730_IMC_COMPLETE         (1 << 1)
#define IEC60730_CPU_CLOCKS_COMPLETE  (1 << 2)
#define IEC60730_CPU_REGS_COMPLETE    (1 << 3)
#define IEC60730_INTERRUPT_COMPLETE   (1 << 4)
#define IEC60730_GPIO_COMPLETE        (1 << 5)
#define IEC60730_ANALOG_COMPLETE      (1 << 6)
#define IEC60730_COMMS_COMPLETE       (1 << 7)
#define IEC60730_OEM0_COMPLETE        (1 << 8)
#define IEC60730_OEM1_COMPLETE        (1 << 9)
#define IEC60730_OEM2_COMPLETE        (1 << 10)
#define IEC60730_OEM3_COMPLETE        (1 << 11)
#define IEC60730_OEM4_COMPLETE        (1 << 12)
#define IEC60730_OEM5_COMPLETE        (1 << 13)
#define IEC60730_OEM6_COMPLETE        (1 << 14)
#define IEC60730_OEM7_COMPLETE        (1 << 15)
#define IEC60730_ALL_COMPLETE_BITS                                            \
  (IEC60730_VMC_COMPLETE | IEC60730_IMC_COMPLETE                              \
   | IEC60730_CPU_CLOCKS_COMPLETE | IEC60730_CPU_REGS_COMPLETE                \
   | IEC60730_INTERRUPT_COMPLETE | IEC60730_GPIO_COMPLETE                     \
   | IEC60730_ANALOG_COMPLETE | IEC60730_COMMS_COMPLETE                       \
   | IEC60730_OEM0_COMPLETE | IEC60730_OEM1_COMPLETE | IEC60730_OEM2_COMPLETE \
   | IEC60730_OEM3_COMPLETE | IEC60730_OEM4_COMPLETE | IEC60730_OEM5_COMPLETE \
   | IEC60730_OEM6_COMPLETE | IEC60730_OEM7_COMPLETE)
 
/**************************************************************************/ 
/**************************************************************************/ 
void sl_iec60730_post(void);
/**************************************************************************/ 
typedef struct {
  uint32_t error;
  uint8_t number_error;
} sl_iec60730_safety_check_t;
 
/**************************************************************************/ 
void sl_iec60730_safety_check_error_occur(sl_iec60730_test_failure_t failure);
 
/**************************************************************************/ 
void sl_iec60730_safety_check_reset_error(void);
 
/**************************************************************************/ 
sl_iec60730_safety_check_t* sl_iec60730_safety_check_get_error(void);
 
/**************************************************************************/ 
void sl_iec60730_bist(void);
/**************************************************************************/ 
/**************************************************************************/ 
void sl_iec60730_restart_watchdogs(void);
 
/**************************************************************************/ 
typedef enum {
  SL_IEC60730_TIMER_TEST_DISABLE = 0, 
  SL_IEC60730_TIMER_TEST_ENABLE  = 1, 
} sl_iec60730_timer_test_control_t;
 
 
/**************************************************************************/ 
void sl_iec60730_sys_clock_count_tick(void);
 
/**************************************************************************/ 
void sl_iec60730_test_clock_tick(void);
 
/**************************************************************************/ 
void sl_iec60730_sys_clock_count_reset(void);
 
/**************************************************************************/ 
#define IEC60730_MAX_IRQ_CHECK          32
 
typedef struct {
  SL_IEC60730_IRQ_TYPE_VARIABLE
    min;   
  SL_IEC60730_IRQ_TYPE_VARIABLE
    max;   
} sl_iec60730_irq_execution_bounds_t;
 
// registered to check.
typedef struct {
  uint32_t irq_fail;
  uint8_t num_irq_fail;
} sl_iec60730_irq_fail_t;
 
typedef struct {
  volatile SL_IEC60730_IRQ_TYPE_VARIABLE* irq_count;
  const sl_iec60730_irq_execution_bounds_t* irq_bounds;
  uint8_t size;
}sl_iec60730_irq_cfg_t;
/**************************************************************************/ 
#define SL_IEC60370_ENTER_ATOMIC()  CORE_ENTER_ATOMIC()
#define SL_IEC60370_EXIT_ATOMIC()   CORE_EXIT_ATOMIC()
#define SL_IEC60370_DECLARE_IRQ_STATE CORE_DECLARE_IRQ_STATE;
 
#define SL_IEC60730_IMC_POST_ENTER_ATOMIC() \
  CORE_DECLARE_IRQ_STATE;                   \
  CORE_ENTER_ATOMIC()
 
#define SL_IEC60730_IMC_POST_EXIT_ATOMIC() CORE_EXIT_ATOMIC()
 
#define SL_IEC60730_IMC_BIST_ENTER_ATOMIC() \
  CORE_DECLARE_IRQ_STATE;                   \
  CORE_ENTER_ATOMIC()
 
#define SL_IEC60730_IMC_BIST_EXIT_ATOMIC() CORE_EXIT_ATOMIC()
 
#define SL_IEC60730_CRC_INIT(crc, init)               GPCRC_Init(crc, init)
#define SL_IEC60730_CRC_RESET(crc)                    GPCRC_Reset(crc)
#define SL_IEC60730_CRC_START(crc)                    GPCRC_Start(crc)
#define SL_IEC60730_CRC_INPUTU32(crc, d)              GPCRC_InputU32(crc, d)
#define SL_IEC60730_CRC_INPUTU16(crc, d)              GPCRC_InputU16(crc, d)
#define SL_IEC60730_CRC_INPUTU8(crc, d)               GPCRC_InputU8(crc, d)
#define SL_IEC60730_CRC_DATA_READ(crc)                GPCRC_DataRead(crc)
#define SL_IEC60730_CRC_DATA_READ_BIT_REVERSED(crc)   GPCRC_DataReadBitReversed(crc)
#define SL_IEC60730_CRC_DATA_READ_BYTE_REVERSED(crc)  GPCRC_DataReadByteReversed(crc)
 
// CRC
typedef GPCRC_TypeDef  sl_iec60730_crc_typedef;
typedef GPCRC_Init_TypeDef sl_iec60730_crc_init_typedef;
 
typedef uint8_t sl_iec60730_read_type_t;
enum {
  SL_IEC60730_IMC_DATA_READ = 0, 
  SL_IEC60730_IMC_DATA_READ_BIT_REVERSED =
    1,   
  SL_IEC60730_IMC_DATA_READ_BYTE_REVERSED =
    2,   
};
 
typedef struct {
  sl_iec60730_crc_typedef *gpcrc; 
} sl_iec60730_imc_params_t;
 
typedef struct {
#if (SL_IEC60730_CRC_USE_SW_ENABLE == 0)
  sl_iec60730_imc_params_t hal;       
  sl_iec60730_crc_init_typedef init; 
  sl_iec60730_read_type_t readType;   
#endif /* SL_IEC60730_CRC_USE_SW_ENABLE */
  sl_iec60730_crc_t xorOut;          
} sl_iec60730_update_crc_params_t;
 
typedef struct {
  uint32_t *start; 
  uint32_t *end;   
} sl_iec60730_imc_test_region_t;
 
typedef struct {
  const sl_iec60730_imc_test_region_t *region;
  uint8_t number_of_test_regions; 
} sl_iec60730_imc_test_multiple_regions_t;
 
#ifdef DOXYGEN
#define SL_IEC60730_DEFAULT_GPRC
#else
#ifndef SL_IEC60730_DEFAULT_GPRC
#if (_SILICON_LABS_32B_SERIES == 2)
#if ((defined SL_IEC60730_NON_SECURE_ENABLE) || (!defined(SL_TRUSTZONE_SECURE)))
#define SL_IEC60730_DEFAULT_GPRC GPCRC_NS
#else
#define SL_IEC60730_DEFAULT_GPRC GPCRC
#endif
#else // (_SILICON_LABS_32B_SERIES == 2)
#define SL_IEC60730_DEFAULT_GPRC GPCRC
#endif // (_SILICON_LABS_32B_SERIES == 2)
#endif // !SL_IEC60730_DEFAULT_GPRC
#endif // DOXYGEN
 
#define SL_IEC60730_IMC_CRC_BUFFER_SAMPLE_TEST "123456789"
 
#ifdef DOXYGEN
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE
 
#define SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT
 
#define SL_IEC60730_IMC_CRC_BUFFER_SAMPLE_RESULT
 
#define SL_IEC60730_IMC_CRC_BUFFER_UPDATE_DEFAULT
 
#else
 
#if (SL_IEC60730_CRC_USE_SW_ENABLE == 1)
#if (SL_IEC60730_USE_CRC_32_ENABLE == 1)
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE       SL_IEC60730_IMC_INIT_VALUE
#define SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT       (0xFFFFFFFFuL)
#define SL_IEC60730_IMC_CRC_BUFFER_SAMPLE_RESULT    (0xCBF43926)
#define SL_IEC60730_IMC_CRC_BUFFER_UPDATE_DEFAULT   { SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT }
#else /* !SL_IEC60730_USE_CRC_32_ENABLE  */
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE       SL_IEC60730_IMC_INIT_VALUE
#define SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT       (0x0000)
#define SL_IEC60730_IMC_CRC_BUFFER_SAMPLE_RESULT    (0x31C3)
#define SL_IEC60730_IMC_CRC_BUFFER_UPDATE_DEFAULT   { SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT }
#endif /* SL_IEC60730_USE_CRC_32_ENABLE  */
#else /* !SL_IEC60730_CRC_USE_SW_ENABLE */
#if (SL_IEC60730_USE_CRC_32_ENABLE == 1)
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE       SL_IEC60730_IMC_INIT_VALUE
#define SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT       (0xFFFFFFFFuL)
#define SL_IEC60730_IMC_CRC_BUFFER_SAMPLE_RESULT    (0xCBF43926)
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_DEFAULT \
  {                                             \
    0x04C11DB7UL,                               \
    SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE,      \
    false,                                      \
    false,                                      \
    false,                                      \
    false,                                      \
    true,                                       \
  }
 
#define SL_IEC60730_IMC_CRC_BUFFER_UPDATE_DEFAULT \
  { { SL_IEC60730_DEFAULT_GPRC },                 \
    SL_IEC60730_IMC_CRC_BUFFER_INIT_DEFAULT,      \
    SL_IEC60730_IMC_DATA_READ,                    \
    SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT }
#else /* !SL_IEC60730_USE_CRC_32_ENABLE  */
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE       SL_IEC60730_IMC_INIT_VALUE
#define SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT       (0x0000)
#define SL_IEC60730_IMC_CRC_BUFFER_SAMPLE_RESULT    (0x31C3)
#define SL_IEC60730_IMC_CRC_BUFFER_INIT_DEFAULT \
  {                                             \
    0x1021UL,                                   \
    SL_IEC60730_IMC_CRC_BUFFER_INIT_VALUE,      \
    false,                                      \
    true,                                       \
    false,                                      \
    false,                                      \
    true,                                       \
  }
#define SL_IEC60730_IMC_CRC_BUFFER_UPDATE_DEFAULT \
  { { SL_IEC60730_DEFAULT_GPRC },                 \
    SL_IEC60730_IMC_CRC_BUFFER_INIT_DEFAULT,      \
    SL_IEC60730_IMC_DATA_READ_BIT_REVERSED,       \
    SL_IEC60730_IMC_CRC_BUFFER_XOR_OUTPUT }
#endif /* SL_IEC60730_USE_CRC_32_ENABLE  */
#endif /* SL_IEC60730_CRC_USE_SW_ENABLE */
 
#endif // DOXYGEN
 
/**************************************************************************/ 
void sl_iec60730_imc_init(sl_iec60730_imc_params_t *params, sl_iec60730_imc_test_multiple_regions_t *test_config);
 
/**************************************************************************/ 
sl_iec60730_test_result_t
sl_iec60730_update_crc_with_data_buffer(sl_iec60730_update_crc_params_t *params,
                                        sl_iec60730_crc_t *crc,
                                        uint8_t *buffer,
                                        uint32_t size);
 
/**************************************************************************/ 
#define SL_IEC60730_VMC_POST_ENTER_CRITICAL() \
  CORE_DECLARE_IRQ_STATE;                     \
  CORE_ENTER_CRITICAL()
 
#define SL_IEC60730_VMC_POST_EXIT_CRITICAL()  CORE_EXIT_CRITICAL()
 
#define SL_IEC60730_VMC_BIST_ENTER_CRITICAL() \
  CORE_DECLARE_IRQ_STATE;                     \
  CORE_ENTER_CRITICAL()
 
#define SL_IEC60730_VMC_BIST_EXIT_CRITICAL()  CORE_EXIT_CRITICAL()
 
typedef struct {
  uint32_t *start; 
  uint32_t *end;   
} sl_iec60730_vmc_test_region_t;
 
typedef struct {
  const sl_iec60730_vmc_test_region_t *region;
  uint8_t number_of_test_regions; 
} sl_iec60730_vmc_test_multiple_regions_t;
 
/**************************************************************************/ 
void sl_iec60730_vmc_init(sl_iec60730_vmc_test_multiple_regions_t *test_config);
 
#if (_SILICON_LABS_32B_SERIES == 2)
// Write to backup ram module
// buram_inst: Pointer to BURAM instance
// idx: BURAM Reg index
// val: write value
#define SL_IEC60730_BURAM_WRITE(buram_inst, idx, val) \
  do {                                                \
    buram_inst->RET[idx].REG = val;                   \
  } while (0)
 
// Read from backup ram module
// buram_inst: Pointer to BURAM instance
// idx: BURAM Reg index
#define SL_IEC60730_BURAM_READ(buram_inst, idx) (buram_inst->RET[idx].REG)
#endif
 
#ifdef __cplusplus
}
#endif /* __cplusplus */
 
#endif /* SL_IEC60730_H */