EZR32WG_DMA_BitFields

Detailed Description

Macros
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   0x00000100UL
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT   0
#define	_DMA_ALTCTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_ALTCTRLBASE_RESETVALUE   0x00000100UL
#define	_DMA_CH_CTRL_MASK   0x003F000FUL
#define	_DMA_CH_CTRL_RESETVALUE   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_ADC0SCAN   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_ADC0SINGLE   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_AESDATARD   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_AESDATAWR   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_AESKEYWR   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_AESXORDATAWR   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_DAC0CH0   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_DAC0CH1   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_I2C0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_I2C1TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_MASK   0xFUL
#define	_DMA_CH_CTRL_SIGSEL_MSCWDATA   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_SHIFT   0
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER3CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER3CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER3CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER3UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_UART0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_UART0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_UART1RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_UART1TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   0x00000004UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USART2RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT   0x00000004UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USARTRF0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SOURCESEL_ADC0   0x00000008UL
#define	_DMA_CH_CTRL_SOURCESEL_AES   0x00000031UL
#define	_DMA_CH_CTRL_SOURCESEL_DAC0   0x0000000AUL
#define	_DMA_CH_CTRL_SOURCESEL_I2C0   0x00000014UL
#define	_DMA_CH_CTRL_SOURCESEL_I2C1   0x00000015UL
#define	_DMA_CH_CTRL_SOURCESEL_LESENSE   0x00000032UL
#define	_DMA_CH_CTRL_SOURCESEL_LEUART0   0x00000010UL
#define	_DMA_CH_CTRL_SOURCESEL_LEUART1   0x00000011UL
#define	_DMA_CH_CTRL_SOURCESEL_MASK   0x3F0000UL
#define	_DMA_CH_CTRL_SOURCESEL_MSC   0x00000030UL
#define	_DMA_CH_CTRL_SOURCESEL_NONE   0x00000000UL
#define	_DMA_CH_CTRL_SOURCESEL_SHIFT   16
#define	_DMA_CH_CTRL_SOURCESEL_TIMER0   0x00000018UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER1   0x00000019UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER2   0x0000001AUL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER3   0x0000001BUL
#define	_DMA_CH_CTRL_SOURCESEL_UART0   0x0000002CUL
#define	_DMA_CH_CTRL_SOURCESEL_UART1   0x0000002DUL
#define	_DMA_CH_CTRL_SOURCESEL_USART1   0x0000000DUL
#define	_DMA_CH_CTRL_SOURCESEL_USART2   0x0000000EUL
#define	_DMA_CH_CTRL_SOURCESEL_USARTRF0   0x0000000CUL
#define	_DMA_CHALTC_CH0ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH0ALTC_MASK   0x1UL
#define	_DMA_CHALTC_CH0ALTC_SHIFT   0
#define	_DMA_CHALTC_CH10ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH10ALTC_MASK   0x400UL
#define	_DMA_CHALTC_CH10ALTC_SHIFT   10
#define	_DMA_CHALTC_CH11ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH11ALTC_MASK   0x800UL
#define	_DMA_CHALTC_CH11ALTC_SHIFT   11
#define	_DMA_CHALTC_CH1ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH1ALTC_MASK   0x2UL
#define	_DMA_CHALTC_CH1ALTC_SHIFT   1
#define	_DMA_CHALTC_CH2ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH2ALTC_MASK   0x4UL
#define	_DMA_CHALTC_CH2ALTC_SHIFT   2
#define	_DMA_CHALTC_CH3ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH3ALTC_MASK   0x8UL
#define	_DMA_CHALTC_CH3ALTC_SHIFT   3
#define	_DMA_CHALTC_CH4ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH4ALTC_MASK   0x10UL
#define	_DMA_CHALTC_CH4ALTC_SHIFT   4
#define	_DMA_CHALTC_CH5ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH5ALTC_MASK   0x20UL
#define	_DMA_CHALTC_CH5ALTC_SHIFT   5
#define	_DMA_CHALTC_CH6ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH6ALTC_MASK   0x40UL
#define	_DMA_CHALTC_CH6ALTC_SHIFT   6
#define	_DMA_CHALTC_CH7ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH7ALTC_MASK   0x80UL
#define	_DMA_CHALTC_CH7ALTC_SHIFT   7
#define	_DMA_CHALTC_CH8ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH8ALTC_MASK   0x100UL
#define	_DMA_CHALTC_CH8ALTC_SHIFT   8
#define	_DMA_CHALTC_CH9ALTC_DEFAULT   0x00000000UL
#define	_DMA_CHALTC_CH9ALTC_MASK   0x200UL
#define	_DMA_CHALTC_CH9ALTC_SHIFT   9
#define	_DMA_CHALTC_MASK   0x00000FFFUL
#define	_DMA_CHALTC_RESETVALUE   0x00000000UL
#define	_DMA_CHALTS_CH0ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH0ALTS_MASK   0x1UL
#define	_DMA_CHALTS_CH0ALTS_SHIFT   0
#define	_DMA_CHALTS_CH10ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH10ALTS_MASK   0x400UL
#define	_DMA_CHALTS_CH10ALTS_SHIFT   10
#define	_DMA_CHALTS_CH11ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH11ALTS_MASK   0x800UL
#define	_DMA_CHALTS_CH11ALTS_SHIFT   11
#define	_DMA_CHALTS_CH1ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH1ALTS_MASK   0x2UL
#define	_DMA_CHALTS_CH1ALTS_SHIFT   1
#define	_DMA_CHALTS_CH2ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH2ALTS_MASK   0x4UL
#define	_DMA_CHALTS_CH2ALTS_SHIFT   2
#define	_DMA_CHALTS_CH3ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH3ALTS_MASK   0x8UL
#define	_DMA_CHALTS_CH3ALTS_SHIFT   3
#define	_DMA_CHALTS_CH4ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH4ALTS_MASK   0x10UL
#define	_DMA_CHALTS_CH4ALTS_SHIFT   4
#define	_DMA_CHALTS_CH5ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH5ALTS_MASK   0x20UL
#define	_DMA_CHALTS_CH5ALTS_SHIFT   5
#define	_DMA_CHALTS_CH6ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH6ALTS_MASK   0x40UL
#define	_DMA_CHALTS_CH6ALTS_SHIFT   6
#define	_DMA_CHALTS_CH7ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH7ALTS_MASK   0x80UL
#define	_DMA_CHALTS_CH7ALTS_SHIFT   7
#define	_DMA_CHALTS_CH8ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH8ALTS_MASK   0x100UL
#define	_DMA_CHALTS_CH8ALTS_SHIFT   8
#define	_DMA_CHALTS_CH9ALTS_DEFAULT   0x00000000UL
#define	_DMA_CHALTS_CH9ALTS_MASK   0x200UL
#define	_DMA_CHALTS_CH9ALTS_SHIFT   9
#define	_DMA_CHALTS_MASK   0x00000FFFUL
#define	_DMA_CHALTS_RESETVALUE   0x00000000UL
#define	_DMA_CHENC_CH0ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH0ENC_MASK   0x1UL
#define	_DMA_CHENC_CH0ENC_SHIFT   0
#define	_DMA_CHENC_CH10ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH10ENC_MASK   0x400UL
#define	_DMA_CHENC_CH10ENC_SHIFT   10
#define	_DMA_CHENC_CH11ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH11ENC_MASK   0x800UL
#define	_DMA_CHENC_CH11ENC_SHIFT   11
#define	_DMA_CHENC_CH1ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH1ENC_MASK   0x2UL
#define	_DMA_CHENC_CH1ENC_SHIFT   1
#define	_DMA_CHENC_CH2ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH2ENC_MASK   0x4UL
#define	_DMA_CHENC_CH2ENC_SHIFT   2
#define	_DMA_CHENC_CH3ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH3ENC_MASK   0x8UL
#define	_DMA_CHENC_CH3ENC_SHIFT   3
#define	_DMA_CHENC_CH4ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH4ENC_MASK   0x10UL
#define	_DMA_CHENC_CH4ENC_SHIFT   4
#define	_DMA_CHENC_CH5ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH5ENC_MASK   0x20UL
#define	_DMA_CHENC_CH5ENC_SHIFT   5
#define	_DMA_CHENC_CH6ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH6ENC_MASK   0x40UL
#define	_DMA_CHENC_CH6ENC_SHIFT   6
#define	_DMA_CHENC_CH7ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH7ENC_MASK   0x80UL
#define	_DMA_CHENC_CH7ENC_SHIFT   7
#define	_DMA_CHENC_CH8ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH8ENC_MASK   0x100UL
#define	_DMA_CHENC_CH8ENC_SHIFT   8
#define	_DMA_CHENC_CH9ENC_DEFAULT   0x00000000UL
#define	_DMA_CHENC_CH9ENC_MASK   0x200UL
#define	_DMA_CHENC_CH9ENC_SHIFT   9
#define	_DMA_CHENC_MASK   0x00000FFFUL
#define	_DMA_CHENC_RESETVALUE   0x00000000UL
#define	_DMA_CHENS_CH0ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH0ENS_MASK   0x1UL
#define	_DMA_CHENS_CH0ENS_SHIFT   0
#define	_DMA_CHENS_CH10ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH10ENS_MASK   0x400UL
#define	_DMA_CHENS_CH10ENS_SHIFT   10
#define	_DMA_CHENS_CH11ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH11ENS_MASK   0x800UL
#define	_DMA_CHENS_CH11ENS_SHIFT   11
#define	_DMA_CHENS_CH1ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH1ENS_MASK   0x2UL
#define	_DMA_CHENS_CH1ENS_SHIFT   1
#define	_DMA_CHENS_CH2ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH2ENS_MASK   0x4UL
#define	_DMA_CHENS_CH2ENS_SHIFT   2
#define	_DMA_CHENS_CH3ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH3ENS_MASK   0x8UL
#define	_DMA_CHENS_CH3ENS_SHIFT   3
#define	_DMA_CHENS_CH4ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH4ENS_MASK   0x10UL
#define	_DMA_CHENS_CH4ENS_SHIFT   4
#define	_DMA_CHENS_CH5ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH5ENS_MASK   0x20UL
#define	_DMA_CHENS_CH5ENS_SHIFT   5
#define	_DMA_CHENS_CH6ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH6ENS_MASK   0x40UL
#define	_DMA_CHENS_CH6ENS_SHIFT   6
#define	_DMA_CHENS_CH7ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH7ENS_MASK   0x80UL
#define	_DMA_CHENS_CH7ENS_SHIFT   7
#define	_DMA_CHENS_CH8ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH8ENS_MASK   0x100UL
#define	_DMA_CHENS_CH8ENS_SHIFT   8
#define	_DMA_CHENS_CH9ENS_DEFAULT   0x00000000UL
#define	_DMA_CHENS_CH9ENS_MASK   0x200UL
#define	_DMA_CHENS_CH9ENS_SHIFT   9
#define	_DMA_CHENS_MASK   0x00000FFFUL
#define	_DMA_CHENS_RESETVALUE   0x00000000UL
#define	_DMA_CHPRIC_CH0PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH0PRIC_MASK   0x1UL
#define	_DMA_CHPRIC_CH0PRIC_SHIFT   0
#define	_DMA_CHPRIC_CH10PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH10PRIC_MASK   0x400UL
#define	_DMA_CHPRIC_CH10PRIC_SHIFT   10
#define	_DMA_CHPRIC_CH11PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH11PRIC_MASK   0x800UL
#define	_DMA_CHPRIC_CH11PRIC_SHIFT   11
#define	_DMA_CHPRIC_CH1PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH1PRIC_MASK   0x2UL
#define	_DMA_CHPRIC_CH1PRIC_SHIFT   1
#define	_DMA_CHPRIC_CH2PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH2PRIC_MASK   0x4UL
#define	_DMA_CHPRIC_CH2PRIC_SHIFT   2
#define	_DMA_CHPRIC_CH3PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH3PRIC_MASK   0x8UL
#define	_DMA_CHPRIC_CH3PRIC_SHIFT   3
#define	_DMA_CHPRIC_CH4PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH4PRIC_MASK   0x10UL
#define	_DMA_CHPRIC_CH4PRIC_SHIFT   4
#define	_DMA_CHPRIC_CH5PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH5PRIC_MASK   0x20UL
#define	_DMA_CHPRIC_CH5PRIC_SHIFT   5
#define	_DMA_CHPRIC_CH6PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH6PRIC_MASK   0x40UL
#define	_DMA_CHPRIC_CH6PRIC_SHIFT   6
#define	_DMA_CHPRIC_CH7PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH7PRIC_MASK   0x80UL
#define	_DMA_CHPRIC_CH7PRIC_SHIFT   7
#define	_DMA_CHPRIC_CH8PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH8PRIC_MASK   0x100UL
#define	_DMA_CHPRIC_CH8PRIC_SHIFT   8
#define	_DMA_CHPRIC_CH9PRIC_DEFAULT   0x00000000UL
#define	_DMA_CHPRIC_CH9PRIC_MASK   0x200UL
#define	_DMA_CHPRIC_CH9PRIC_SHIFT   9
#define	_DMA_CHPRIC_MASK   0x00000FFFUL
#define	_DMA_CHPRIC_RESETVALUE   0x00000000UL
#define	_DMA_CHPRIS_CH0PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH0PRIS_MASK   0x1UL
#define	_DMA_CHPRIS_CH0PRIS_SHIFT   0
#define	_DMA_CHPRIS_CH10PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH10PRIS_MASK   0x400UL
#define	_DMA_CHPRIS_CH10PRIS_SHIFT   10
#define	_DMA_CHPRIS_CH11PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH11PRIS_MASK   0x800UL
#define	_DMA_CHPRIS_CH11PRIS_SHIFT   11
#define	_DMA_CHPRIS_CH1PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH1PRIS_MASK   0x2UL
#define	_DMA_CHPRIS_CH1PRIS_SHIFT   1
#define	_DMA_CHPRIS_CH2PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH2PRIS_MASK   0x4UL
#define	_DMA_CHPRIS_CH2PRIS_SHIFT   2
#define	_DMA_CHPRIS_CH3PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH3PRIS_MASK   0x8UL
#define	_DMA_CHPRIS_CH3PRIS_SHIFT   3
#define	_DMA_CHPRIS_CH4PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH4PRIS_MASK   0x10UL
#define	_DMA_CHPRIS_CH4PRIS_SHIFT   4
#define	_DMA_CHPRIS_CH5PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH5PRIS_MASK   0x20UL
#define	_DMA_CHPRIS_CH5PRIS_SHIFT   5
#define	_DMA_CHPRIS_CH6PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH6PRIS_MASK   0x40UL
#define	_DMA_CHPRIS_CH6PRIS_SHIFT   6
#define	_DMA_CHPRIS_CH7PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH7PRIS_MASK   0x80UL
#define	_DMA_CHPRIS_CH7PRIS_SHIFT   7
#define	_DMA_CHPRIS_CH8PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH8PRIS_MASK   0x100UL
#define	_DMA_CHPRIS_CH8PRIS_SHIFT   8
#define	_DMA_CHPRIS_CH9PRIS_DEFAULT   0x00000000UL
#define	_DMA_CHPRIS_CH9PRIS_MASK   0x200UL
#define	_DMA_CHPRIS_CH9PRIS_SHIFT   9
#define	_DMA_CHPRIS_MASK   0x00000FFFUL
#define	_DMA_CHPRIS_RESETVALUE   0x00000000UL
#define	_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH0REQMASKC_MASK   0x1UL
#define	_DMA_CHREQMASKC_CH0REQMASKC_SHIFT   0
#define	_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH10REQMASKC_MASK   0x400UL
#define	_DMA_CHREQMASKC_CH10REQMASKC_SHIFT   10
#define	_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH11REQMASKC_MASK   0x800UL
#define	_DMA_CHREQMASKC_CH11REQMASKC_SHIFT   11
#define	_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH1REQMASKC_MASK   0x2UL
#define	_DMA_CHREQMASKC_CH1REQMASKC_SHIFT   1
#define	_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH2REQMASKC_MASK   0x4UL
#define	_DMA_CHREQMASKC_CH2REQMASKC_SHIFT   2
#define	_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH3REQMASKC_MASK   0x8UL
#define	_DMA_CHREQMASKC_CH3REQMASKC_SHIFT   3
#define	_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH4REQMASKC_MASK   0x10UL
#define	_DMA_CHREQMASKC_CH4REQMASKC_SHIFT   4
#define	_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH5REQMASKC_MASK   0x20UL
#define	_DMA_CHREQMASKC_CH5REQMASKC_SHIFT   5
#define	_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH6REQMASKC_MASK   0x40UL
#define	_DMA_CHREQMASKC_CH6REQMASKC_SHIFT   6
#define	_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH7REQMASKC_MASK   0x80UL
#define	_DMA_CHREQMASKC_CH7REQMASKC_SHIFT   7
#define	_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH8REQMASKC_MASK   0x100UL
#define	_DMA_CHREQMASKC_CH8REQMASKC_SHIFT   8
#define	_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKC_CH9REQMASKC_MASK   0x200UL
#define	_DMA_CHREQMASKC_CH9REQMASKC_SHIFT   9
#define	_DMA_CHREQMASKC_MASK   0x00000FFFUL
#define	_DMA_CHREQMASKC_RESETVALUE   0x00000000UL
#define	_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH0REQMASKS_MASK   0x1UL
#define	_DMA_CHREQMASKS_CH0REQMASKS_SHIFT   0
#define	_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH10REQMASKS_MASK   0x400UL
#define	_DMA_CHREQMASKS_CH10REQMASKS_SHIFT   10
#define	_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH11REQMASKS_MASK   0x800UL
#define	_DMA_CHREQMASKS_CH11REQMASKS_SHIFT   11
#define	_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH1REQMASKS_MASK   0x2UL
#define	_DMA_CHREQMASKS_CH1REQMASKS_SHIFT   1
#define	_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH2REQMASKS_MASK   0x4UL
#define	_DMA_CHREQMASKS_CH2REQMASKS_SHIFT   2
#define	_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH3REQMASKS_MASK   0x8UL
#define	_DMA_CHREQMASKS_CH3REQMASKS_SHIFT   3
#define	_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH4REQMASKS_MASK   0x10UL
#define	_DMA_CHREQMASKS_CH4REQMASKS_SHIFT   4
#define	_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH5REQMASKS_MASK   0x20UL
#define	_DMA_CHREQMASKS_CH5REQMASKS_SHIFT   5
#define	_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH6REQMASKS_MASK   0x40UL
#define	_DMA_CHREQMASKS_CH6REQMASKS_SHIFT   6
#define	_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH7REQMASKS_MASK   0x80UL
#define	_DMA_CHREQMASKS_CH7REQMASKS_SHIFT   7
#define	_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH8REQMASKS_MASK   0x100UL
#define	_DMA_CHREQMASKS_CH8REQMASKS_SHIFT   8
#define	_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT   0x00000000UL
#define	_DMA_CHREQMASKS_CH9REQMASKS_MASK   0x200UL
#define	_DMA_CHREQMASKS_CH9REQMASKS_SHIFT   9
#define	_DMA_CHREQMASKS_MASK   0x00000FFFUL
#define	_DMA_CHREQMASKS_RESETVALUE   0x00000000UL
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_MASK   0x1UL
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT   0
#define	_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH10REQSTATUS_MASK   0x400UL
#define	_DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT   10
#define	_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH11REQSTATUS_MASK   0x800UL
#define	_DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT   11
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_MASK   0x2UL
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT   1
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_MASK   0x4UL
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT   2
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_MASK   0x8UL
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT   3
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_MASK   0x10UL
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT   4
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_MASK   0x20UL
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT   5
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_MASK   0x40UL
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT   6
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_MASK   0x80UL
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT   7
#define	_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH8REQSTATUS_MASK   0x100UL
#define	_DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT   8
#define	_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHREQSTATUS_CH9REQSTATUS_MASK   0x200UL
#define	_DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT   9
#define	_DMA_CHREQSTATUS_MASK   0x00000FFFUL
#define	_DMA_CHREQSTATUS_RESETVALUE   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK   0x1UL
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT   0
#define	_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK   0x400UL
#define	_DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT   10
#define	_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK   0x800UL
#define	_DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT   11
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK   0x2UL
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT   1
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK   0x4UL
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT   2
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK   0x8UL
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT   3
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK   0x10UL
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT   4
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK   0x20UL
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT   5
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK   0x40UL
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT   6
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK   0x80UL
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT   7
#define	_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK   0x100UL
#define	_DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT   8
#define	_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT   0x00000000UL
#define	_DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK   0x200UL
#define	_DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT   9
#define	_DMA_CHSREQSTATUS_MASK   0x00000FFFUL
#define	_DMA_CHSREQSTATUS_RESETVALUE   0x00000000UL
#define	_DMA_CHSWREQ_CH0SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH0SWREQ_MASK   0x1UL
#define	_DMA_CHSWREQ_CH0SWREQ_SHIFT   0
#define	_DMA_CHSWREQ_CH10SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH10SWREQ_MASK   0x400UL
#define	_DMA_CHSWREQ_CH10SWREQ_SHIFT   10
#define	_DMA_CHSWREQ_CH11SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH11SWREQ_MASK   0x800UL
#define	_DMA_CHSWREQ_CH11SWREQ_SHIFT   11
#define	_DMA_CHSWREQ_CH1SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH1SWREQ_MASK   0x2UL
#define	_DMA_CHSWREQ_CH1SWREQ_SHIFT   1
#define	_DMA_CHSWREQ_CH2SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH2SWREQ_MASK   0x4UL
#define	_DMA_CHSWREQ_CH2SWREQ_SHIFT   2
#define	_DMA_CHSWREQ_CH3SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH3SWREQ_MASK   0x8UL
#define	_DMA_CHSWREQ_CH3SWREQ_SHIFT   3
#define	_DMA_CHSWREQ_CH4SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH4SWREQ_MASK   0x10UL
#define	_DMA_CHSWREQ_CH4SWREQ_SHIFT   4
#define	_DMA_CHSWREQ_CH5SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH5SWREQ_MASK   0x20UL
#define	_DMA_CHSWREQ_CH5SWREQ_SHIFT   5
#define	_DMA_CHSWREQ_CH6SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH6SWREQ_MASK   0x40UL
#define	_DMA_CHSWREQ_CH6SWREQ_SHIFT   6
#define	_DMA_CHSWREQ_CH7SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH7SWREQ_MASK   0x80UL
#define	_DMA_CHSWREQ_CH7SWREQ_SHIFT   7
#define	_DMA_CHSWREQ_CH8SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH8SWREQ_MASK   0x100UL
#define	_DMA_CHSWREQ_CH8SWREQ_SHIFT   8
#define	_DMA_CHSWREQ_CH9SWREQ_DEFAULT   0x00000000UL
#define	_DMA_CHSWREQ_CH9SWREQ_MASK   0x200UL
#define	_DMA_CHSWREQ_CH9SWREQ_SHIFT   9
#define	_DMA_CHSWREQ_MASK   0x00000FFFUL
#define	_DMA_CHSWREQ_RESETVALUE   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH08USEBURSTC_MASK   0x100UL
#define	_DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT   8
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_MASK   0x1UL
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT   0
#define	_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH10USEBURSTC_MASK   0x400UL
#define	_DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT   10
#define	_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH11USEBURSTC_MASK   0x800UL
#define	_DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT   11
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_MASK   0x2UL
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT   1
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_MASK   0x4UL
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT   2
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_MASK   0x8UL
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT   3
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_MASK   0x10UL
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT   4
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_MASK   0x20UL
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT   5
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_MASK   0x40UL
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT   6
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_MASK   0x80UL
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT   7
#define	_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTC_CH9USEBURSTC_MASK   0x200UL
#define	_DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT   9
#define	_DMA_CHUSEBURSTC_MASK   0x00000FFFUL
#define	_DMA_CHUSEBURSTC_RESETVALUE   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   0x00000001UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_MASK   0x1UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT   0
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH10USEBURSTS_MASK   0x400UL
#define	_DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT   10
#define	_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH11USEBURSTS_MASK   0x800UL
#define	_DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT   11
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_MASK   0x2UL
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT   1
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_MASK   0x4UL
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT   2
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_MASK   0x8UL
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT   3
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_MASK   0x10UL
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT   4
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_MASK   0x20UL
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT   5
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_MASK   0x40UL
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT   6
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_MASK   0x80UL
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT   7
#define	_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH8USEBURSTS_MASK   0x100UL
#define	_DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT   8
#define	_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH9USEBURSTS_MASK   0x200UL
#define	_DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT   9
#define	_DMA_CHUSEBURSTS_MASK   0x00000FFFUL
#define	_DMA_CHUSEBURSTS_RESETVALUE   0x00000000UL
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK   0x1UL
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT   0
#define	_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK   0x400UL
#define	_DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT   10
#define	_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK   0x800UL
#define	_DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT   11
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK   0x2UL
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT   1
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK   0x4UL
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT   2
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK   0x8UL
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT   3
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK   0x10UL
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT   4
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK   0x20UL
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT   5
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK   0x40UL
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT   6
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK   0x80UL
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT   7
#define	_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK   0x100UL
#define	_DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT   8
#define	_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT   0x00000001UL
#define	_DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK   0x200UL
#define	_DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT   9
#define	_DMA_CHWAITSTATUS_MASK   0x00000FFFUL
#define	_DMA_CHWAITSTATUS_RESETVALUE   0x00000FFFUL
#define	_DMA_CONFIG_CHPROT_DEFAULT   0x00000000UL
#define	_DMA_CONFIG_CHPROT_MASK   0x20UL
#define	_DMA_CONFIG_CHPROT_SHIFT   5
#define	_DMA_CONFIG_EN_DEFAULT   0x00000000UL
#define	_DMA_CONFIG_EN_MASK   0x1UL
#define	_DMA_CONFIG_EN_SHIFT   0
#define	_DMA_CONFIG_MASK   0x00000021UL
#define	_DMA_CONFIG_RESETVALUE   0x00000000UL
#define	_DMA_CTRL_DESCRECT_DEFAULT   0x00000000UL
#define	_DMA_CTRL_DESCRECT_MASK   0x1UL
#define	_DMA_CTRL_DESCRECT_SHIFT   0
#define	_DMA_CTRL_MASK   0x00000003UL
#define	_DMA_CTRL_PRDU_DEFAULT   0x00000000UL
#define	_DMA_CTRL_PRDU_MASK   0x2UL
#define	_DMA_CTRL_PRDU_SHIFT   1
#define	_DMA_CTRL_RESETVALUE   0x00000000UL
#define	_DMA_CTRLBASE_CTRLBASE_DEFAULT   0x00000000UL
#define	_DMA_CTRLBASE_CTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_CTRLBASE_CTRLBASE_SHIFT   0
#define	_DMA_CTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_CTRLBASE_RESETVALUE   0x00000000UL
#define	_DMA_ERRORC_ERRORC_DEFAULT   0x00000000UL
#define	_DMA_ERRORC_ERRORC_MASK   0x1UL
#define	_DMA_ERRORC_ERRORC_SHIFT   0
#define	_DMA_ERRORC_MASK   0x00000001UL
#define	_DMA_ERRORC_RESETVALUE   0x00000000UL
#define	_DMA_IEN_CH0DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH0DONE_MASK   0x1UL
#define	_DMA_IEN_CH0DONE_SHIFT   0
#define	_DMA_IEN_CH10DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH10DONE_MASK   0x400UL
#define	_DMA_IEN_CH10DONE_SHIFT   10
#define	_DMA_IEN_CH11DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH11DONE_MASK   0x800UL
#define	_DMA_IEN_CH11DONE_SHIFT   11
#define	_DMA_IEN_CH1DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH1DONE_MASK   0x2UL
#define	_DMA_IEN_CH1DONE_SHIFT   1
#define	_DMA_IEN_CH2DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH2DONE_MASK   0x4UL
#define	_DMA_IEN_CH2DONE_SHIFT   2
#define	_DMA_IEN_CH3DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH3DONE_MASK   0x8UL
#define	_DMA_IEN_CH3DONE_SHIFT   3
#define	_DMA_IEN_CH4DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH4DONE_MASK   0x10UL
#define	_DMA_IEN_CH4DONE_SHIFT   4
#define	_DMA_IEN_CH5DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH5DONE_MASK   0x20UL
#define	_DMA_IEN_CH5DONE_SHIFT   5
#define	_DMA_IEN_CH6DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH6DONE_MASK   0x40UL
#define	_DMA_IEN_CH6DONE_SHIFT   6
#define	_DMA_IEN_CH7DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH7DONE_MASK   0x80UL
#define	_DMA_IEN_CH7DONE_SHIFT   7
#define	_DMA_IEN_CH8DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH8DONE_MASK   0x100UL
#define	_DMA_IEN_CH8DONE_SHIFT   8
#define	_DMA_IEN_CH9DONE_DEFAULT   0x00000000UL
#define	_DMA_IEN_CH9DONE_MASK   0x200UL
#define	_DMA_IEN_CH9DONE_SHIFT   9
#define	_DMA_IEN_ERR_DEFAULT   0x00000000UL
#define	_DMA_IEN_ERR_MASK   0x80000000UL
#define	_DMA_IEN_ERR_SHIFT   31
#define	_DMA_IEN_MASK   0x80000FFFUL
#define	_DMA_IEN_RESETVALUE   0x00000000UL
#define	_DMA_IF_CH0DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH0DONE_MASK   0x1UL
#define	_DMA_IF_CH0DONE_SHIFT   0
#define	_DMA_IF_CH10DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH10DONE_MASK   0x400UL
#define	_DMA_IF_CH10DONE_SHIFT   10
#define	_DMA_IF_CH11DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH11DONE_MASK   0x800UL
#define	_DMA_IF_CH11DONE_SHIFT   11
#define	_DMA_IF_CH1DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH1DONE_MASK   0x2UL
#define	_DMA_IF_CH1DONE_SHIFT   1
#define	_DMA_IF_CH2DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH2DONE_MASK   0x4UL
#define	_DMA_IF_CH2DONE_SHIFT   2
#define	_DMA_IF_CH3DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH3DONE_MASK   0x8UL
#define	_DMA_IF_CH3DONE_SHIFT   3
#define	_DMA_IF_CH4DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH4DONE_MASK   0x10UL
#define	_DMA_IF_CH4DONE_SHIFT   4
#define	_DMA_IF_CH5DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH5DONE_MASK   0x20UL
#define	_DMA_IF_CH5DONE_SHIFT   5
#define	_DMA_IF_CH6DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH6DONE_MASK   0x40UL
#define	_DMA_IF_CH6DONE_SHIFT   6
#define	_DMA_IF_CH7DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH7DONE_MASK   0x80UL
#define	_DMA_IF_CH7DONE_SHIFT   7
#define	_DMA_IF_CH8DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH8DONE_MASK   0x100UL
#define	_DMA_IF_CH8DONE_SHIFT   8
#define	_DMA_IF_CH9DONE_DEFAULT   0x00000000UL
#define	_DMA_IF_CH9DONE_MASK   0x200UL
#define	_DMA_IF_CH9DONE_SHIFT   9
#define	_DMA_IF_ERR_DEFAULT   0x00000000UL
#define	_DMA_IF_ERR_MASK   0x80000000UL
#define	_DMA_IF_ERR_SHIFT   31
#define	_DMA_IF_MASK   0x80000FFFUL
#define	_DMA_IF_RESETVALUE   0x00000000UL
#define	_DMA_IFC_CH0DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH0DONE_MASK   0x1UL
#define	_DMA_IFC_CH0DONE_SHIFT   0
#define	_DMA_IFC_CH10DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH10DONE_MASK   0x400UL
#define	_DMA_IFC_CH10DONE_SHIFT   10
#define	_DMA_IFC_CH11DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH11DONE_MASK   0x800UL
#define	_DMA_IFC_CH11DONE_SHIFT   11
#define	_DMA_IFC_CH1DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH1DONE_MASK   0x2UL
#define	_DMA_IFC_CH1DONE_SHIFT   1
#define	_DMA_IFC_CH2DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH2DONE_MASK   0x4UL
#define	_DMA_IFC_CH2DONE_SHIFT   2
#define	_DMA_IFC_CH3DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH3DONE_MASK   0x8UL
#define	_DMA_IFC_CH3DONE_SHIFT   3
#define	_DMA_IFC_CH4DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH4DONE_MASK   0x10UL
#define	_DMA_IFC_CH4DONE_SHIFT   4
#define	_DMA_IFC_CH5DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH5DONE_MASK   0x20UL
#define	_DMA_IFC_CH5DONE_SHIFT   5
#define	_DMA_IFC_CH6DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH6DONE_MASK   0x40UL
#define	_DMA_IFC_CH6DONE_SHIFT   6
#define	_DMA_IFC_CH7DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH7DONE_MASK   0x80UL
#define	_DMA_IFC_CH7DONE_SHIFT   7
#define	_DMA_IFC_CH8DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH8DONE_MASK   0x100UL
#define	_DMA_IFC_CH8DONE_SHIFT   8
#define	_DMA_IFC_CH9DONE_DEFAULT   0x00000000UL
#define	_DMA_IFC_CH9DONE_MASK   0x200UL
#define	_DMA_IFC_CH9DONE_SHIFT   9
#define	_DMA_IFC_ERR_DEFAULT   0x00000000UL
#define	_DMA_IFC_ERR_MASK   0x80000000UL
#define	_DMA_IFC_ERR_SHIFT   31
#define	_DMA_IFC_MASK   0x80000FFFUL
#define	_DMA_IFC_RESETVALUE   0x00000000UL
#define	_DMA_IFS_CH0DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH0DONE_MASK   0x1UL
#define	_DMA_IFS_CH0DONE_SHIFT   0
#define	_DMA_IFS_CH10DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH10DONE_MASK   0x400UL
#define	_DMA_IFS_CH10DONE_SHIFT   10
#define	_DMA_IFS_CH11DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH11DONE_MASK   0x800UL
#define	_DMA_IFS_CH11DONE_SHIFT   11
#define	_DMA_IFS_CH1DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH1DONE_MASK   0x2UL
#define	_DMA_IFS_CH1DONE_SHIFT   1
#define	_DMA_IFS_CH2DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH2DONE_MASK   0x4UL
#define	_DMA_IFS_CH2DONE_SHIFT   2
#define	_DMA_IFS_CH3DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH3DONE_MASK   0x8UL
#define	_DMA_IFS_CH3DONE_SHIFT   3
#define	_DMA_IFS_CH4DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH4DONE_MASK   0x10UL
#define	_DMA_IFS_CH4DONE_SHIFT   4
#define	_DMA_IFS_CH5DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH5DONE_MASK   0x20UL
#define	_DMA_IFS_CH5DONE_SHIFT   5
#define	_DMA_IFS_CH6DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH6DONE_MASK   0x40UL
#define	_DMA_IFS_CH6DONE_SHIFT   6
#define	_DMA_IFS_CH7DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH7DONE_MASK   0x80UL
#define	_DMA_IFS_CH7DONE_SHIFT   7
#define	_DMA_IFS_CH8DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH8DONE_MASK   0x100UL
#define	_DMA_IFS_CH8DONE_SHIFT   8
#define	_DMA_IFS_CH9DONE_DEFAULT   0x00000000UL
#define	_DMA_IFS_CH9DONE_MASK   0x200UL
#define	_DMA_IFS_CH9DONE_SHIFT   9
#define	_DMA_IFS_ERR_DEFAULT   0x00000000UL
#define	_DMA_IFS_ERR_MASK   0x80000000UL
#define	_DMA_IFS_ERR_SHIFT   31
#define	_DMA_IFS_MASK   0x80000FFFUL
#define	_DMA_IFS_RESETVALUE   0x00000000UL
#define	_DMA_LOOP0_EN_DEFAULT   0x00000000UL
#define	_DMA_LOOP0_EN_MASK   0x10000UL
#define	_DMA_LOOP0_EN_SHIFT   16
#define	_DMA_LOOP0_MASK   0x000103FFUL
#define	_DMA_LOOP0_RESETVALUE   0x00000000UL
#define	_DMA_LOOP0_WIDTH_DEFAULT   0x00000000UL
#define	_DMA_LOOP0_WIDTH_MASK   0x3FFUL
#define	_DMA_LOOP0_WIDTH_SHIFT   0
#define	_DMA_LOOP1_EN_DEFAULT   0x00000000UL
#define	_DMA_LOOP1_EN_MASK   0x10000UL
#define	_DMA_LOOP1_EN_SHIFT   16
#define	_DMA_LOOP1_MASK   0x000103FFUL
#define	_DMA_LOOP1_RESETVALUE   0x00000000UL
#define	_DMA_LOOP1_WIDTH_DEFAULT   0x00000000UL
#define	_DMA_LOOP1_WIDTH_MASK   0x3FFUL
#define	_DMA_LOOP1_WIDTH_SHIFT   0
#define	_DMA_RDS_MASK   0x00000FFFUL
#define	_DMA_RDS_RDSCH0_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH0_MASK   0x1UL
#define	_DMA_RDS_RDSCH0_SHIFT   0
#define	_DMA_RDS_RDSCH10_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH10_MASK   0x400UL
#define	_DMA_RDS_RDSCH10_SHIFT   10
#define	_DMA_RDS_RDSCH11_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH11_MASK   0x800UL
#define	_DMA_RDS_RDSCH11_SHIFT   11
#define	_DMA_RDS_RDSCH1_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH1_MASK   0x2UL
#define	_DMA_RDS_RDSCH1_SHIFT   1
#define	_DMA_RDS_RDSCH2_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH2_MASK   0x4UL
#define	_DMA_RDS_RDSCH2_SHIFT   2
#define	_DMA_RDS_RDSCH3_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH3_MASK   0x8UL
#define	_DMA_RDS_RDSCH3_SHIFT   3
#define	_DMA_RDS_RDSCH4_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH4_MASK   0x10UL
#define	_DMA_RDS_RDSCH4_SHIFT   4
#define	_DMA_RDS_RDSCH5_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH5_MASK   0x20UL
#define	_DMA_RDS_RDSCH5_SHIFT   5
#define	_DMA_RDS_RDSCH6_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH6_MASK   0x40UL
#define	_DMA_RDS_RDSCH6_SHIFT   6
#define	_DMA_RDS_RDSCH7_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH7_MASK   0x80UL
#define	_DMA_RDS_RDSCH7_SHIFT   7
#define	_DMA_RDS_RDSCH8_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH8_MASK   0x100UL
#define	_DMA_RDS_RDSCH8_SHIFT   8
#define	_DMA_RDS_RDSCH9_DEFAULT   0x00000000UL
#define	_DMA_RDS_RDSCH9_MASK   0x200UL
#define	_DMA_RDS_RDSCH9_SHIFT   9
#define	_DMA_RDS_RESETVALUE   0x00000000UL
#define	_DMA_RECT0_DSTSTRIDE_DEFAULT   0x00000000UL
#define	_DMA_RECT0_DSTSTRIDE_MASK   0xFFE00000UL
#define	_DMA_RECT0_DSTSTRIDE_SHIFT   21
#define	_DMA_RECT0_HEIGHT_DEFAULT   0x00000000UL
#define	_DMA_RECT0_HEIGHT_MASK   0x3FFUL
#define	_DMA_RECT0_HEIGHT_SHIFT   0
#define	_DMA_RECT0_MASK   0xFFFFFFFFUL
#define	_DMA_RECT0_RESETVALUE   0x00000000UL
#define	_DMA_RECT0_SRCSTRIDE_DEFAULT   0x00000000UL
#define	_DMA_RECT0_SRCSTRIDE_MASK   0x1FFC00UL
#define	_DMA_RECT0_SRCSTRIDE_SHIFT   10
#define	_DMA_STATUS_CHNUM_DEFAULT   0x0000000BUL
#define	_DMA_STATUS_CHNUM_MASK   0x1F0000UL
#define	_DMA_STATUS_CHNUM_SHIFT   16
#define	_DMA_STATUS_EN_DEFAULT   0x00000000UL
#define	_DMA_STATUS_EN_MASK   0x1UL
#define	_DMA_STATUS_EN_SHIFT   0
#define	_DMA_STATUS_MASK   0x001F00F1UL
#define	_DMA_STATUS_RESETVALUE   0x100B0000UL
#define	_DMA_STATUS_STATE_DEFAULT   0x00000000UL
#define	_DMA_STATUS_STATE_DONE   0x00000009UL
#define	_DMA_STATUS_STATE_IDLE   0x00000000UL
#define	_DMA_STATUS_STATE_MASK   0xF0UL
#define	_DMA_STATUS_STATE_PERSCATTRANS   0x0000000AUL
#define	_DMA_STATUS_STATE_RDCHCTRLDATA   0x00000001UL
#define	_DMA_STATUS_STATE_RDDSTENDPTR   0x00000003UL
#define	_DMA_STATUS_STATE_RDSRCDATA   0x00000004UL
#define	_DMA_STATUS_STATE_RDSRCENDPTR   0x00000002UL
#define	_DMA_STATUS_STATE_SHIFT   4
#define	_DMA_STATUS_STATE_STALLED   0x00000008UL
#define	_DMA_STATUS_STATE_WAITREQCLR   0x00000006UL
#define	_DMA_STATUS_STATE_WRCHCTRLDATA   0x00000007UL
#define	_DMA_STATUS_STATE_WRDSTDATA   0x00000005UL
#define	DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
#define	DMA_CH_CTRL_SIGSEL_ADC0SCAN   (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
#define	DMA_CH_CTRL_SIGSEL_ADC0SINGLE   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
#define	DMA_CH_CTRL_SIGSEL_AESDATARD   (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
#define	DMA_CH_CTRL_SIGSEL_AESDATAWR   (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
#define	DMA_CH_CTRL_SIGSEL_AESKEYWR   (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
#define	DMA_CH_CTRL_SIGSEL_AESXORDATAWR   (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
#define	DMA_CH_CTRL_SIGSEL_DAC0CH0   (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)
#define	DMA_CH_CTRL_SIGSEL_DAC0CH1   (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C0TXBL   (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C1RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C1TXBL   (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV   (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_MSCWDATA   (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC0   (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC1   (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC2   (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC0   (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC1   (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC2   (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC0   (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC1   (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC2   (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER3CC0   (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER3CC1   (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER3CC2   (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER3UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0TXBL   (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_UART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_UART1TXBL   (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_UART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXBL   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT   (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXBL   (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT   (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV   (_DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USARTRF0TXBL   (_DMA_CH_CTRL_SIGSEL_USARTRF0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY << 0)
#define	DMA_CH_CTRL_SOURCESEL_ADC0   (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_AES   (_DMA_CH_CTRL_SOURCESEL_AES << 16)
#define	DMA_CH_CTRL_SOURCESEL_DAC0   (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_I2C0   (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_I2C1   (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_LESENSE   (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16)
#define	DMA_CH_CTRL_SOURCESEL_LEUART0   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_LEUART1   (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_MSC   (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
#define	DMA_CH_CTRL_SOURCESEL_NONE   (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER0   (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER1   (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER2   (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER3   (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16)
#define	DMA_CH_CTRL_SOURCESEL_UART0   (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_UART1   (_DMA_CH_CTRL_SOURCESEL_UART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART1   (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART2   (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USARTRF0   (_DMA_CH_CTRL_SOURCESEL_USARTRF0 << 16)
#define	DMA_CHALTC_CH0ALTC   (0x1UL << 0)
#define	DMA_CHALTC_CH0ALTC_DEFAULT   (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
#define	DMA_CHALTC_CH10ALTC   (0x1UL << 10)
#define	DMA_CHALTC_CH10ALTC_DEFAULT   (_DMA_CHALTC_CH10ALTC_DEFAULT << 10)
#define	DMA_CHALTC_CH11ALTC   (0x1UL << 11)
#define	DMA_CHALTC_CH11ALTC_DEFAULT   (_DMA_CHALTC_CH11ALTC_DEFAULT << 11)
#define	DMA_CHALTC_CH1ALTC   (0x1UL << 1)
#define	DMA_CHALTC_CH1ALTC_DEFAULT   (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
#define	DMA_CHALTC_CH2ALTC   (0x1UL << 2)
#define	DMA_CHALTC_CH2ALTC_DEFAULT   (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
#define	DMA_CHALTC_CH3ALTC   (0x1UL << 3)
#define	DMA_CHALTC_CH3ALTC_DEFAULT   (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
#define	DMA_CHALTC_CH4ALTC   (0x1UL << 4)
#define	DMA_CHALTC_CH4ALTC_DEFAULT   (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
#define	DMA_CHALTC_CH5ALTC   (0x1UL << 5)
#define	DMA_CHALTC_CH5ALTC_DEFAULT   (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
#define	DMA_CHALTC_CH6ALTC   (0x1UL << 6)
#define	DMA_CHALTC_CH6ALTC_DEFAULT   (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
#define	DMA_CHALTC_CH7ALTC   (0x1UL << 7)
#define	DMA_CHALTC_CH7ALTC_DEFAULT   (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
#define	DMA_CHALTC_CH8ALTC   (0x1UL << 8)
#define	DMA_CHALTC_CH8ALTC_DEFAULT   (_DMA_CHALTC_CH8ALTC_DEFAULT << 8)
#define	DMA_CHALTC_CH9ALTC   (0x1UL << 9)
#define	DMA_CHALTC_CH9ALTC_DEFAULT   (_DMA_CHALTC_CH9ALTC_DEFAULT << 9)
#define	DMA_CHALTS_CH0ALTS   (0x1UL << 0)
#define	DMA_CHALTS_CH0ALTS_DEFAULT   (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
#define	DMA_CHALTS_CH10ALTS   (0x1UL << 10)
#define	DMA_CHALTS_CH10ALTS_DEFAULT   (_DMA_CHALTS_CH10ALTS_DEFAULT << 10)
#define	DMA_CHALTS_CH11ALTS   (0x1UL << 11)
#define	DMA_CHALTS_CH11ALTS_DEFAULT   (_DMA_CHALTS_CH11ALTS_DEFAULT << 11)
#define	DMA_CHALTS_CH1ALTS   (0x1UL << 1)
#define	DMA_CHALTS_CH1ALTS_DEFAULT   (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
#define	DMA_CHALTS_CH2ALTS   (0x1UL << 2)
#define	DMA_CHALTS_CH2ALTS_DEFAULT   (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
#define	DMA_CHALTS_CH3ALTS   (0x1UL << 3)
#define	DMA_CHALTS_CH3ALTS_DEFAULT   (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
#define	DMA_CHALTS_CH4ALTS   (0x1UL << 4)
#define	DMA_CHALTS_CH4ALTS_DEFAULT   (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
#define	DMA_CHALTS_CH5ALTS   (0x1UL << 5)
#define	DMA_CHALTS_CH5ALTS_DEFAULT   (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
#define	DMA_CHALTS_CH6ALTS   (0x1UL << 6)
#define	DMA_CHALTS_CH6ALTS_DEFAULT   (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
#define	DMA_CHALTS_CH7ALTS   (0x1UL << 7)
#define	DMA_CHALTS_CH7ALTS_DEFAULT   (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
#define	DMA_CHALTS_CH8ALTS   (0x1UL << 8)
#define	DMA_CHALTS_CH8ALTS_DEFAULT   (_DMA_CHALTS_CH8ALTS_DEFAULT << 8)
#define	DMA_CHALTS_CH9ALTS   (0x1UL << 9)
#define	DMA_CHALTS_CH9ALTS_DEFAULT   (_DMA_CHALTS_CH9ALTS_DEFAULT << 9)
#define	DMA_CHENC_CH0ENC   (0x1UL << 0)
#define	DMA_CHENC_CH0ENC_DEFAULT   (_DMA_CHENC_CH0ENC_DEFAULT << 0)
#define	DMA_CHENC_CH10ENC   (0x1UL << 10)
#define	DMA_CHENC_CH10ENC_DEFAULT   (_DMA_CHENC_CH10ENC_DEFAULT << 10)
#define	DMA_CHENC_CH11ENC   (0x1UL << 11)
#define	DMA_CHENC_CH11ENC_DEFAULT   (_DMA_CHENC_CH11ENC_DEFAULT << 11)
#define	DMA_CHENC_CH1ENC   (0x1UL << 1)
#define	DMA_CHENC_CH1ENC_DEFAULT   (_DMA_CHENC_CH1ENC_DEFAULT << 1)
#define	DMA_CHENC_CH2ENC   (0x1UL << 2)
#define	DMA_CHENC_CH2ENC_DEFAULT   (_DMA_CHENC_CH2ENC_DEFAULT << 2)
#define	DMA_CHENC_CH3ENC   (0x1UL << 3)
#define	DMA_CHENC_CH3ENC_DEFAULT   (_DMA_CHENC_CH3ENC_DEFAULT << 3)
#define	DMA_CHENC_CH4ENC   (0x1UL << 4)
#define	DMA_CHENC_CH4ENC_DEFAULT   (_DMA_CHENC_CH4ENC_DEFAULT << 4)
#define	DMA_CHENC_CH5ENC   (0x1UL << 5)
#define	DMA_CHENC_CH5ENC_DEFAULT   (_DMA_CHENC_CH5ENC_DEFAULT << 5)
#define	DMA_CHENC_CH6ENC   (0x1UL << 6)
#define	DMA_CHENC_CH6ENC_DEFAULT   (_DMA_CHENC_CH6ENC_DEFAULT << 6)
#define	DMA_CHENC_CH7ENC   (0x1UL << 7)
#define	DMA_CHENC_CH7ENC_DEFAULT   (_DMA_CHENC_CH7ENC_DEFAULT << 7)
#define	DMA_CHENC_CH8ENC   (0x1UL << 8)
#define	DMA_CHENC_CH8ENC_DEFAULT   (_DMA_CHENC_CH8ENC_DEFAULT << 8)
#define	DMA_CHENC_CH9ENC   (0x1UL << 9)
#define	DMA_CHENC_CH9ENC_DEFAULT   (_DMA_CHENC_CH9ENC_DEFAULT << 9)
#define	DMA_CHENS_CH0ENS   (0x1UL << 0)
#define	DMA_CHENS_CH0ENS_DEFAULT   (_DMA_CHENS_CH0ENS_DEFAULT << 0)
#define	DMA_CHENS_CH10ENS   (0x1UL << 10)
#define	DMA_CHENS_CH10ENS_DEFAULT   (_DMA_CHENS_CH10ENS_DEFAULT << 10)
#define	DMA_CHENS_CH11ENS   (0x1UL << 11)
#define	DMA_CHENS_CH11ENS_DEFAULT   (_DMA_CHENS_CH11ENS_DEFAULT << 11)
#define	DMA_CHENS_CH1ENS   (0x1UL << 1)
#define	DMA_CHENS_CH1ENS_DEFAULT   (_DMA_CHENS_CH1ENS_DEFAULT << 1)
#define	DMA_CHENS_CH2ENS   (0x1UL << 2)
#define	DMA_CHENS_CH2ENS_DEFAULT   (_DMA_CHENS_CH2ENS_DEFAULT << 2)
#define	DMA_CHENS_CH3ENS   (0x1UL << 3)
#define	DMA_CHENS_CH3ENS_DEFAULT   (_DMA_CHENS_CH3ENS_DEFAULT << 3)
#define	DMA_CHENS_CH4ENS   (0x1UL << 4)
#define	DMA_CHENS_CH4ENS_DEFAULT   (_DMA_CHENS_CH4ENS_DEFAULT << 4)
#define	DMA_CHENS_CH5ENS   (0x1UL << 5)
#define	DMA_CHENS_CH5ENS_DEFAULT   (_DMA_CHENS_CH5ENS_DEFAULT << 5)
#define	DMA_CHENS_CH6ENS   (0x1UL << 6)
#define	DMA_CHENS_CH6ENS_DEFAULT   (_DMA_CHENS_CH6ENS_DEFAULT << 6)
#define	DMA_CHENS_CH7ENS   (0x1UL << 7)
#define	DMA_CHENS_CH7ENS_DEFAULT   (_DMA_CHENS_CH7ENS_DEFAULT << 7)
#define	DMA_CHENS_CH8ENS   (0x1UL << 8)
#define	DMA_CHENS_CH8ENS_DEFAULT   (_DMA_CHENS_CH8ENS_DEFAULT << 8)
#define	DMA_CHENS_CH9ENS   (0x1UL << 9)
#define	DMA_CHENS_CH9ENS_DEFAULT   (_DMA_CHENS_CH9ENS_DEFAULT << 9)
#define	DMA_CHPRIC_CH0PRIC   (0x1UL << 0)
#define	DMA_CHPRIC_CH0PRIC_DEFAULT   (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
#define	DMA_CHPRIC_CH10PRIC   (0x1UL << 10)
#define	DMA_CHPRIC_CH10PRIC_DEFAULT   (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10)
#define	DMA_CHPRIC_CH11PRIC   (0x1UL << 11)
#define	DMA_CHPRIC_CH11PRIC_DEFAULT   (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11)
#define	DMA_CHPRIC_CH1PRIC   (0x1UL << 1)
#define	DMA_CHPRIC_CH1PRIC_DEFAULT   (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
#define	DMA_CHPRIC_CH2PRIC   (0x1UL << 2)
#define	DMA_CHPRIC_CH2PRIC_DEFAULT   (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
#define	DMA_CHPRIC_CH3PRIC   (0x1UL << 3)
#define	DMA_CHPRIC_CH3PRIC_DEFAULT   (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
#define	DMA_CHPRIC_CH4PRIC   (0x1UL << 4)
#define	DMA_CHPRIC_CH4PRIC_DEFAULT   (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
#define	DMA_CHPRIC_CH5PRIC   (0x1UL << 5)
#define	DMA_CHPRIC_CH5PRIC_DEFAULT   (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
#define	DMA_CHPRIC_CH6PRIC   (0x1UL << 6)
#define	DMA_CHPRIC_CH6PRIC_DEFAULT   (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
#define	DMA_CHPRIC_CH7PRIC   (0x1UL << 7)
#define	DMA_CHPRIC_CH7PRIC_DEFAULT   (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
#define	DMA_CHPRIC_CH8PRIC   (0x1UL << 8)
#define	DMA_CHPRIC_CH8PRIC_DEFAULT   (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8)
#define	DMA_CHPRIC_CH9PRIC   (0x1UL << 9)
#define	DMA_CHPRIC_CH9PRIC_DEFAULT   (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9)
#define	DMA_CHPRIS_CH0PRIS   (0x1UL << 0)
#define	DMA_CHPRIS_CH0PRIS_DEFAULT   (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
#define	DMA_CHPRIS_CH10PRIS   (0x1UL << 10)
#define	DMA_CHPRIS_CH10PRIS_DEFAULT   (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10)
#define	DMA_CHPRIS_CH11PRIS   (0x1UL << 11)
#define	DMA_CHPRIS_CH11PRIS_DEFAULT   (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11)
#define	DMA_CHPRIS_CH1PRIS   (0x1UL << 1)
#define	DMA_CHPRIS_CH1PRIS_DEFAULT   (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
#define	DMA_CHPRIS_CH2PRIS   (0x1UL << 2)
#define	DMA_CHPRIS_CH2PRIS_DEFAULT   (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
#define	DMA_CHPRIS_CH3PRIS   (0x1UL << 3)
#define	DMA_CHPRIS_CH3PRIS_DEFAULT   (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
#define	DMA_CHPRIS_CH4PRIS   (0x1UL << 4)
#define	DMA_CHPRIS_CH4PRIS_DEFAULT   (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
#define	DMA_CHPRIS_CH5PRIS   (0x1UL << 5)
#define	DMA_CHPRIS_CH5PRIS_DEFAULT   (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
#define	DMA_CHPRIS_CH6PRIS   (0x1UL << 6)
#define	DMA_CHPRIS_CH6PRIS_DEFAULT   (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
#define	DMA_CHPRIS_CH7PRIS   (0x1UL << 7)
#define	DMA_CHPRIS_CH7PRIS_DEFAULT   (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
#define	DMA_CHPRIS_CH8PRIS   (0x1UL << 8)
#define	DMA_CHPRIS_CH8PRIS_DEFAULT   (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8)
#define	DMA_CHPRIS_CH9PRIS   (0x1UL << 9)
#define	DMA_CHPRIS_CH9PRIS_DEFAULT   (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9)
#define	DMA_CHREQMASKC_CH0REQMASKC   (0x1UL << 0)
#define	DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
#define	DMA_CHREQMASKC_CH10REQMASKC   (0x1UL << 10)
#define	DMA_CHREQMASKC_CH10REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10)
#define	DMA_CHREQMASKC_CH11REQMASKC   (0x1UL << 11)
#define	DMA_CHREQMASKC_CH11REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11)
#define	DMA_CHREQMASKC_CH1REQMASKC   (0x1UL << 1)
#define	DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
#define	DMA_CHREQMASKC_CH2REQMASKC   (0x1UL << 2)
#define	DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
#define	DMA_CHREQMASKC_CH3REQMASKC   (0x1UL << 3)
#define	DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
#define	DMA_CHREQMASKC_CH4REQMASKC   (0x1UL << 4)
#define	DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
#define	DMA_CHREQMASKC_CH5REQMASKC   (0x1UL << 5)
#define	DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
#define	DMA_CHREQMASKC_CH6REQMASKC   (0x1UL << 6)
#define	DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
#define	DMA_CHREQMASKC_CH7REQMASKC   (0x1UL << 7)
#define	DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
#define	DMA_CHREQMASKC_CH8REQMASKC   (0x1UL << 8)
#define	DMA_CHREQMASKC_CH8REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8)
#define	DMA_CHREQMASKC_CH9REQMASKC   (0x1UL << 9)
#define	DMA_CHREQMASKC_CH9REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9)
#define	DMA_CHREQMASKS_CH0REQMASKS   (0x1UL << 0)
#define	DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
#define	DMA_CHREQMASKS_CH10REQMASKS   (0x1UL << 10)
#define	DMA_CHREQMASKS_CH10REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10)
#define	DMA_CHREQMASKS_CH11REQMASKS   (0x1UL << 11)
#define	DMA_CHREQMASKS_CH11REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11)
#define	DMA_CHREQMASKS_CH1REQMASKS   (0x1UL << 1)
#define	DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
#define	DMA_CHREQMASKS_CH2REQMASKS   (0x1UL << 2)
#define	DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
#define	DMA_CHREQMASKS_CH3REQMASKS   (0x1UL << 3)
#define	DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
#define	DMA_CHREQMASKS_CH4REQMASKS   (0x1UL << 4)
#define	DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
#define	DMA_CHREQMASKS_CH5REQMASKS   (0x1UL << 5)
#define	DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
#define	DMA_CHREQMASKS_CH6REQMASKS   (0x1UL << 6)
#define	DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
#define	DMA_CHREQMASKS_CH7REQMASKS   (0x1UL << 7)
#define	DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
#define	DMA_CHREQMASKS_CH8REQMASKS   (0x1UL << 8)
#define	DMA_CHREQMASKS_CH8REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8)
#define	DMA_CHREQMASKS_CH9REQMASKS   (0x1UL << 9)
#define	DMA_CHREQMASKS_CH9REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9)
#define	DMA_CHREQSTATUS_CH0REQSTATUS   (0x1UL << 0)
#define	DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
#define	DMA_CHREQSTATUS_CH10REQSTATUS   (0x1UL << 10)
#define	DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10)
#define	DMA_CHREQSTATUS_CH11REQSTATUS   (0x1UL << 11)
#define	DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11)
#define	DMA_CHREQSTATUS_CH1REQSTATUS   (0x1UL << 1)
#define	DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
#define	DMA_CHREQSTATUS_CH2REQSTATUS   (0x1UL << 2)
#define	DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
#define	DMA_CHREQSTATUS_CH3REQSTATUS   (0x1UL << 3)
#define	DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
#define	DMA_CHREQSTATUS_CH4REQSTATUS   (0x1UL << 4)
#define	DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
#define	DMA_CHREQSTATUS_CH5REQSTATUS   (0x1UL << 5)
#define	DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
#define	DMA_CHREQSTATUS_CH6REQSTATUS   (0x1UL << 6)
#define	DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
#define	DMA_CHREQSTATUS_CH7REQSTATUS   (0x1UL << 7)
#define	DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
#define	DMA_CHREQSTATUS_CH8REQSTATUS   (0x1UL << 8)
#define	DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8)
#define	DMA_CHREQSTATUS_CH9REQSTATUS   (0x1UL << 9)
#define	DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9)
#define	DMA_CHSREQSTATUS_CH0SREQSTATUS   (0x1UL << 0)
#define	DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
#define	DMA_CHSREQSTATUS_CH10SREQSTATUS   (0x1UL << 10)
#define	DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10)
#define	DMA_CHSREQSTATUS_CH11SREQSTATUS   (0x1UL << 11)
#define	DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11)
#define	DMA_CHSREQSTATUS_CH1SREQSTATUS   (0x1UL << 1)
#define	DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
#define	DMA_CHSREQSTATUS_CH2SREQSTATUS   (0x1UL << 2)
#define	DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
#define	DMA_CHSREQSTATUS_CH3SREQSTATUS   (0x1UL << 3)
#define	DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
#define	DMA_CHSREQSTATUS_CH4SREQSTATUS   (0x1UL << 4)
#define	DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
#define	DMA_CHSREQSTATUS_CH5SREQSTATUS   (0x1UL << 5)
#define	DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
#define	DMA_CHSREQSTATUS_CH6SREQSTATUS   (0x1UL << 6)
#define	DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
#define	DMA_CHSREQSTATUS_CH7SREQSTATUS   (0x1UL << 7)
#define	DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
#define	DMA_CHSREQSTATUS_CH8SREQSTATUS   (0x1UL << 8)
#define	DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8)
#define	DMA_CHSREQSTATUS_CH9SREQSTATUS   (0x1UL << 9)
#define	DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9)
#define	DMA_CHSWREQ_CH0SWREQ   (0x1UL << 0)
#define	DMA_CHSWREQ_CH0SWREQ_DEFAULT   (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
#define	DMA_CHSWREQ_CH10SWREQ   (0x1UL << 10)
#define	DMA_CHSWREQ_CH10SWREQ_DEFAULT   (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10)
#define	DMA_CHSWREQ_CH11SWREQ   (0x1UL << 11)
#define	DMA_CHSWREQ_CH11SWREQ_DEFAULT   (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11)
#define	DMA_CHSWREQ_CH1SWREQ   (0x1UL << 1)
#define	DMA_CHSWREQ_CH1SWREQ_DEFAULT   (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
#define	DMA_CHSWREQ_CH2SWREQ   (0x1UL << 2)
#define	DMA_CHSWREQ_CH2SWREQ_DEFAULT   (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
#define	DMA_CHSWREQ_CH3SWREQ   (0x1UL << 3)
#define	DMA_CHSWREQ_CH3SWREQ_DEFAULT   (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
#define	DMA_CHSWREQ_CH4SWREQ   (0x1UL << 4)
#define	DMA_CHSWREQ_CH4SWREQ_DEFAULT   (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
#define	DMA_CHSWREQ_CH5SWREQ   (0x1UL << 5)
#define	DMA_CHSWREQ_CH5SWREQ_DEFAULT   (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
#define	DMA_CHSWREQ_CH6SWREQ   (0x1UL << 6)
#define	DMA_CHSWREQ_CH6SWREQ_DEFAULT   (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
#define	DMA_CHSWREQ_CH7SWREQ   (0x1UL << 7)
#define	DMA_CHSWREQ_CH7SWREQ_DEFAULT   (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
#define	DMA_CHSWREQ_CH8SWREQ   (0x1UL << 8)
#define	DMA_CHSWREQ_CH8SWREQ_DEFAULT   (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8)
#define	DMA_CHSWREQ_CH9SWREQ   (0x1UL << 9)
#define	DMA_CHSWREQ_CH9SWREQ_DEFAULT   (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9)
#define	DMA_CHUSEBURSTC_CH08USEBURSTC   (0x1UL << 8)
#define	DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8)
#define	DMA_CHUSEBURSTC_CH0USEBURSTC   (0x1UL << 0)
#define	DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
#define	DMA_CHUSEBURSTC_CH10USEBURSTC   (0x1UL << 10)
#define	DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10)
#define	DMA_CHUSEBURSTC_CH11USEBURSTC   (0x1UL << 11)
#define	DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11)
#define	DMA_CHUSEBURSTC_CH1USEBURSTC   (0x1UL << 1)
#define	DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
#define	DMA_CHUSEBURSTC_CH2USEBURSTC   (0x1UL << 2)
#define	DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
#define	DMA_CHUSEBURSTC_CH3USEBURSTC   (0x1UL << 3)
#define	DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
#define	DMA_CHUSEBURSTC_CH4USEBURSTC   (0x1UL << 4)
#define	DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
#define	DMA_CHUSEBURSTC_CH5USEBURSTC   (0x1UL << 5)
#define	DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
#define	DMA_CHUSEBURSTC_CH6USEBURSTC   (0x1UL << 6)
#define	DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
#define	DMA_CHUSEBURSTC_CH7USEBURSTC   (0x1UL << 7)
#define	DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
#define	DMA_CHUSEBURSTC_CH9USEBURSTC   (0x1UL << 9)
#define	DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS   (0x1UL << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
#define	DMA_CHUSEBURSTS_CH10USEBURSTS   (0x1UL << 10)
#define	DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10)
#define	DMA_CHUSEBURSTS_CH11USEBURSTS   (0x1UL << 11)
#define	DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11)
#define	DMA_CHUSEBURSTS_CH1USEBURSTS   (0x1UL << 1)
#define	DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
#define	DMA_CHUSEBURSTS_CH2USEBURSTS   (0x1UL << 2)
#define	DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
#define	DMA_CHUSEBURSTS_CH3USEBURSTS   (0x1UL << 3)
#define	DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
#define	DMA_CHUSEBURSTS_CH4USEBURSTS   (0x1UL << 4)
#define	DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
#define	DMA_CHUSEBURSTS_CH5USEBURSTS   (0x1UL << 5)
#define	DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
#define	DMA_CHUSEBURSTS_CH6USEBURSTS   (0x1UL << 6)
#define	DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
#define	DMA_CHUSEBURSTS_CH7USEBURSTS   (0x1UL << 7)
#define	DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
#define	DMA_CHUSEBURSTS_CH8USEBURSTS   (0x1UL << 8)
#define	DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8)
#define	DMA_CHUSEBURSTS_CH9USEBURSTS   (0x1UL << 9)
#define	DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9)
#define	DMA_CHWAITSTATUS_CH0WAITSTATUS   (0x1UL << 0)
#define	DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
#define	DMA_CHWAITSTATUS_CH10WAITSTATUS   (0x1UL << 10)
#define	DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10)
#define	DMA_CHWAITSTATUS_CH11WAITSTATUS   (0x1UL << 11)
#define	DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11)
#define	DMA_CHWAITSTATUS_CH1WAITSTATUS   (0x1UL << 1)
#define	DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
#define	DMA_CHWAITSTATUS_CH2WAITSTATUS   (0x1UL << 2)
#define	DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
#define	DMA_CHWAITSTATUS_CH3WAITSTATUS   (0x1UL << 3)
#define	DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
#define	DMA_CHWAITSTATUS_CH4WAITSTATUS   (0x1UL << 4)
#define	DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
#define	DMA_CHWAITSTATUS_CH5WAITSTATUS   (0x1UL << 5)
#define	DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
#define	DMA_CHWAITSTATUS_CH6WAITSTATUS   (0x1UL << 6)
#define	DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
#define	DMA_CHWAITSTATUS_CH7WAITSTATUS   (0x1UL << 7)
#define	DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
#define	DMA_CHWAITSTATUS_CH8WAITSTATUS   (0x1UL << 8)
#define	DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8)
#define	DMA_CHWAITSTATUS_CH9WAITSTATUS   (0x1UL << 9)
#define	DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9)
#define	DMA_CONFIG_CHPROT   (0x1UL << 5)
#define	DMA_CONFIG_CHPROT_DEFAULT   (_DMA_CONFIG_CHPROT_DEFAULT << 5)
#define	DMA_CONFIG_EN   (0x1UL << 0)
#define	DMA_CONFIG_EN_DEFAULT   (_DMA_CONFIG_EN_DEFAULT << 0)
#define	DMA_CTRL_DESCRECT   (0x1UL << 0)
#define	DMA_CTRL_DESCRECT_DEFAULT   (_DMA_CTRL_DESCRECT_DEFAULT << 0)
#define	DMA_CTRL_PRDU   (0x1UL << 1)
#define	DMA_CTRL_PRDU_DEFAULT   (_DMA_CTRL_PRDU_DEFAULT << 1)
#define	DMA_CTRLBASE_CTRLBASE_DEFAULT   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
#define	DMA_ERRORC_ERRORC   (0x1UL << 0)
#define	DMA_ERRORC_ERRORC_DEFAULT   (_DMA_ERRORC_ERRORC_DEFAULT << 0)
#define	DMA_IEN_CH0DONE   (0x1UL << 0)
#define	DMA_IEN_CH0DONE_DEFAULT   (_DMA_IEN_CH0DONE_DEFAULT << 0)
#define	DMA_IEN_CH10DONE   (0x1UL << 10)
#define	DMA_IEN_CH10DONE_DEFAULT   (_DMA_IEN_CH10DONE_DEFAULT << 10)
#define	DMA_IEN_CH11DONE   (0x1UL << 11)
#define	DMA_IEN_CH11DONE_DEFAULT   (_DMA_IEN_CH11DONE_DEFAULT << 11)
#define	DMA_IEN_CH1DONE   (0x1UL << 1)
#define	DMA_IEN_CH1DONE_DEFAULT   (_DMA_IEN_CH1DONE_DEFAULT << 1)
#define	DMA_IEN_CH2DONE   (0x1UL << 2)
#define	DMA_IEN_CH2DONE_DEFAULT   (_DMA_IEN_CH2DONE_DEFAULT << 2)
#define	DMA_IEN_CH3DONE   (0x1UL << 3)
#define	DMA_IEN_CH3DONE_DEFAULT   (_DMA_IEN_CH3DONE_DEFAULT << 3)
#define	DMA_IEN_CH4DONE   (0x1UL << 4)
#define	DMA_IEN_CH4DONE_DEFAULT   (_DMA_IEN_CH4DONE_DEFAULT << 4)
#define	DMA_IEN_CH5DONE   (0x1UL << 5)
#define	DMA_IEN_CH5DONE_DEFAULT   (_DMA_IEN_CH5DONE_DEFAULT << 5)
#define	DMA_IEN_CH6DONE   (0x1UL << 6)
#define	DMA_IEN_CH6DONE_DEFAULT   (_DMA_IEN_CH6DONE_DEFAULT << 6)
#define	DMA_IEN_CH7DONE   (0x1UL << 7)
#define	DMA_IEN_CH7DONE_DEFAULT   (_DMA_IEN_CH7DONE_DEFAULT << 7)
#define	DMA_IEN_CH8DONE   (0x1UL << 8)
#define	DMA_IEN_CH8DONE_DEFAULT   (_DMA_IEN_CH8DONE_DEFAULT << 8)
#define	DMA_IEN_CH9DONE   (0x1UL << 9)
#define	DMA_IEN_CH9DONE_DEFAULT   (_DMA_IEN_CH9DONE_DEFAULT << 9)
#define	DMA_IEN_ERR   (0x1UL << 31)
#define	DMA_IEN_ERR_DEFAULT   (_DMA_IEN_ERR_DEFAULT << 31)
#define	DMA_IF_CH0DONE   (0x1UL << 0)
#define	DMA_IF_CH0DONE_DEFAULT   (_DMA_IF_CH0DONE_DEFAULT << 0)
#define	DMA_IF_CH10DONE   (0x1UL << 10)
#define	DMA_IF_CH10DONE_DEFAULT   (_DMA_IF_CH10DONE_DEFAULT << 10)
#define	DMA_IF_CH11DONE   (0x1UL << 11)
#define	DMA_IF_CH11DONE_DEFAULT   (_DMA_IF_CH11DONE_DEFAULT << 11)
#define	DMA_IF_CH1DONE   (0x1UL << 1)
#define	DMA_IF_CH1DONE_DEFAULT   (_DMA_IF_CH1DONE_DEFAULT << 1)
#define	DMA_IF_CH2DONE   (0x1UL << 2)
#define	DMA_IF_CH2DONE_DEFAULT   (_DMA_IF_CH2DONE_DEFAULT << 2)
#define	DMA_IF_CH3DONE   (0x1UL << 3)
#define	DMA_IF_CH3DONE_DEFAULT   (_DMA_IF_CH3DONE_DEFAULT << 3)
#define	DMA_IF_CH4DONE   (0x1UL << 4)
#define	DMA_IF_CH4DONE_DEFAULT   (_DMA_IF_CH4DONE_DEFAULT << 4)
#define	DMA_IF_CH5DONE   (0x1UL << 5)
#define	DMA_IF_CH5DONE_DEFAULT   (_DMA_IF_CH5DONE_DEFAULT << 5)
#define	DMA_IF_CH6DONE   (0x1UL << 6)
#define	DMA_IF_CH6DONE_DEFAULT   (_DMA_IF_CH6DONE_DEFAULT << 6)
#define	DMA_IF_CH7DONE   (0x1UL << 7)
#define	DMA_IF_CH7DONE_DEFAULT   (_DMA_IF_CH7DONE_DEFAULT << 7)
#define	DMA_IF_CH8DONE   (0x1UL << 8)
#define	DMA_IF_CH8DONE_DEFAULT   (_DMA_IF_CH8DONE_DEFAULT << 8)
#define	DMA_IF_CH9DONE   (0x1UL << 9)
#define	DMA_IF_CH9DONE_DEFAULT   (_DMA_IF_CH9DONE_DEFAULT << 9)
#define	DMA_IF_ERR   (0x1UL << 31)
#define	DMA_IF_ERR_DEFAULT   (_DMA_IF_ERR_DEFAULT << 31)
#define	DMA_IFC_CH0DONE   (0x1UL << 0)
#define	DMA_IFC_CH0DONE_DEFAULT   (_DMA_IFC_CH0DONE_DEFAULT << 0)
#define	DMA_IFC_CH10DONE   (0x1UL << 10)
#define	DMA_IFC_CH10DONE_DEFAULT   (_DMA_IFC_CH10DONE_DEFAULT << 10)
#define	DMA_IFC_CH11DONE   (0x1UL << 11)
#define	DMA_IFC_CH11DONE_DEFAULT   (_DMA_IFC_CH11DONE_DEFAULT << 11)
#define	DMA_IFC_CH1DONE   (0x1UL << 1)
#define	DMA_IFC_CH1DONE_DEFAULT   (_DMA_IFC_CH1DONE_DEFAULT << 1)
#define	DMA_IFC_CH2DONE   (0x1UL << 2)
#define	DMA_IFC_CH2DONE_DEFAULT   (_DMA_IFC_CH2DONE_DEFAULT << 2)
#define	DMA_IFC_CH3DONE   (0x1UL << 3)
#define	DMA_IFC_CH3DONE_DEFAULT   (_DMA_IFC_CH3DONE_DEFAULT << 3)
#define	DMA_IFC_CH4DONE   (0x1UL << 4)
#define	DMA_IFC_CH4DONE_DEFAULT   (_DMA_IFC_CH4DONE_DEFAULT << 4)
#define	DMA_IFC_CH5DONE   (0x1UL << 5)
#define	DMA_IFC_CH5DONE_DEFAULT   (_DMA_IFC_CH5DONE_DEFAULT << 5)
#define	DMA_IFC_CH6DONE   (0x1UL << 6)
#define	DMA_IFC_CH6DONE_DEFAULT   (_DMA_IFC_CH6DONE_DEFAULT << 6)
#define	DMA_IFC_CH7DONE   (0x1UL << 7)
#define	DMA_IFC_CH7DONE_DEFAULT   (_DMA_IFC_CH7DONE_DEFAULT << 7)
#define	DMA_IFC_CH8DONE   (0x1UL << 8)
#define	DMA_IFC_CH8DONE_DEFAULT   (_DMA_IFC_CH8DONE_DEFAULT << 8)
#define	DMA_IFC_CH9DONE   (0x1UL << 9)
#define	DMA_IFC_CH9DONE_DEFAULT   (_DMA_IFC_CH9DONE_DEFAULT << 9)
#define	DMA_IFC_ERR   (0x1UL << 31)
#define	DMA_IFC_ERR_DEFAULT   (_DMA_IFC_ERR_DEFAULT << 31)
#define	DMA_IFS_CH0DONE   (0x1UL << 0)
#define	DMA_IFS_CH0DONE_DEFAULT   (_DMA_IFS_CH0DONE_DEFAULT << 0)
#define	DMA_IFS_CH10DONE   (0x1UL << 10)
#define	DMA_IFS_CH10DONE_DEFAULT   (_DMA_IFS_CH10DONE_DEFAULT << 10)
#define	DMA_IFS_CH11DONE   (0x1UL << 11)
#define	DMA_IFS_CH11DONE_DEFAULT   (_DMA_IFS_CH11DONE_DEFAULT << 11)
#define	DMA_IFS_CH1DONE   (0x1UL << 1)
#define	DMA_IFS_CH1DONE_DEFAULT   (_DMA_IFS_CH1DONE_DEFAULT << 1)
#define	DMA_IFS_CH2DONE   (0x1UL << 2)
#define	DMA_IFS_CH2DONE_DEFAULT   (_DMA_IFS_CH2DONE_DEFAULT << 2)
#define	DMA_IFS_CH3DONE   (0x1UL << 3)
#define	DMA_IFS_CH3DONE_DEFAULT   (_DMA_IFS_CH3DONE_DEFAULT << 3)
#define	DMA_IFS_CH4DONE   (0x1UL << 4)
#define	DMA_IFS_CH4DONE_DEFAULT   (_DMA_IFS_CH4DONE_DEFAULT << 4)
#define	DMA_IFS_CH5DONE   (0x1UL << 5)
#define	DMA_IFS_CH5DONE_DEFAULT   (_DMA_IFS_CH5DONE_DEFAULT << 5)
#define	DMA_IFS_CH6DONE   (0x1UL << 6)
#define	DMA_IFS_CH6DONE_DEFAULT   (_DMA_IFS_CH6DONE_DEFAULT << 6)
#define	DMA_IFS_CH7DONE   (0x1UL << 7)
#define	DMA_IFS_CH7DONE_DEFAULT   (_DMA_IFS_CH7DONE_DEFAULT << 7)
#define	DMA_IFS_CH8DONE   (0x1UL << 8)
#define	DMA_IFS_CH8DONE_DEFAULT   (_DMA_IFS_CH8DONE_DEFAULT << 8)
#define	DMA_IFS_CH9DONE   (0x1UL << 9)
#define	DMA_IFS_CH9DONE_DEFAULT   (_DMA_IFS_CH9DONE_DEFAULT << 9)
#define	DMA_IFS_ERR   (0x1UL << 31)
#define	DMA_IFS_ERR_DEFAULT   (_DMA_IFS_ERR_DEFAULT << 31)
#define	DMA_LOOP0_EN   (0x1UL << 16)
#define	DMA_LOOP0_EN_DEFAULT   (_DMA_LOOP0_EN_DEFAULT << 16)
#define	DMA_LOOP0_WIDTH_DEFAULT   (_DMA_LOOP0_WIDTH_DEFAULT << 0)
#define	DMA_LOOP1_EN   (0x1UL << 16)
#define	DMA_LOOP1_EN_DEFAULT   (_DMA_LOOP1_EN_DEFAULT << 16)
#define	DMA_LOOP1_WIDTH_DEFAULT   (_DMA_LOOP1_WIDTH_DEFAULT << 0)
#define	DMA_RDS_RDSCH0   (0x1UL << 0)
#define	DMA_RDS_RDSCH0_DEFAULT   (_DMA_RDS_RDSCH0_DEFAULT << 0)
#define	DMA_RDS_RDSCH1   (0x1UL << 1)
#define	DMA_RDS_RDSCH10   (0x1UL << 10)
#define	DMA_RDS_RDSCH10_DEFAULT   (_DMA_RDS_RDSCH10_DEFAULT << 10)
#define	DMA_RDS_RDSCH11   (0x1UL << 11)
#define	DMA_RDS_RDSCH11_DEFAULT   (_DMA_RDS_RDSCH11_DEFAULT << 11)
#define	DMA_RDS_RDSCH1_DEFAULT   (_DMA_RDS_RDSCH1_DEFAULT << 1)
#define	DMA_RDS_RDSCH2   (0x1UL << 2)
#define	DMA_RDS_RDSCH2_DEFAULT   (_DMA_RDS_RDSCH2_DEFAULT << 2)
#define	DMA_RDS_RDSCH3   (0x1UL << 3)
#define	DMA_RDS_RDSCH3_DEFAULT   (_DMA_RDS_RDSCH3_DEFAULT << 3)
#define	DMA_RDS_RDSCH4   (0x1UL << 4)
#define	DMA_RDS_RDSCH4_DEFAULT   (_DMA_RDS_RDSCH4_DEFAULT << 4)
#define	DMA_RDS_RDSCH5   (0x1UL << 5)
#define	DMA_RDS_RDSCH5_DEFAULT   (_DMA_RDS_RDSCH5_DEFAULT << 5)
#define	DMA_RDS_RDSCH6   (0x1UL << 6)
#define	DMA_RDS_RDSCH6_DEFAULT   (_DMA_RDS_RDSCH6_DEFAULT << 6)
#define	DMA_RDS_RDSCH7   (0x1UL << 7)
#define	DMA_RDS_RDSCH7_DEFAULT   (_DMA_RDS_RDSCH7_DEFAULT << 7)
#define	DMA_RDS_RDSCH8   (0x1UL << 8)
#define	DMA_RDS_RDSCH8_DEFAULT   (_DMA_RDS_RDSCH8_DEFAULT << 8)
#define	DMA_RDS_RDSCH9   (0x1UL << 9)
#define	DMA_RDS_RDSCH9_DEFAULT   (_DMA_RDS_RDSCH9_DEFAULT << 9)
#define	DMA_RECT0_DSTSTRIDE_DEFAULT   (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21)
#define	DMA_RECT0_HEIGHT_DEFAULT   (_DMA_RECT0_HEIGHT_DEFAULT << 0)
#define	DMA_RECT0_SRCSTRIDE_DEFAULT   (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10)
#define	DMA_STATUS_CHNUM_DEFAULT   (_DMA_STATUS_CHNUM_DEFAULT << 16)
#define	DMA_STATUS_EN   (0x1UL << 0)
#define	DMA_STATUS_EN_DEFAULT   (_DMA_STATUS_EN_DEFAULT << 0)
#define	DMA_STATUS_STATE_DEFAULT   (_DMA_STATUS_STATE_DEFAULT << 4)
#define	DMA_STATUS_STATE_DONE   (_DMA_STATUS_STATE_DONE << 4)
#define	DMA_STATUS_STATE_IDLE   (_DMA_STATUS_STATE_IDLE << 4)
#define	DMA_STATUS_STATE_PERSCATTRANS   (_DMA_STATUS_STATE_PERSCATTRANS << 4)
#define	DMA_STATUS_STATE_RDCHCTRLDATA   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
#define	DMA_STATUS_STATE_RDDSTENDPTR   (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
#define	DMA_STATUS_STATE_RDSRCDATA   (_DMA_STATUS_STATE_RDSRCDATA << 4)
#define	DMA_STATUS_STATE_RDSRCENDPTR   (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
#define	DMA_STATUS_STATE_STALLED   (_DMA_STATUS_STATE_STALLED << 4)
#define	DMA_STATUS_STATE_WAITREQCLR   (_DMA_STATUS_STATE_WAITREQCLR << 4)
#define	DMA_STATUS_STATE_WRCHCTRLDATA   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
#define	DMA_STATUS_STATE_WRDSTDATA   (_DMA_STATUS_STATE_WRDSTDATA << 4)

Macro Definition Documentation

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   0x00000100UL

Mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 156 of file ezr32wg_dma.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK   0xFFFFFFFFUL

Bit mask for DMA_ALTCTRLBASE

Definition at line 155 of file ezr32wg_dma.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT   0

Shift value for DMA_ALTCTRLBASE

Definition at line 154 of file ezr32wg_dma.h.

#define _DMA_ALTCTRLBASE_MASK   0xFFFFFFFFUL

Mask for DMA_ALTCTRLBASE

Definition at line 153 of file ezr32wg_dma.h.

#define _DMA_ALTCTRLBASE_RESETVALUE   0x00000100UL

Default value for DMA_ALTCTRLBASE

Definition at line 152 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_MASK   0x003F000FUL

Mask for DMA_CH_CTRL

Definition at line 1466 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_RESETVALUE   0x00000000UL

Default value for DMA_CH_CTRL

Definition at line 1465 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN   0x00000001UL

Mode ADC0SCAN for DMA_CH_CTRL

Definition at line 1487 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE   0x00000000UL

Mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 1469 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATARD   0x00000002UL

Mode AESDATARD for DMA_CH_CTRL

Definition at line 1514 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATAWR   0x00000000UL

Mode AESDATAWR for DMA_CH_CTRL

Definition at line 1485 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESKEYWR   0x00000003UL

Mode AESKEYWR for DMA_CH_CTRL

Definition at line 1521 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR   0x00000001UL

Mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 1502 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_DAC0CH0   0x00000000UL

Mode DAC0CH0 for DMA_CH_CTRL

Definition at line 1470 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_DAC0CH1   0x00000001UL

Mode DAC0CH1 for DMA_CH_CTRL

Definition at line 1488 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   0x00000000UL

Mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 1476 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL   0x00000001UL

Mode I2C0TXBL for DMA_CH_CTRL

Definition at line 1494 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV   0x00000000UL

Mode I2C1RXDATAV for DMA_CH_CTRL

Definition at line 1477 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL   0x00000001UL

Mode I2C1TXBL for DMA_CH_CTRL

Definition at line 1495 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV   0x00000000UL

Mode LESENSEBUFDATAV for DMA_CH_CTRL

Definition at line 1486 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   0x00000000UL

Mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 1474 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL   0x00000001UL

Mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 1492 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   0x00000002UL

Mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 1506 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   0x00000000UL

Mode LEUART1RXDATAV for DMA_CH_CTRL

Definition at line 1475 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL   0x00000001UL

Mode LEUART1TXBL for DMA_CH_CTRL

Definition at line 1493 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   0x00000002UL

Mode LEUART1TXEMPTY for DMA_CH_CTRL

Definition at line 1507 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_MASK   0xFUL

Bit mask for DMA_SIGSEL

Definition at line 1468 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_MSCWDATA   0x00000000UL

Mode MSCWDATA for DMA_CH_CTRL

Definition at line 1484 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_SHIFT   0

Shift value for DMA_SIGSEL

Definition at line 1467 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0   0x00000001UL

Mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 1496 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1   0x00000002UL

Mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 1508 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2   0x00000003UL

Mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 1517 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF   0x00000000UL

Mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 1478 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0   0x00000001UL

Mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 1497 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1   0x00000002UL

Mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 1509 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2   0x00000003UL

Mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 1518 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF   0x00000000UL

Mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 1479 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0   0x00000001UL

Mode TIMER2CC0 for DMA_CH_CTRL

Definition at line 1498 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1   0x00000002UL

Mode TIMER2CC1 for DMA_CH_CTRL

Definition at line 1510 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2   0x00000003UL

Mode TIMER2CC2 for DMA_CH_CTRL

Definition at line 1519 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF   0x00000000UL

Mode TIMER2UFOF for DMA_CH_CTRL

Definition at line 1480 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0   0x00000001UL

Mode TIMER3CC0 for DMA_CH_CTRL

Definition at line 1499 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1   0x00000002UL

Mode TIMER3CC1 for DMA_CH_CTRL

Definition at line 1511 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2   0x00000003UL

Mode TIMER3CC2 for DMA_CH_CTRL

Definition at line 1520 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF   0x00000000UL

Mode TIMER3UFOF for DMA_CH_CTRL

Definition at line 1481 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV   0x00000000UL

Mode UART0RXDATAV for DMA_CH_CTRL

Definition at line 1482 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_UART0TXBL   0x00000001UL

Mode UART0TXBL for DMA_CH_CTRL

Definition at line 1500 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   0x00000002UL

Mode UART0TXEMPTY for DMA_CH_CTRL

Definition at line 1512 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV   0x00000000UL

Mode UART1RXDATAV for DMA_CH_CTRL

Definition at line 1483 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_UART1TXBL   0x00000001UL

Mode UART1TXBL for DMA_CH_CTRL

Definition at line 1501 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY   0x00000002UL

Mode UART1TXEMPTY for DMA_CH_CTRL

Definition at line 1513 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV   0x00000000UL

Mode USART1RXDATAV for DMA_CH_CTRL

Definition at line 1472 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   0x00000003UL

Mode USART1RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 1515 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXBL   0x00000001UL

Mode USART1TXBL for DMA_CH_CTRL

Definition at line 1490 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   0x00000004UL

Mode USART1TXBLRIGHT for DMA_CH_CTRL

Definition at line 1522 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   0x00000002UL

Mode USART1TXEMPTY for DMA_CH_CTRL

Definition at line 1504 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV   0x00000000UL

Mode USART2RXDATAV for DMA_CH_CTRL

Definition at line 1473 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT   0x00000003UL

Mode USART2RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 1516 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART2TXBL   0x00000001UL

Mode USART2TXBL for DMA_CH_CTRL

Definition at line 1491 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT   0x00000004UL

Mode USART2TXBLRIGHT for DMA_CH_CTRL

Definition at line 1523 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   0x00000002UL

Mode USART2TXEMPTY for DMA_CH_CTRL

Definition at line 1505 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV   0x00000000UL

Mode USARTRF0RXDATAV for DMA_CH_CTRL

Definition at line 1471 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF0TXBL   0x00000001UL

Mode USARTRF0TXBL for DMA_CH_CTRL

Definition at line 1489 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY   0x00000002UL

Mode USARTRF0TXEMPTY for DMA_CH_CTRL

Definition at line 1503 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_ADC0   0x00000008UL

Mode ADC0 for DMA_CH_CTRL

Definition at line 1582 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_AES   0x00000031UL

Mode AES for DMA_CH_CTRL

Definition at line 1598 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_DAC0   0x0000000AUL

Mode DAC0 for DMA_CH_CTRL

Definition at line 1583 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_I2C0   0x00000014UL

Mode I2C0 for DMA_CH_CTRL

Definition at line 1589 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_I2C1   0x00000015UL

Mode I2C1 for DMA_CH_CTRL

Definition at line 1590 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_LESENSE   0x00000032UL

Mode LESENSE for DMA_CH_CTRL

Definition at line 1599 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_LEUART0   0x00000010UL

Mode LEUART0 for DMA_CH_CTRL

Definition at line 1587 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_LEUART1   0x00000011UL

Mode LEUART1 for DMA_CH_CTRL

Definition at line 1588 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_MASK   0x3F0000UL

Bit mask for DMA_SOURCESEL

Definition at line 1580 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_MSC   0x00000030UL

Mode MSC for DMA_CH_CTRL

Definition at line 1597 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_NONE   0x00000000UL

Mode NONE for DMA_CH_CTRL

Definition at line 1581 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_SHIFT   16

Shift value for DMA_SOURCESEL

Definition at line 1579 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER0   0x00000018UL

Mode TIMER0 for DMA_CH_CTRL

Definition at line 1591 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER1   0x00000019UL

Mode TIMER1 for DMA_CH_CTRL

Definition at line 1592 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER2   0x0000001AUL

Mode TIMER2 for DMA_CH_CTRL

Definition at line 1593 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER3   0x0000001BUL

Mode TIMER3 for DMA_CH_CTRL

Definition at line 1594 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_UART0   0x0000002CUL

Mode UART0 for DMA_CH_CTRL

Definition at line 1595 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_UART1   0x0000002DUL

Mode UART1 for DMA_CH_CTRL

Definition at line 1596 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_USART1   0x0000000DUL

Mode USART1 for DMA_CH_CTRL

Definition at line 1585 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_USART2   0x0000000EUL

Mode USART2 for DMA_CH_CTRL

Definition at line 1586 of file ezr32wg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_USARTRF0   0x0000000CUL

Mode USARTRF0 for DMA_CH_CTRL

Definition at line 1584 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH0ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 745 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH0ALTC_MASK   0x1UL

Bit mask for DMA_CH0ALTC

Definition at line 744 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH0ALTC_SHIFT   0

Shift value for DMA_CH0ALTC

Definition at line 743 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH10ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 795 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH10ALTC_MASK   0x400UL

Bit mask for DMA_CH10ALTC

Definition at line 794 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH10ALTC_SHIFT   10

Shift value for DMA_CH10ALTC

Definition at line 793 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH11ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 800 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH11ALTC_MASK   0x800UL

Bit mask for DMA_CH11ALTC

Definition at line 799 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH11ALTC_SHIFT   11

Shift value for DMA_CH11ALTC

Definition at line 798 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH1ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 750 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH1ALTC_MASK   0x2UL

Bit mask for DMA_CH1ALTC

Definition at line 749 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH1ALTC_SHIFT   1

Shift value for DMA_CH1ALTC

Definition at line 748 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH2ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 755 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH2ALTC_MASK   0x4UL

Bit mask for DMA_CH2ALTC

Definition at line 754 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH2ALTC_SHIFT   2

Shift value for DMA_CH2ALTC

Definition at line 753 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH3ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 760 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH3ALTC_MASK   0x8UL

Bit mask for DMA_CH3ALTC

Definition at line 759 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH3ALTC_SHIFT   3

Shift value for DMA_CH3ALTC

Definition at line 758 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH4ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 765 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH4ALTC_MASK   0x10UL

Bit mask for DMA_CH4ALTC

Definition at line 764 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH4ALTC_SHIFT   4

Shift value for DMA_CH4ALTC

Definition at line 763 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH5ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 770 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH5ALTC_MASK   0x20UL

Bit mask for DMA_CH5ALTC

Definition at line 769 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH5ALTC_SHIFT   5

Shift value for DMA_CH5ALTC

Definition at line 768 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH6ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 775 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH6ALTC_MASK   0x40UL

Bit mask for DMA_CH6ALTC

Definition at line 774 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH6ALTC_SHIFT   6

Shift value for DMA_CH6ALTC

Definition at line 773 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH7ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 780 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH7ALTC_MASK   0x80UL

Bit mask for DMA_CH7ALTC

Definition at line 779 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH7ALTC_SHIFT   7

Shift value for DMA_CH7ALTC

Definition at line 778 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH8ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 785 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH8ALTC_MASK   0x100UL

Bit mask for DMA_CH8ALTC

Definition at line 784 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH8ALTC_SHIFT   8

Shift value for DMA_CH8ALTC

Definition at line 783 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH9ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 790 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH9ALTC_MASK   0x200UL

Bit mask for DMA_CH9ALTC

Definition at line 789 of file ezr32wg_dma.h.

#define _DMA_CHALTC_CH9ALTC_SHIFT   9

Shift value for DMA_CH9ALTC

Definition at line 788 of file ezr32wg_dma.h.

#define _DMA_CHALTC_MASK   0x00000FFFUL

Mask for DMA_CHALTC

Definition at line 741 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHALTC_RESETVALUE   0x00000000UL

Default value for DMA_CHALTC

Definition at line 740 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH0ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 681 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH0ALTS_MASK   0x1UL

Bit mask for DMA_CH0ALTS

Definition at line 680 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH0ALTS_SHIFT   0

Shift value for DMA_CH0ALTS

Definition at line 679 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH10ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 731 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH10ALTS_MASK   0x400UL

Bit mask for DMA_CH10ALTS

Definition at line 730 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH10ALTS_SHIFT   10

Shift value for DMA_CH10ALTS

Definition at line 729 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH11ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 736 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH11ALTS_MASK   0x800UL

Bit mask for DMA_CH11ALTS

Definition at line 735 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH11ALTS_SHIFT   11

Shift value for DMA_CH11ALTS

Definition at line 734 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH1ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 686 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH1ALTS_MASK   0x2UL

Bit mask for DMA_CH1ALTS

Definition at line 685 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH1ALTS_SHIFT   1

Shift value for DMA_CH1ALTS

Definition at line 684 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH2ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 691 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH2ALTS_MASK   0x4UL

Bit mask for DMA_CH2ALTS

Definition at line 690 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH2ALTS_SHIFT   2

Shift value for DMA_CH2ALTS

Definition at line 689 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH3ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 696 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH3ALTS_MASK   0x8UL

Bit mask for DMA_CH3ALTS

Definition at line 695 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH3ALTS_SHIFT   3

Shift value for DMA_CH3ALTS

Definition at line 694 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH4ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 701 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH4ALTS_MASK   0x10UL

Bit mask for DMA_CH4ALTS

Definition at line 700 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH4ALTS_SHIFT   4

Shift value for DMA_CH4ALTS

Definition at line 699 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH5ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 706 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH5ALTS_MASK   0x20UL

Bit mask for DMA_CH5ALTS

Definition at line 705 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH5ALTS_SHIFT   5

Shift value for DMA_CH5ALTS

Definition at line 704 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH6ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 711 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH6ALTS_MASK   0x40UL

Bit mask for DMA_CH6ALTS

Definition at line 710 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH6ALTS_SHIFT   6

Shift value for DMA_CH6ALTS

Definition at line 709 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH7ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 716 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH7ALTS_MASK   0x80UL

Bit mask for DMA_CH7ALTS

Definition at line 715 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH7ALTS_SHIFT   7

Shift value for DMA_CH7ALTS

Definition at line 714 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH8ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 721 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH8ALTS_MASK   0x100UL

Bit mask for DMA_CH8ALTS

Definition at line 720 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH8ALTS_SHIFT   8

Shift value for DMA_CH8ALTS

Definition at line 719 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH9ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 726 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH9ALTS_MASK   0x200UL

Bit mask for DMA_CH9ALTS

Definition at line 725 of file ezr32wg_dma.h.

#define _DMA_CHALTS_CH9ALTS_SHIFT   9

Shift value for DMA_CH9ALTS

Definition at line 724 of file ezr32wg_dma.h.

#define _DMA_CHALTS_MASK   0x00000FFFUL

Mask for DMA_CHALTS

Definition at line 677 of file ezr32wg_dma.h.

#define _DMA_CHALTS_RESETVALUE   0x00000000UL

Default value for DMA_CHALTS

Definition at line 676 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH0ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 617 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH0ENC_MASK   0x1UL

Bit mask for DMA_CH0ENC

Definition at line 616 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH0ENC_SHIFT   0

Shift value for DMA_CH0ENC

Definition at line 615 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH10ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 667 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH10ENC_MASK   0x400UL

Bit mask for DMA_CH10ENC

Definition at line 666 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH10ENC_SHIFT   10

Shift value for DMA_CH10ENC

Definition at line 665 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH11ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 672 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH11ENC_MASK   0x800UL

Bit mask for DMA_CH11ENC

Definition at line 671 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH11ENC_SHIFT   11

Shift value for DMA_CH11ENC

Definition at line 670 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH1ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 622 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH1ENC_MASK   0x2UL

Bit mask for DMA_CH1ENC

Definition at line 621 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH1ENC_SHIFT   1

Shift value for DMA_CH1ENC

Definition at line 620 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH2ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 627 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH2ENC_MASK   0x4UL

Bit mask for DMA_CH2ENC

Definition at line 626 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH2ENC_SHIFT   2

Shift value for DMA_CH2ENC

Definition at line 625 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH3ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 632 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH3ENC_MASK   0x8UL

Bit mask for DMA_CH3ENC

Definition at line 631 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH3ENC_SHIFT   3

Shift value for DMA_CH3ENC

Definition at line 630 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH4ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 637 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH4ENC_MASK   0x10UL

Bit mask for DMA_CH4ENC

Definition at line 636 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH4ENC_SHIFT   4

Shift value for DMA_CH4ENC

Definition at line 635 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH5ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 642 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH5ENC_MASK   0x20UL

Bit mask for DMA_CH5ENC

Definition at line 641 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH5ENC_SHIFT   5

Shift value for DMA_CH5ENC

Definition at line 640 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH6ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 647 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH6ENC_MASK   0x40UL

Bit mask for DMA_CH6ENC

Definition at line 646 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH6ENC_SHIFT   6

Shift value for DMA_CH6ENC

Definition at line 645 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH7ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 652 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH7ENC_MASK   0x80UL

Bit mask for DMA_CH7ENC

Definition at line 651 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH7ENC_SHIFT   7

Shift value for DMA_CH7ENC

Definition at line 650 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH8ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 657 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH8ENC_MASK   0x100UL

Bit mask for DMA_CH8ENC

Definition at line 656 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH8ENC_SHIFT   8

Shift value for DMA_CH8ENC

Definition at line 655 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH9ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 662 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH9ENC_MASK   0x200UL

Bit mask for DMA_CH9ENC

Definition at line 661 of file ezr32wg_dma.h.

#define _DMA_CHENC_CH9ENC_SHIFT   9

Shift value for DMA_CH9ENC

Definition at line 660 of file ezr32wg_dma.h.

#define _DMA_CHENC_MASK   0x00000FFFUL

Mask for DMA_CHENC

Definition at line 613 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHENC_RESETVALUE   0x00000000UL

Default value for DMA_CHENC

Definition at line 612 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH0ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 553 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH0ENS_MASK   0x1UL

Bit mask for DMA_CH0ENS

Definition at line 552 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH0ENS_SHIFT   0

Shift value for DMA_CH0ENS

Definition at line 551 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH10ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 603 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH10ENS_MASK   0x400UL

Bit mask for DMA_CH10ENS

Definition at line 602 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH10ENS_SHIFT   10

Shift value for DMA_CH10ENS

Definition at line 601 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH11ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 608 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH11ENS_MASK   0x800UL

Bit mask for DMA_CH11ENS

Definition at line 607 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH11ENS_SHIFT   11

Shift value for DMA_CH11ENS

Definition at line 606 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH1ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 558 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH1ENS_MASK   0x2UL

Bit mask for DMA_CH1ENS

Definition at line 557 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH1ENS_SHIFT   1

Shift value for DMA_CH1ENS

Definition at line 556 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH2ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 563 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH2ENS_MASK   0x4UL

Bit mask for DMA_CH2ENS

Definition at line 562 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH2ENS_SHIFT   2

Shift value for DMA_CH2ENS

Definition at line 561 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH3ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 568 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH3ENS_MASK   0x8UL

Bit mask for DMA_CH3ENS

Definition at line 567 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH3ENS_SHIFT   3

Shift value for DMA_CH3ENS

Definition at line 566 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH4ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 573 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH4ENS_MASK   0x10UL

Bit mask for DMA_CH4ENS

Definition at line 572 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH4ENS_SHIFT   4

Shift value for DMA_CH4ENS

Definition at line 571 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH5ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 578 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH5ENS_MASK   0x20UL

Bit mask for DMA_CH5ENS

Definition at line 577 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH5ENS_SHIFT   5

Shift value for DMA_CH5ENS

Definition at line 576 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH6ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 583 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH6ENS_MASK   0x40UL

Bit mask for DMA_CH6ENS

Definition at line 582 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH6ENS_SHIFT   6

Shift value for DMA_CH6ENS

Definition at line 581 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH7ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 588 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH7ENS_MASK   0x80UL

Bit mask for DMA_CH7ENS

Definition at line 587 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH7ENS_SHIFT   7

Shift value for DMA_CH7ENS

Definition at line 586 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH8ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 593 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH8ENS_MASK   0x100UL

Bit mask for DMA_CH8ENS

Definition at line 592 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH8ENS_SHIFT   8

Shift value for DMA_CH8ENS

Definition at line 591 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH9ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 598 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH9ENS_MASK   0x200UL

Bit mask for DMA_CH9ENS

Definition at line 597 of file ezr32wg_dma.h.

#define _DMA_CHENS_CH9ENS_SHIFT   9

Shift value for DMA_CH9ENS

Definition at line 596 of file ezr32wg_dma.h.

#define _DMA_CHENS_MASK   0x00000FFFUL

Mask for DMA_CHENS

Definition at line 549 of file ezr32wg_dma.h.

#define _DMA_CHENS_RESETVALUE   0x00000000UL

Default value for DMA_CHENS

Definition at line 548 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 873 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_MASK   0x1UL

Bit mask for DMA_CH0PRIC

Definition at line 872 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_SHIFT   0

Shift value for DMA_CH0PRIC

Definition at line 871 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH10PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 923 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH10PRIC_MASK   0x400UL

Bit mask for DMA_CH10PRIC

Definition at line 922 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH10PRIC_SHIFT   10

Shift value for DMA_CH10PRIC

Definition at line 921 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH11PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 928 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH11PRIC_MASK   0x800UL

Bit mask for DMA_CH11PRIC

Definition at line 927 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH11PRIC_SHIFT   11

Shift value for DMA_CH11PRIC

Definition at line 926 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 878 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_MASK   0x2UL

Bit mask for DMA_CH1PRIC

Definition at line 877 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_SHIFT   1

Shift value for DMA_CH1PRIC

Definition at line 876 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 883 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_MASK   0x4UL

Bit mask for DMA_CH2PRIC

Definition at line 882 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_SHIFT   2

Shift value for DMA_CH2PRIC

Definition at line 881 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 888 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_MASK   0x8UL

Bit mask for DMA_CH3PRIC

Definition at line 887 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_SHIFT   3

Shift value for DMA_CH3PRIC

Definition at line 886 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH4PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 893 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH4PRIC_MASK   0x10UL

Bit mask for DMA_CH4PRIC

Definition at line 892 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH4PRIC_SHIFT   4

Shift value for DMA_CH4PRIC

Definition at line 891 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH5PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 898 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH5PRIC_MASK   0x20UL

Bit mask for DMA_CH5PRIC

Definition at line 897 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH5PRIC_SHIFT   5

Shift value for DMA_CH5PRIC

Definition at line 896 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH6PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 903 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH6PRIC_MASK   0x40UL

Bit mask for DMA_CH6PRIC

Definition at line 902 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH6PRIC_SHIFT   6

Shift value for DMA_CH6PRIC

Definition at line 901 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH7PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 908 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH7PRIC_MASK   0x80UL

Bit mask for DMA_CH7PRIC

Definition at line 907 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH7PRIC_SHIFT   7

Shift value for DMA_CH7PRIC

Definition at line 906 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH8PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 913 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH8PRIC_MASK   0x100UL

Bit mask for DMA_CH8PRIC

Definition at line 912 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH8PRIC_SHIFT   8

Shift value for DMA_CH8PRIC

Definition at line 911 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH9PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 918 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH9PRIC_MASK   0x200UL

Bit mask for DMA_CH9PRIC

Definition at line 917 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_CH9PRIC_SHIFT   9

Shift value for DMA_CH9PRIC

Definition at line 916 of file ezr32wg_dma.h.

#define _DMA_CHPRIC_MASK   0x00000FFFUL

Mask for DMA_CHPRIC

Definition at line 869 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHPRIC_RESETVALUE   0x00000000UL

Default value for DMA_CHPRIC

Definition at line 868 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 809 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_MASK   0x1UL

Bit mask for DMA_CH0PRIS

Definition at line 808 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_SHIFT   0

Shift value for DMA_CH0PRIS

Definition at line 807 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH10PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 859 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH10PRIS_MASK   0x400UL

Bit mask for DMA_CH10PRIS

Definition at line 858 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH10PRIS_SHIFT   10

Shift value for DMA_CH10PRIS

Definition at line 857 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH11PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 864 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH11PRIS_MASK   0x800UL

Bit mask for DMA_CH11PRIS

Definition at line 863 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH11PRIS_SHIFT   11

Shift value for DMA_CH11PRIS

Definition at line 862 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 814 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_MASK   0x2UL

Bit mask for DMA_CH1PRIS

Definition at line 813 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_SHIFT   1

Shift value for DMA_CH1PRIS

Definition at line 812 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 819 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_MASK   0x4UL

Bit mask for DMA_CH2PRIS

Definition at line 818 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_SHIFT   2

Shift value for DMA_CH2PRIS

Definition at line 817 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 824 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_MASK   0x8UL

Bit mask for DMA_CH3PRIS

Definition at line 823 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_SHIFT   3

Shift value for DMA_CH3PRIS

Definition at line 822 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH4PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 829 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH4PRIS_MASK   0x10UL

Bit mask for DMA_CH4PRIS

Definition at line 828 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH4PRIS_SHIFT   4

Shift value for DMA_CH4PRIS

Definition at line 827 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH5PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 834 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH5PRIS_MASK   0x20UL

Bit mask for DMA_CH5PRIS

Definition at line 833 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH5PRIS_SHIFT   5

Shift value for DMA_CH5PRIS

Definition at line 832 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH6PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 839 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH6PRIS_MASK   0x40UL

Bit mask for DMA_CH6PRIS

Definition at line 838 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH6PRIS_SHIFT   6

Shift value for DMA_CH6PRIS

Definition at line 837 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH7PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 844 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH7PRIS_MASK   0x80UL

Bit mask for DMA_CH7PRIS

Definition at line 843 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH7PRIS_SHIFT   7

Shift value for DMA_CH7PRIS

Definition at line 842 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH8PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 849 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH8PRIS_MASK   0x100UL

Bit mask for DMA_CH8PRIS

Definition at line 848 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH8PRIS_SHIFT   8

Shift value for DMA_CH8PRIS

Definition at line 847 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH9PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 854 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH9PRIS_MASK   0x200UL

Bit mask for DMA_CH9PRIS

Definition at line 853 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_CH9PRIS_SHIFT   9

Shift value for DMA_CH9PRIS

Definition at line 852 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_MASK   0x00000FFFUL

Mask for DMA_CHPRIS

Definition at line 805 of file ezr32wg_dma.h.

#define _DMA_CHPRIS_RESETVALUE   0x00000000UL

Default value for DMA_CHPRIS

Definition at line 804 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 489 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_MASK   0x1UL

Bit mask for DMA_CH0REQMASKC

Definition at line 488 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT   0

Shift value for DMA_CH0REQMASKC

Definition at line 487 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 539 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH10REQMASKC_MASK   0x400UL

Bit mask for DMA_CH10REQMASKC

Definition at line 538 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT   10

Shift value for DMA_CH10REQMASKC

Definition at line 537 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 544 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH11REQMASKC_MASK   0x800UL

Bit mask for DMA_CH11REQMASKC

Definition at line 543 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT   11

Shift value for DMA_CH11REQMASKC

Definition at line 542 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 494 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_MASK   0x2UL

Bit mask for DMA_CH1REQMASKC

Definition at line 493 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT   1

Shift value for DMA_CH1REQMASKC

Definition at line 492 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 499 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_MASK   0x4UL

Bit mask for DMA_CH2REQMASKC

Definition at line 498 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT   2

Shift value for DMA_CH2REQMASKC

Definition at line 497 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 504 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_MASK   0x8UL

Bit mask for DMA_CH3REQMASKC

Definition at line 503 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT   3

Shift value for DMA_CH3REQMASKC

Definition at line 502 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 509 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_MASK   0x10UL

Bit mask for DMA_CH4REQMASKC

Definition at line 508 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT   4

Shift value for DMA_CH4REQMASKC

Definition at line 507 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 514 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_MASK   0x20UL

Bit mask for DMA_CH5REQMASKC

Definition at line 513 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT   5

Shift value for DMA_CH5REQMASKC

Definition at line 512 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 519 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH6REQMASKC_MASK   0x40UL

Bit mask for DMA_CH6REQMASKC

Definition at line 518 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT   6

Shift value for DMA_CH6REQMASKC

Definition at line 517 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 524 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH7REQMASKC_MASK   0x80UL

Bit mask for DMA_CH7REQMASKC

Definition at line 523 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT   7

Shift value for DMA_CH7REQMASKC

Definition at line 522 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 529 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH8REQMASKC_MASK   0x100UL

Bit mask for DMA_CH8REQMASKC

Definition at line 528 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT   8

Shift value for DMA_CH8REQMASKC

Definition at line 527 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 534 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH9REQMASKC_MASK   0x200UL

Bit mask for DMA_CH9REQMASKC

Definition at line 533 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT   9

Shift value for DMA_CH9REQMASKC

Definition at line 532 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKC_MASK   0x00000FFFUL

Mask for DMA_CHREQMASKC

Definition at line 485 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHREQMASKC_RESETVALUE   0x00000000UL

Default value for DMA_CHREQMASKC

Definition at line 484 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 425 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_MASK   0x1UL

Bit mask for DMA_CH0REQMASKS

Definition at line 424 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT   0

Shift value for DMA_CH0REQMASKS

Definition at line 423 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 475 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH10REQMASKS_MASK   0x400UL

Bit mask for DMA_CH10REQMASKS

Definition at line 474 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT   10

Shift value for DMA_CH10REQMASKS

Definition at line 473 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 480 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH11REQMASKS_MASK   0x800UL

Bit mask for DMA_CH11REQMASKS

Definition at line 479 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT   11

Shift value for DMA_CH11REQMASKS

Definition at line 478 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 430 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_MASK   0x2UL

Bit mask for DMA_CH1REQMASKS

Definition at line 429 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT   1

Shift value for DMA_CH1REQMASKS

Definition at line 428 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 435 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_MASK   0x4UL

Bit mask for DMA_CH2REQMASKS

Definition at line 434 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT   2

Shift value for DMA_CH2REQMASKS

Definition at line 433 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 440 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_MASK   0x8UL

Bit mask for DMA_CH3REQMASKS

Definition at line 439 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT   3

Shift value for DMA_CH3REQMASKS

Definition at line 438 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 445 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_MASK   0x10UL

Bit mask for DMA_CH4REQMASKS

Definition at line 444 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT   4

Shift value for DMA_CH4REQMASKS

Definition at line 443 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 450 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_MASK   0x20UL

Bit mask for DMA_CH5REQMASKS

Definition at line 449 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT   5

Shift value for DMA_CH5REQMASKS

Definition at line 448 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 455 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH6REQMASKS_MASK   0x40UL

Bit mask for DMA_CH6REQMASKS

Definition at line 454 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT   6

Shift value for DMA_CH6REQMASKS

Definition at line 453 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 460 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH7REQMASKS_MASK   0x80UL

Bit mask for DMA_CH7REQMASKS

Definition at line 459 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT   7

Shift value for DMA_CH7REQMASKS

Definition at line 458 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 465 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH8REQMASKS_MASK   0x100UL

Bit mask for DMA_CH8REQMASKS

Definition at line 464 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT   8

Shift value for DMA_CH8REQMASKS

Definition at line 463 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 470 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH9REQMASKS_MASK   0x200UL

Bit mask for DMA_CH9REQMASKS

Definition at line 469 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT   9

Shift value for DMA_CH9REQMASKS

Definition at line 468 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_MASK   0x00000FFFUL

Mask for DMA_CHREQMASKS

Definition at line 421 of file ezr32wg_dma.h.

#define _DMA_CHREQMASKS_RESETVALUE   0x00000000UL

Default value for DMA_CHREQMASKS

Definition at line 420 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 946 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK   0x1UL

Bit mask for DMA_CH0REQSTATUS

Definition at line 945 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT   0

Shift value for DMA_CH0REQSTATUS

Definition at line 944 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 996 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK   0x400UL

Bit mask for DMA_CH10REQSTATUS

Definition at line 995 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT   10

Shift value for DMA_CH10REQSTATUS

Definition at line 994 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 1001 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK   0x800UL

Bit mask for DMA_CH11REQSTATUS

Definition at line 1000 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT   11

Shift value for DMA_CH11REQSTATUS

Definition at line 999 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 951 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK   0x2UL

Bit mask for DMA_CH1REQSTATUS

Definition at line 950 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT   1

Shift value for DMA_CH1REQSTATUS

Definition at line 949 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 956 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK   0x4UL

Bit mask for DMA_CH2REQSTATUS

Definition at line 955 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT   2

Shift value for DMA_CH2REQSTATUS

Definition at line 954 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 961 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK   0x8UL

Bit mask for DMA_CH3REQSTATUS

Definition at line 960 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT   3

Shift value for DMA_CH3REQSTATUS

Definition at line 959 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 966 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK   0x10UL

Bit mask for DMA_CH4REQSTATUS

Definition at line 965 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT   4

Shift value for DMA_CH4REQSTATUS

Definition at line 964 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 971 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK   0x20UL

Bit mask for DMA_CH5REQSTATUS

Definition at line 970 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT   5

Shift value for DMA_CH5REQSTATUS

Definition at line 969 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 976 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK   0x40UL

Bit mask for DMA_CH6REQSTATUS

Definition at line 975 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT   6

Shift value for DMA_CH6REQSTATUS

Definition at line 974 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 981 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK   0x80UL

Bit mask for DMA_CH7REQSTATUS

Definition at line 980 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT   7

Shift value for DMA_CH7REQSTATUS

Definition at line 979 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 986 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK   0x100UL

Bit mask for DMA_CH8REQSTATUS

Definition at line 985 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT   8

Shift value for DMA_CH8REQSTATUS

Definition at line 984 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 991 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK   0x200UL

Bit mask for DMA_CH9REQSTATUS

Definition at line 990 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT   9

Shift value for DMA_CH9REQSTATUS

Definition at line 989 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_MASK   0x00000FFFUL

Mask for DMA_CHREQSTATUS

Definition at line 942 of file ezr32wg_dma.h.

#define _DMA_CHREQSTATUS_RESETVALUE   0x00000000UL

Default value for DMA_CHREQSTATUS

Definition at line 941 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1010 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK   0x1UL

Bit mask for DMA_CH0SREQSTATUS

Definition at line 1009 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT   0

Shift value for DMA_CH0SREQSTATUS

Definition at line 1008 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1060 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK   0x400UL

Bit mask for DMA_CH10SREQSTATUS

Definition at line 1059 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT   10

Shift value for DMA_CH10SREQSTATUS

Definition at line 1058 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1065 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK   0x800UL

Bit mask for DMA_CH11SREQSTATUS

Definition at line 1064 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT   11

Shift value for DMA_CH11SREQSTATUS

Definition at line 1063 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1015 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK   0x2UL

Bit mask for DMA_CH1SREQSTATUS

Definition at line 1014 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT   1

Shift value for DMA_CH1SREQSTATUS

Definition at line 1013 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1020 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK   0x4UL

Bit mask for DMA_CH2SREQSTATUS

Definition at line 1019 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT   2

Shift value for DMA_CH2SREQSTATUS

Definition at line 1018 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1025 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK   0x8UL

Bit mask for DMA_CH3SREQSTATUS

Definition at line 1024 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT   3

Shift value for DMA_CH3SREQSTATUS

Definition at line 1023 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1030 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK   0x10UL

Bit mask for DMA_CH4SREQSTATUS

Definition at line 1029 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT   4

Shift value for DMA_CH4SREQSTATUS

Definition at line 1028 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1035 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK   0x20UL

Bit mask for DMA_CH5SREQSTATUS

Definition at line 1034 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT   5

Shift value for DMA_CH5SREQSTATUS

Definition at line 1033 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1040 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK   0x40UL

Bit mask for DMA_CH6SREQSTATUS

Definition at line 1039 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT   6

Shift value for DMA_CH6SREQSTATUS

Definition at line 1038 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1045 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK   0x80UL

Bit mask for DMA_CH7SREQSTATUS

Definition at line 1044 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT   7

Shift value for DMA_CH7SREQSTATUS

Definition at line 1043 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1050 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK   0x100UL

Bit mask for DMA_CH8SREQSTATUS

Definition at line 1049 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT   8

Shift value for DMA_CH8SREQSTATUS

Definition at line 1048 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1055 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK   0x200UL

Bit mask for DMA_CH9SREQSTATUS

Definition at line 1054 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT   9

Shift value for DMA_CH9SREQSTATUS

Definition at line 1053 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_MASK   0x00000FFFUL

Mask for DMA_CHSREQSTATUS

Definition at line 1006 of file ezr32wg_dma.h.

#define _DMA_CHSREQSTATUS_RESETVALUE   0x00000000UL

Default value for DMA_CHSREQSTATUS

Definition at line 1005 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 229 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_MASK   0x1UL

Bit mask for DMA_CH0SWREQ

Definition at line 228 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_SHIFT   0

Shift value for DMA_CH0SWREQ

Definition at line 227 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 279 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH10SWREQ_MASK   0x400UL

Bit mask for DMA_CH10SWREQ

Definition at line 278 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH10SWREQ_SHIFT   10

Shift value for DMA_CH10SWREQ

Definition at line 277 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 284 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH11SWREQ_MASK   0x800UL

Bit mask for DMA_CH11SWREQ

Definition at line 283 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH11SWREQ_SHIFT   11

Shift value for DMA_CH11SWREQ

Definition at line 282 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 234 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_MASK   0x2UL

Bit mask for DMA_CH1SWREQ

Definition at line 233 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_SHIFT   1

Shift value for DMA_CH1SWREQ

Definition at line 232 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 239 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_MASK   0x4UL

Bit mask for DMA_CH2SWREQ

Definition at line 238 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_SHIFT   2

Shift value for DMA_CH2SWREQ

Definition at line 237 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 244 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_MASK   0x8UL

Bit mask for DMA_CH3SWREQ

Definition at line 243 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_SHIFT   3

Shift value for DMA_CH3SWREQ

Definition at line 242 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 249 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH4SWREQ_MASK   0x10UL

Bit mask for DMA_CH4SWREQ

Definition at line 248 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH4SWREQ_SHIFT   4

Shift value for DMA_CH4SWREQ

Definition at line 247 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 254 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH5SWREQ_MASK   0x20UL

Bit mask for DMA_CH5SWREQ

Definition at line 253 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH5SWREQ_SHIFT   5

Shift value for DMA_CH5SWREQ

Definition at line 252 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 259 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH6SWREQ_MASK   0x40UL

Bit mask for DMA_CH6SWREQ

Definition at line 258 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH6SWREQ_SHIFT   6

Shift value for DMA_CH6SWREQ

Definition at line 257 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 264 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH7SWREQ_MASK   0x80UL

Bit mask for DMA_CH7SWREQ

Definition at line 263 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH7SWREQ_SHIFT   7

Shift value for DMA_CH7SWREQ

Definition at line 262 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 269 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH8SWREQ_MASK   0x100UL

Bit mask for DMA_CH8SWREQ

Definition at line 268 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH8SWREQ_SHIFT   8

Shift value for DMA_CH8SWREQ

Definition at line 267 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 274 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH9SWREQ_MASK   0x200UL

Bit mask for DMA_CH9SWREQ

Definition at line 273 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_CH9SWREQ_SHIFT   9

Shift value for DMA_CH9SWREQ

Definition at line 272 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_MASK   0x00000FFFUL

Mask for DMA_CHSWREQ

Definition at line 225 of file ezr32wg_dma.h.

#define _DMA_CHSWREQ_RESETVALUE   0x00000000UL

Default value for DMA_CHSWREQ

Definition at line 224 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 401 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK   0x100UL

Bit mask for DMA_CH08USEBURSTC

Definition at line 400 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT   8

Shift value for DMA_CH08USEBURSTC

Definition at line 399 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 361 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK   0x1UL

Bit mask for DMA_CH0USEBURSTC

Definition at line 360 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT   0

Shift value for DMA_CH0USEBURSTC

Definition at line 359 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 411 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK   0x400UL

Bit mask for DMA_CH10USEBURSTC

Definition at line 410 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT   10

Shift value for DMA_CH10USEBURSTC

Definition at line 409 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 416 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK   0x800UL

Bit mask for DMA_CH11USEBURSTC

Definition at line 415 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT   11

Shift value for DMA_CH11USEBURSTC

Definition at line 414 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 366 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK   0x2UL

Bit mask for DMA_CH1USEBURSTC

Definition at line 365 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT   1

Shift value for DMA_CH1USEBURSTC

Definition at line 364 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 371 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK   0x4UL

Bit mask for DMA_CH2USEBURSTC

Definition at line 370 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT   2

Shift value for DMA_CH2USEBURSTC

Definition at line 369 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 376 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK   0x8UL

Bit mask for DMA_CH3USEBURSTC

Definition at line 375 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT   3

Shift value for DMA_CH3USEBURSTC

Definition at line 374 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 381 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK   0x10UL

Bit mask for DMA_CH4USEBURSTC

Definition at line 380 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT   4

Shift value for DMA_CH4USEBURSTC

Definition at line 379 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 386 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK   0x20UL

Bit mask for DMA_CH5USEBURSTC

Definition at line 385 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT   5

Shift value for DMA_CH5USEBURSTC

Definition at line 384 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 391 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK   0x40UL

Bit mask for DMA_CH6USEBURSTC

Definition at line 390 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT   6

Shift value for DMA_CH6USEBURSTC

Definition at line 389 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 396 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK   0x80UL

Bit mask for DMA_CH7USEBURSTC

Definition at line 395 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT   7

Shift value for DMA_CH7USEBURSTC

Definition at line 394 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 406 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK   0x200UL

Bit mask for DMA_CH9USEBURSTC

Definition at line 405 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT   9

Shift value for DMA_CH9USEBURSTC

Definition at line 404 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTC_MASK   0x00000FFFUL

Mask for DMA_CHUSEBURSTC

Definition at line 357 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHUSEBURSTC_RESETVALUE   0x00000000UL

Default value for DMA_CHUSEBURSTC

Definition at line 356 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   0x00000001UL

Mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 295 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 293 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK   0x1UL

Bit mask for DMA_CH0USEBURSTS

Definition at line 292 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT   0

Shift value for DMA_CH0USEBURSTS

Definition at line 291 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   0x00000000UL

Mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 294 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 347 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK   0x400UL

Bit mask for DMA_CH10USEBURSTS

Definition at line 346 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT   10

Shift value for DMA_CH10USEBURSTS

Definition at line 345 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 352 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK   0x800UL

Bit mask for DMA_CH11USEBURSTS

Definition at line 351 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT   11

Shift value for DMA_CH11USEBURSTS

Definition at line 350 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 302 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK   0x2UL

Bit mask for DMA_CH1USEBURSTS

Definition at line 301 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT   1

Shift value for DMA_CH1USEBURSTS

Definition at line 300 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 307 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK   0x4UL

Bit mask for DMA_CH2USEBURSTS

Definition at line 306 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT   2

Shift value for DMA_CH2USEBURSTS

Definition at line 305 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 312 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK   0x8UL

Bit mask for DMA_CH3USEBURSTS

Definition at line 311 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT   3

Shift value for DMA_CH3USEBURSTS

Definition at line 310 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 317 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK   0x10UL

Bit mask for DMA_CH4USEBURSTS

Definition at line 316 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT   4

Shift value for DMA_CH4USEBURSTS

Definition at line 315 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 322 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK   0x20UL

Bit mask for DMA_CH5USEBURSTS

Definition at line 321 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT   5

Shift value for DMA_CH5USEBURSTS

Definition at line 320 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 327 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK   0x40UL

Bit mask for DMA_CH6USEBURSTS

Definition at line 326 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT   6

Shift value for DMA_CH6USEBURSTS

Definition at line 325 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 332 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK   0x80UL

Bit mask for DMA_CH7USEBURSTS

Definition at line 331 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT   7

Shift value for DMA_CH7USEBURSTS

Definition at line 330 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 337 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK   0x100UL

Bit mask for DMA_CH8USEBURSTS

Definition at line 336 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT   8

Shift value for DMA_CH8USEBURSTS

Definition at line 335 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 342 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK   0x200UL

Bit mask for DMA_CH9USEBURSTS

Definition at line 341 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT   9

Shift value for DMA_CH9USEBURSTS

Definition at line 340 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_MASK   0x00000FFFUL

Mask for DMA_CHUSEBURSTS

Definition at line 289 of file ezr32wg_dma.h.

#define _DMA_CHUSEBURSTS_RESETVALUE   0x00000000UL

Default value for DMA_CHUSEBURSTS

Definition at line 288 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 165 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK   0x1UL

Bit mask for DMA_CH0WAITSTATUS

Definition at line 164 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT   0

Shift value for DMA_CH0WAITSTATUS

Definition at line 163 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 215 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK   0x400UL

Bit mask for DMA_CH10WAITSTATUS

Definition at line 214 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT   10

Shift value for DMA_CH10WAITSTATUS

Definition at line 213 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 220 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK   0x800UL

Bit mask for DMA_CH11WAITSTATUS

Definition at line 219 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT   11

Shift value for DMA_CH11WAITSTATUS

Definition at line 218 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 170 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK   0x2UL

Bit mask for DMA_CH1WAITSTATUS

Definition at line 169 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT   1

Shift value for DMA_CH1WAITSTATUS

Definition at line 168 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 175 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK   0x4UL

Bit mask for DMA_CH2WAITSTATUS

Definition at line 174 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT   2

Shift value for DMA_CH2WAITSTATUS

Definition at line 173 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 180 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK   0x8UL

Bit mask for DMA_CH3WAITSTATUS

Definition at line 179 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT   3

Shift value for DMA_CH3WAITSTATUS

Definition at line 178 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 185 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK   0x10UL

Bit mask for DMA_CH4WAITSTATUS

Definition at line 184 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT   4

Shift value for DMA_CH4WAITSTATUS

Definition at line 183 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 190 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK   0x20UL

Bit mask for DMA_CH5WAITSTATUS

Definition at line 189 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT   5

Shift value for DMA_CH5WAITSTATUS

Definition at line 188 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 195 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK   0x40UL

Bit mask for DMA_CH6WAITSTATUS

Definition at line 194 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT   6

Shift value for DMA_CH6WAITSTATUS

Definition at line 193 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 200 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK   0x80UL

Bit mask for DMA_CH7WAITSTATUS

Definition at line 199 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT   7

Shift value for DMA_CH7WAITSTATUS

Definition at line 198 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 205 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK   0x100UL

Bit mask for DMA_CH8WAITSTATUS

Definition at line 204 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT   8

Shift value for DMA_CH8WAITSTATUS

Definition at line 203 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 210 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK   0x200UL

Bit mask for DMA_CH9WAITSTATUS

Definition at line 209 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT   9

Shift value for DMA_CH9WAITSTATUS

Definition at line 208 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_MASK   0x00000FFFUL

Mask for DMA_CHWAITSTATUS

Definition at line 161 of file ezr32wg_dma.h.

#define _DMA_CHWAITSTATUS_RESETVALUE   0x00000FFFUL

Default value for DMA_CHWAITSTATUS

Definition at line 160 of file ezr32wg_dma.h.

#define _DMA_CONFIG_CHPROT_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 140 of file ezr32wg_dma.h.

#define _DMA_CONFIG_CHPROT_MASK   0x20UL

Bit mask for DMA_CHPROT

Definition at line 139 of file ezr32wg_dma.h.

#define _DMA_CONFIG_CHPROT_SHIFT   5

Shift value for DMA_CHPROT

Definition at line 138 of file ezr32wg_dma.h.

Referenced by DMA_Init().

#define _DMA_CONFIG_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 135 of file ezr32wg_dma.h.

#define _DMA_CONFIG_EN_MASK   0x1UL

Bit mask for DMA_EN

Definition at line 134 of file ezr32wg_dma.h.

#define _DMA_CONFIG_EN_SHIFT   0

Shift value for DMA_EN

Definition at line 133 of file ezr32wg_dma.h.

#define _DMA_CONFIG_MASK   0x00000021UL

Mask for DMA_CONFIG

Definition at line 131 of file ezr32wg_dma.h.

#define _DMA_CONFIG_RESETVALUE   0x00000000UL

Default value for DMA_CONFIG

Definition at line 130 of file ezr32wg_dma.h.

Referenced by DMA_Reset(), and DMADRV_DeInit().

#define _DMA_CTRL_DESCRECT_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CTRL

Definition at line 1350 of file ezr32wg_dma.h.

#define _DMA_CTRL_DESCRECT_MASK   0x1UL

Bit mask for DMA_DESCRECT

Definition at line 1349 of file ezr32wg_dma.h.

#define _DMA_CTRL_DESCRECT_SHIFT   0

Shift value for DMA_DESCRECT

Definition at line 1348 of file ezr32wg_dma.h.

#define _DMA_CTRL_MASK   0x00000003UL

Mask for DMA_CTRL

Definition at line 1346 of file ezr32wg_dma.h.

#define _DMA_CTRL_PRDU_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CTRL

Definition at line 1355 of file ezr32wg_dma.h.

#define _DMA_CTRL_PRDU_MASK   0x2UL

Bit mask for DMA_PRDU

Definition at line 1354 of file ezr32wg_dma.h.

#define _DMA_CTRL_PRDU_SHIFT   1

Shift value for DMA_PRDU

Definition at line 1353 of file ezr32wg_dma.h.

#define _DMA_CTRL_RESETVALUE   0x00000000UL

Default value for DMA_CTRL

Definition at line 1345 of file ezr32wg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CTRLBASE

Definition at line 148 of file ezr32wg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_MASK   0xFFFFFFFFUL

Bit mask for DMA_CTRLBASE

Definition at line 147 of file ezr32wg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_SHIFT   0

Shift value for DMA_CTRLBASE

Definition at line 146 of file ezr32wg_dma.h.

#define _DMA_CTRLBASE_MASK   0xFFFFFFFFUL

Mask for DMA_CTRLBASE

Definition at line 145 of file ezr32wg_dma.h.

#define _DMA_CTRLBASE_RESETVALUE   0x00000000UL

Default value for DMA_CTRLBASE

Definition at line 144 of file ezr32wg_dma.h.

#define _DMA_ERRORC_ERRORC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_ERRORC

Definition at line 937 of file ezr32wg_dma.h.

#define _DMA_ERRORC_ERRORC_MASK   0x1UL

Bit mask for DMA_ERRORC

Definition at line 936 of file ezr32wg_dma.h.

#define _DMA_ERRORC_ERRORC_SHIFT   0

Shift value for DMA_ERRORC

Definition at line 935 of file ezr32wg_dma.h.

#define _DMA_ERRORC_MASK   0x00000001UL

Mask for DMA_ERRORC

Definition at line 933 of file ezr32wg_dma.h.

#define _DMA_ERRORC_RESETVALUE   0x00000000UL

Default value for DMA_ERRORC

Definition at line 932 of file ezr32wg_dma.h.

#define _DMA_IEN_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1281 of file ezr32wg_dma.h.

#define _DMA_IEN_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 1280 of file ezr32wg_dma.h.

#define _DMA_IEN_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 1279 of file ezr32wg_dma.h.

#define _DMA_IEN_CH10DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1331 of file ezr32wg_dma.h.

#define _DMA_IEN_CH10DONE_MASK   0x400UL

Bit mask for DMA_CH10DONE

Definition at line 1330 of file ezr32wg_dma.h.

#define _DMA_IEN_CH10DONE_SHIFT   10

Shift value for DMA_CH10DONE

Definition at line 1329 of file ezr32wg_dma.h.

#define _DMA_IEN_CH11DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1336 of file ezr32wg_dma.h.

#define _DMA_IEN_CH11DONE_MASK   0x800UL

Bit mask for DMA_CH11DONE

Definition at line 1335 of file ezr32wg_dma.h.

#define _DMA_IEN_CH11DONE_SHIFT   11

Shift value for DMA_CH11DONE

Definition at line 1334 of file ezr32wg_dma.h.

#define _DMA_IEN_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1286 of file ezr32wg_dma.h.

#define _DMA_IEN_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 1285 of file ezr32wg_dma.h.

#define _DMA_IEN_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 1284 of file ezr32wg_dma.h.

#define _DMA_IEN_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1291 of file ezr32wg_dma.h.

#define _DMA_IEN_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 1290 of file ezr32wg_dma.h.

#define _DMA_IEN_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 1289 of file ezr32wg_dma.h.

#define _DMA_IEN_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1296 of file ezr32wg_dma.h.

#define _DMA_IEN_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 1295 of file ezr32wg_dma.h.

#define _DMA_IEN_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 1294 of file ezr32wg_dma.h.

#define _DMA_IEN_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1301 of file ezr32wg_dma.h.

#define _DMA_IEN_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 1300 of file ezr32wg_dma.h.

#define _DMA_IEN_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 1299 of file ezr32wg_dma.h.

#define _DMA_IEN_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1306 of file ezr32wg_dma.h.

#define _DMA_IEN_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 1305 of file ezr32wg_dma.h.

#define _DMA_IEN_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 1304 of file ezr32wg_dma.h.

#define _DMA_IEN_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1311 of file ezr32wg_dma.h.

#define _DMA_IEN_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 1310 of file ezr32wg_dma.h.

#define _DMA_IEN_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 1309 of file ezr32wg_dma.h.

#define _DMA_IEN_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1316 of file ezr32wg_dma.h.

#define _DMA_IEN_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 1315 of file ezr32wg_dma.h.

#define _DMA_IEN_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 1314 of file ezr32wg_dma.h.

#define _DMA_IEN_CH8DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1321 of file ezr32wg_dma.h.

#define _DMA_IEN_CH8DONE_MASK   0x100UL

Bit mask for DMA_CH8DONE

Definition at line 1320 of file ezr32wg_dma.h.

#define _DMA_IEN_CH8DONE_SHIFT   8

Shift value for DMA_CH8DONE

Definition at line 1319 of file ezr32wg_dma.h.

#define _DMA_IEN_CH9DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1326 of file ezr32wg_dma.h.

#define _DMA_IEN_CH9DONE_MASK   0x200UL

Bit mask for DMA_CH9DONE

Definition at line 1325 of file ezr32wg_dma.h.

#define _DMA_IEN_CH9DONE_SHIFT   9

Shift value for DMA_CH9DONE

Definition at line 1324 of file ezr32wg_dma.h.

#define _DMA_IEN_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 1341 of file ezr32wg_dma.h.

#define _DMA_IEN_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 1340 of file ezr32wg_dma.h.

#define _DMA_IEN_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 1339 of file ezr32wg_dma.h.

#define _DMA_IEN_MASK   0x80000FFFUL

Mask for DMA_IEN

Definition at line 1277 of file ezr32wg_dma.h.

#define _DMA_IEN_RESETVALUE   0x00000000UL

Default value for DMA_IEN

Definition at line 1276 of file ezr32wg_dma.h.

Referenced by DMA_Reset(), and DMADRV_DeInit().

#define _DMA_IF_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1074 of file ezr32wg_dma.h.

#define _DMA_IF_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 1073 of file ezr32wg_dma.h.

#define _DMA_IF_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 1072 of file ezr32wg_dma.h.

#define _DMA_IF_CH10DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1124 of file ezr32wg_dma.h.

#define _DMA_IF_CH10DONE_MASK   0x400UL

Bit mask for DMA_CH10DONE

Definition at line 1123 of file ezr32wg_dma.h.

#define _DMA_IF_CH10DONE_SHIFT   10

Shift value for DMA_CH10DONE

Definition at line 1122 of file ezr32wg_dma.h.

#define _DMA_IF_CH11DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1129 of file ezr32wg_dma.h.

#define _DMA_IF_CH11DONE_MASK   0x800UL

Bit mask for DMA_CH11DONE

Definition at line 1128 of file ezr32wg_dma.h.

#define _DMA_IF_CH11DONE_SHIFT   11

Shift value for DMA_CH11DONE

Definition at line 1127 of file ezr32wg_dma.h.

#define _DMA_IF_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1079 of file ezr32wg_dma.h.

#define _DMA_IF_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 1078 of file ezr32wg_dma.h.

#define _DMA_IF_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 1077 of file ezr32wg_dma.h.

#define _DMA_IF_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1084 of file ezr32wg_dma.h.

#define _DMA_IF_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 1083 of file ezr32wg_dma.h.

#define _DMA_IF_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 1082 of file ezr32wg_dma.h.

#define _DMA_IF_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1089 of file ezr32wg_dma.h.

#define _DMA_IF_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 1088 of file ezr32wg_dma.h.

#define _DMA_IF_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 1087 of file ezr32wg_dma.h.

#define _DMA_IF_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1094 of file ezr32wg_dma.h.

#define _DMA_IF_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 1093 of file ezr32wg_dma.h.

#define _DMA_IF_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 1092 of file ezr32wg_dma.h.

#define _DMA_IF_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1099 of file ezr32wg_dma.h.

#define _DMA_IF_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 1098 of file ezr32wg_dma.h.

#define _DMA_IF_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 1097 of file ezr32wg_dma.h.

#define _DMA_IF_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1104 of file ezr32wg_dma.h.

#define _DMA_IF_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 1103 of file ezr32wg_dma.h.

#define _DMA_IF_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 1102 of file ezr32wg_dma.h.

#define _DMA_IF_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1109 of file ezr32wg_dma.h.

#define _DMA_IF_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 1108 of file ezr32wg_dma.h.

#define _DMA_IF_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 1107 of file ezr32wg_dma.h.

#define _DMA_IF_CH8DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1114 of file ezr32wg_dma.h.

#define _DMA_IF_CH8DONE_MASK   0x100UL

Bit mask for DMA_CH8DONE

Definition at line 1113 of file ezr32wg_dma.h.

#define _DMA_IF_CH8DONE_SHIFT   8

Shift value for DMA_CH8DONE

Definition at line 1112 of file ezr32wg_dma.h.

#define _DMA_IF_CH9DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1119 of file ezr32wg_dma.h.

#define _DMA_IF_CH9DONE_MASK   0x200UL

Bit mask for DMA_CH9DONE

Definition at line 1118 of file ezr32wg_dma.h.

#define _DMA_IF_CH9DONE_SHIFT   9

Shift value for DMA_CH9DONE

Definition at line 1117 of file ezr32wg_dma.h.

#define _DMA_IF_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 1134 of file ezr32wg_dma.h.

#define _DMA_IF_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 1133 of file ezr32wg_dma.h.

#define _DMA_IF_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 1132 of file ezr32wg_dma.h.

#define _DMA_IF_MASK   0x80000FFFUL

Mask for DMA_IF

Definition at line 1070 of file ezr32wg_dma.h.

#define _DMA_IF_RESETVALUE   0x00000000UL

Default value for DMA_IF

Definition at line 1069 of file ezr32wg_dma.h.

#define _DMA_IFC_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1212 of file ezr32wg_dma.h.

#define _DMA_IFC_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 1211 of file ezr32wg_dma.h.

#define _DMA_IFC_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 1210 of file ezr32wg_dma.h.

#define _DMA_IFC_CH10DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1262 of file ezr32wg_dma.h.

#define _DMA_IFC_CH10DONE_MASK   0x400UL

Bit mask for DMA_CH10DONE

Definition at line 1261 of file ezr32wg_dma.h.

#define _DMA_IFC_CH10DONE_SHIFT   10

Shift value for DMA_CH10DONE

Definition at line 1260 of file ezr32wg_dma.h.

#define _DMA_IFC_CH11DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1267 of file ezr32wg_dma.h.

#define _DMA_IFC_CH11DONE_MASK   0x800UL

Bit mask for DMA_CH11DONE

Definition at line 1266 of file ezr32wg_dma.h.

#define _DMA_IFC_CH11DONE_SHIFT   11

Shift value for DMA_CH11DONE

Definition at line 1265 of file ezr32wg_dma.h.

#define _DMA_IFC_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1217 of file ezr32wg_dma.h.

#define _DMA_IFC_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 1216 of file ezr32wg_dma.h.

#define _DMA_IFC_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 1215 of file ezr32wg_dma.h.

#define _DMA_IFC_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1222 of file ezr32wg_dma.h.

#define _DMA_IFC_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 1221 of file ezr32wg_dma.h.

#define _DMA_IFC_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 1220 of file ezr32wg_dma.h.

#define _DMA_IFC_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1227 of file ezr32wg_dma.h.

#define _DMA_IFC_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 1226 of file ezr32wg_dma.h.

#define _DMA_IFC_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 1225 of file ezr32wg_dma.h.

#define _DMA_IFC_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1232 of file ezr32wg_dma.h.

#define _DMA_IFC_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 1231 of file ezr32wg_dma.h.

#define _DMA_IFC_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 1230 of file ezr32wg_dma.h.

#define _DMA_IFC_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1237 of file ezr32wg_dma.h.

#define _DMA_IFC_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 1236 of file ezr32wg_dma.h.

#define _DMA_IFC_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 1235 of file ezr32wg_dma.h.

#define _DMA_IFC_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1242 of file ezr32wg_dma.h.

#define _DMA_IFC_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 1241 of file ezr32wg_dma.h.

#define _DMA_IFC_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 1240 of file ezr32wg_dma.h.

#define _DMA_IFC_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1247 of file ezr32wg_dma.h.

#define _DMA_IFC_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 1246 of file ezr32wg_dma.h.

#define _DMA_IFC_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 1245 of file ezr32wg_dma.h.

#define _DMA_IFC_CH8DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1252 of file ezr32wg_dma.h.

#define _DMA_IFC_CH8DONE_MASK   0x100UL

Bit mask for DMA_CH8DONE

Definition at line 1251 of file ezr32wg_dma.h.

#define _DMA_IFC_CH8DONE_SHIFT   8

Shift value for DMA_CH8DONE

Definition at line 1250 of file ezr32wg_dma.h.

#define _DMA_IFC_CH9DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1257 of file ezr32wg_dma.h.

#define _DMA_IFC_CH9DONE_MASK   0x200UL

Bit mask for DMA_CH9DONE

Definition at line 1256 of file ezr32wg_dma.h.

#define _DMA_IFC_CH9DONE_SHIFT   9

Shift value for DMA_CH9DONE

Definition at line 1255 of file ezr32wg_dma.h.

#define _DMA_IFC_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 1272 of file ezr32wg_dma.h.

#define _DMA_IFC_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 1271 of file ezr32wg_dma.h.

#define _DMA_IFC_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 1270 of file ezr32wg_dma.h.

#define _DMA_IFC_MASK   0x80000FFFUL

Mask for DMA_IFC

Definition at line 1208 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define _DMA_IFC_RESETVALUE   0x00000000UL

Default value for DMA_IFC

Definition at line 1207 of file ezr32wg_dma.h.

#define _DMA_IFS_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1143 of file ezr32wg_dma.h.

#define _DMA_IFS_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 1142 of file ezr32wg_dma.h.

#define _DMA_IFS_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 1141 of file ezr32wg_dma.h.

#define _DMA_IFS_CH10DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1193 of file ezr32wg_dma.h.

#define _DMA_IFS_CH10DONE_MASK   0x400UL

Bit mask for DMA_CH10DONE

Definition at line 1192 of file ezr32wg_dma.h.

#define _DMA_IFS_CH10DONE_SHIFT   10

Shift value for DMA_CH10DONE

Definition at line 1191 of file ezr32wg_dma.h.

#define _DMA_IFS_CH11DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1198 of file ezr32wg_dma.h.

#define _DMA_IFS_CH11DONE_MASK   0x800UL

Bit mask for DMA_CH11DONE

Definition at line 1197 of file ezr32wg_dma.h.

#define _DMA_IFS_CH11DONE_SHIFT   11

Shift value for DMA_CH11DONE

Definition at line 1196 of file ezr32wg_dma.h.

#define _DMA_IFS_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1148 of file ezr32wg_dma.h.

#define _DMA_IFS_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 1147 of file ezr32wg_dma.h.

#define _DMA_IFS_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 1146 of file ezr32wg_dma.h.

#define _DMA_IFS_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1153 of file ezr32wg_dma.h.

#define _DMA_IFS_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 1152 of file ezr32wg_dma.h.

#define _DMA_IFS_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 1151 of file ezr32wg_dma.h.

#define _DMA_IFS_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1158 of file ezr32wg_dma.h.

#define _DMA_IFS_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 1157 of file ezr32wg_dma.h.

#define _DMA_IFS_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 1156 of file ezr32wg_dma.h.

#define _DMA_IFS_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1163 of file ezr32wg_dma.h.

#define _DMA_IFS_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 1162 of file ezr32wg_dma.h.

#define _DMA_IFS_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 1161 of file ezr32wg_dma.h.

#define _DMA_IFS_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1168 of file ezr32wg_dma.h.

#define _DMA_IFS_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 1167 of file ezr32wg_dma.h.

#define _DMA_IFS_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 1166 of file ezr32wg_dma.h.

#define _DMA_IFS_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1173 of file ezr32wg_dma.h.

#define _DMA_IFS_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 1172 of file ezr32wg_dma.h.

#define _DMA_IFS_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 1171 of file ezr32wg_dma.h.

#define _DMA_IFS_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1178 of file ezr32wg_dma.h.

#define _DMA_IFS_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 1177 of file ezr32wg_dma.h.

#define _DMA_IFS_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 1176 of file ezr32wg_dma.h.

#define _DMA_IFS_CH8DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1183 of file ezr32wg_dma.h.

#define _DMA_IFS_CH8DONE_MASK   0x100UL

Bit mask for DMA_CH8DONE

Definition at line 1182 of file ezr32wg_dma.h.

#define _DMA_IFS_CH8DONE_SHIFT   8

Shift value for DMA_CH8DONE

Definition at line 1181 of file ezr32wg_dma.h.

#define _DMA_IFS_CH9DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1188 of file ezr32wg_dma.h.

#define _DMA_IFS_CH9DONE_MASK   0x200UL

Bit mask for DMA_CH9DONE

Definition at line 1187 of file ezr32wg_dma.h.

#define _DMA_IFS_CH9DONE_SHIFT   9

Shift value for DMA_CH9DONE

Definition at line 1186 of file ezr32wg_dma.h.

#define _DMA_IFS_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 1203 of file ezr32wg_dma.h.

#define _DMA_IFS_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 1202 of file ezr32wg_dma.h.

#define _DMA_IFS_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 1201 of file ezr32wg_dma.h.

#define _DMA_IFS_MASK   0x80000FFFUL

Mask for DMA_IFS

Definition at line 1139 of file ezr32wg_dma.h.

#define _DMA_IFS_RESETVALUE   0x00000000UL

Default value for DMA_IFS

Definition at line 1138 of file ezr32wg_dma.h.

#define _DMA_LOOP0_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_LOOP0

Definition at line 1432 of file ezr32wg_dma.h.

#define _DMA_LOOP0_EN_MASK   0x10000UL

Bit mask for DMA_EN

Definition at line 1431 of file ezr32wg_dma.h.

#define _DMA_LOOP0_EN_SHIFT   16

Shift value for DMA_EN

Definition at line 1430 of file ezr32wg_dma.h.

Referenced by DMA_CfgLoop().

#define _DMA_LOOP0_MASK   0x000103FFUL

Mask for DMA_LOOP0

Definition at line 1424 of file ezr32wg_dma.h.

#define _DMA_LOOP0_RESETVALUE   0x00000000UL

Default value for DMA_LOOP0

Definition at line 1423 of file ezr32wg_dma.h.

Referenced by DMA_ResetLoop().

#define _DMA_LOOP0_WIDTH_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_LOOP0

Definition at line 1427 of file ezr32wg_dma.h.

#define _DMA_LOOP0_WIDTH_MASK   0x3FFUL

Bit mask for DMA_WIDTH

Definition at line 1426 of file ezr32wg_dma.h.

#define _DMA_LOOP0_WIDTH_SHIFT   0

Shift value for DMA_WIDTH

Definition at line 1425 of file ezr32wg_dma.h.

Referenced by DMA_CfgLoop().

#define _DMA_LOOP1_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_LOOP1

Definition at line 1445 of file ezr32wg_dma.h.

#define _DMA_LOOP1_EN_MASK   0x10000UL

Bit mask for DMA_EN

Definition at line 1444 of file ezr32wg_dma.h.

#define _DMA_LOOP1_EN_SHIFT   16

Shift value for DMA_EN

Definition at line 1443 of file ezr32wg_dma.h.

Referenced by DMA_CfgLoop().

#define _DMA_LOOP1_MASK   0x000103FFUL

Mask for DMA_LOOP1

Definition at line 1437 of file ezr32wg_dma.h.

#define _DMA_LOOP1_RESETVALUE   0x00000000UL

Default value for DMA_LOOP1

Definition at line 1436 of file ezr32wg_dma.h.

Referenced by DMA_ResetLoop().

#define _DMA_LOOP1_WIDTH_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_LOOP1

Definition at line 1440 of file ezr32wg_dma.h.

#define _DMA_LOOP1_WIDTH_MASK   0x3FFUL

Bit mask for DMA_WIDTH

Definition at line 1439 of file ezr32wg_dma.h.

#define _DMA_LOOP1_WIDTH_SHIFT   0

Shift value for DMA_WIDTH

Definition at line 1438 of file ezr32wg_dma.h.

Referenced by DMA_CfgLoop().

#define _DMA_RDS_MASK   0x00000FFFUL

Mask for DMA_RDS

Definition at line 1360 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH0_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1364 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH0_MASK   0x1UL

Bit mask for DMA_RDSCH0

Definition at line 1363 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH0_SHIFT   0

Shift value for DMA_RDSCH0

Definition at line 1362 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH10_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1414 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH10_MASK   0x400UL

Bit mask for DMA_RDSCH10

Definition at line 1413 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH10_SHIFT   10

Shift value for DMA_RDSCH10

Definition at line 1412 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH11_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1419 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH11_MASK   0x800UL

Bit mask for DMA_RDSCH11

Definition at line 1418 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH11_SHIFT   11

Shift value for DMA_RDSCH11

Definition at line 1417 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH1_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1369 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH1_MASK   0x2UL

Bit mask for DMA_RDSCH1

Definition at line 1368 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH1_SHIFT   1

Shift value for DMA_RDSCH1

Definition at line 1367 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH2_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1374 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH2_MASK   0x4UL

Bit mask for DMA_RDSCH2

Definition at line 1373 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH2_SHIFT   2

Shift value for DMA_RDSCH2

Definition at line 1372 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH3_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1379 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH3_MASK   0x8UL

Bit mask for DMA_RDSCH3

Definition at line 1378 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH3_SHIFT   3

Shift value for DMA_RDSCH3

Definition at line 1377 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH4_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1384 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH4_MASK   0x10UL

Bit mask for DMA_RDSCH4

Definition at line 1383 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH4_SHIFT   4

Shift value for DMA_RDSCH4

Definition at line 1382 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH5_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1389 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH5_MASK   0x20UL

Bit mask for DMA_RDSCH5

Definition at line 1388 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH5_SHIFT   5

Shift value for DMA_RDSCH5

Definition at line 1387 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH6_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1394 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH6_MASK   0x40UL

Bit mask for DMA_RDSCH6

Definition at line 1393 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH6_SHIFT   6

Shift value for DMA_RDSCH6

Definition at line 1392 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH7_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1399 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH7_MASK   0x80UL

Bit mask for DMA_RDSCH7

Definition at line 1398 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH7_SHIFT   7

Shift value for DMA_RDSCH7

Definition at line 1397 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH8_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1404 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH8_MASK   0x100UL

Bit mask for DMA_RDSCH8

Definition at line 1403 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH8_SHIFT   8

Shift value for DMA_RDSCH8

Definition at line 1402 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH9_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RDS

Definition at line 1409 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH9_MASK   0x200UL

Bit mask for DMA_RDSCH9

Definition at line 1408 of file ezr32wg_dma.h.

#define _DMA_RDS_RDSCH9_SHIFT   9

Shift value for DMA_RDSCH9

Definition at line 1407 of file ezr32wg_dma.h.

#define _DMA_RDS_RESETVALUE   0x00000000UL

Default value for DMA_RDS

Definition at line 1359 of file ezr32wg_dma.h.

#define _DMA_RECT0_DSTSTRIDE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RECT0

Definition at line 1461 of file ezr32wg_dma.h.

#define _DMA_RECT0_DSTSTRIDE_MASK   0xFFE00000UL

Bit mask for DMA_DSTSTRIDE

Definition at line 1460 of file ezr32wg_dma.h.

#define _DMA_RECT0_DSTSTRIDE_SHIFT   21

Shift value for DMA_DSTSTRIDE

Definition at line 1459 of file ezr32wg_dma.h.

Referenced by DMA_CfgRect().

#define _DMA_RECT0_HEIGHT_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RECT0

Definition at line 1453 of file ezr32wg_dma.h.

#define _DMA_RECT0_HEIGHT_MASK   0x3FFUL

Bit mask for DMA_HEIGHT

Definition at line 1452 of file ezr32wg_dma.h.

#define _DMA_RECT0_HEIGHT_SHIFT   0

Shift value for DMA_HEIGHT

Definition at line 1451 of file ezr32wg_dma.h.

Referenced by DMA_CfgRect().

#define _DMA_RECT0_MASK   0xFFFFFFFFUL

Mask for DMA_RECT0

Definition at line 1450 of file ezr32wg_dma.h.

#define _DMA_RECT0_RESETVALUE   0x00000000UL

Default value for DMA_RECT0

Definition at line 1449 of file ezr32wg_dma.h.

Referenced by DMA_ResetRect().

#define _DMA_RECT0_SRCSTRIDE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_RECT0

Definition at line 1457 of file ezr32wg_dma.h.

#define _DMA_RECT0_SRCSTRIDE_MASK   0x1FFC00UL

Bit mask for DMA_SRCSTRIDE

Definition at line 1456 of file ezr32wg_dma.h.

#define _DMA_RECT0_SRCSTRIDE_SHIFT   10

Shift value for DMA_SRCSTRIDE

Definition at line 1455 of file ezr32wg_dma.h.

Referenced by DMA_CfgRect().

#define _DMA_STATUS_CHNUM_DEFAULT   0x0000000BUL

Mode DEFAULT for DMA_STATUS

Definition at line 126 of file ezr32wg_dma.h.

#define _DMA_STATUS_CHNUM_MASK   0x1F0000UL

Bit mask for DMA_CHNUM

Definition at line 125 of file ezr32wg_dma.h.

#define _DMA_STATUS_CHNUM_SHIFT   16

Shift value for DMA_CHNUM

Definition at line 124 of file ezr32wg_dma.h.

#define _DMA_STATUS_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 96 of file ezr32wg_dma.h.

#define _DMA_STATUS_EN_MASK   0x1UL

Bit mask for DMA_EN

Definition at line 95 of file ezr32wg_dma.h.

#define _DMA_STATUS_EN_SHIFT   0

Shift value for DMA_EN

Definition at line 94 of file ezr32wg_dma.h.

#define _DMA_STATUS_MASK   0x001F00F1UL

Mask for DMA_STATUS

Definition at line 92 of file ezr32wg_dma.h.

#define _DMA_STATUS_RESETVALUE   0x100B0000UL

Default value for DMA_STATUS

Definition at line 91 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 100 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_DONE   0x00000009UL

Mode DONE for DMA_STATUS

Definition at line 110 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_IDLE   0x00000000UL

Mode IDLE for DMA_STATUS

Definition at line 101 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_MASK   0xF0UL

Bit mask for DMA_STATE

Definition at line 99 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_PERSCATTRANS   0x0000000AUL

Mode PERSCATTRANS for DMA_STATUS

Definition at line 111 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_RDCHCTRLDATA   0x00000001UL

Mode RDCHCTRLDATA for DMA_STATUS

Definition at line 102 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_RDDSTENDPTR   0x00000003UL

Mode RDDSTENDPTR for DMA_STATUS

Definition at line 104 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_RDSRCDATA   0x00000004UL

Mode RDSRCDATA for DMA_STATUS

Definition at line 105 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_RDSRCENDPTR   0x00000002UL

Mode RDSRCENDPTR for DMA_STATUS

Definition at line 103 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_SHIFT   4

Shift value for DMA_STATE

Definition at line 98 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_STALLED   0x00000008UL

Mode STALLED for DMA_STATUS

Definition at line 109 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_WAITREQCLR   0x00000006UL

Mode WAITREQCLR for DMA_STATUS

Definition at line 107 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_WRCHCTRLDATA   0x00000007UL

Mode WRCHCTRLDATA for DMA_STATUS

Definition at line 108 of file ezr32wg_dma.h.

#define _DMA_STATUS_STATE_WRDSTDATA   0x00000005UL

Mode WRDSTDATA for DMA_STATUS

Definition at line 106 of file ezr32wg_dma.h.

#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 157 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SCAN   (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

Shifted mode ADC0SCAN for DMA_CH_CTRL

Definition at line 1542 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

Shifted mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 1524 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESDATARD   (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

Shifted mode AESDATARD for DMA_CH_CTRL

Definition at line 1569 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESDATAWR   (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

Shifted mode AESDATAWR for DMA_CH_CTRL

Definition at line 1540 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESKEYWR   (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

Shifted mode AESKEYWR for DMA_CH_CTRL

Definition at line 1576 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR   (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

Shifted mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 1557 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_DAC0CH0   (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)

Shifted mode DAC0CH0 for DMA_CH_CTRL

Definition at line 1525 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_DAC0CH1   (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)

Shifted mode DAC0CH1 for DMA_CH_CTRL

Definition at line 1543 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

Shifted mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 1531 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C0TXBL   (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

Shifted mode I2C0TXBL for DMA_CH_CTRL

Definition at line 1549 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0)

Shifted mode I2C1RXDATAV for DMA_CH_CTRL

Definition at line 1532 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C1TXBL   (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0)

Shifted mode I2C1TXBL for DMA_CH_CTRL

Definition at line 1550 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV   (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0)

Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL

Definition at line 1541 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

Shifted mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 1529 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

Shifted mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 1547 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 1561 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)

Shifted mode LEUART1RXDATAV for DMA_CH_CTRL

Definition at line 1530 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)

Shifted mode LEUART1TXBL for DMA_CH_CTRL

Definition at line 1548 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)

Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL

Definition at line 1562 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_MSCWDATA   (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

Shifted mode MSCWDATA for DMA_CH_CTRL

Definition at line 1539 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC0   (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

Shifted mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 1551 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC1   (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

Shifted mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 1563 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC2   (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

Shifted mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 1572 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

Shifted mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 1533 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC0   (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

Shifted mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 1552 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC1   (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

Shifted mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 1564 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC2   (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

Shifted mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 1573 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

Shifted mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 1534 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC0   (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)

Shifted mode TIMER2CC0 for DMA_CH_CTRL

Definition at line 1553 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC1   (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)

Shifted mode TIMER2CC1 for DMA_CH_CTRL

Definition at line 1565 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC2   (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)

Shifted mode TIMER2CC2 for DMA_CH_CTRL

Definition at line 1574 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)

Shifted mode TIMER2UFOF for DMA_CH_CTRL

Definition at line 1535 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER3CC0   (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0)

Shifted mode TIMER3CC0 for DMA_CH_CTRL

Definition at line 1554 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER3CC1   (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0)

Shifted mode TIMER3CC1 for DMA_CH_CTRL

Definition at line 1566 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER3CC2   (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0)

Shifted mode TIMER3CC2 for DMA_CH_CTRL

Definition at line 1575 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0)

Shifted mode TIMER3UFOF for DMA_CH_CTRL

Definition at line 1536 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)

Shifted mode UART0RXDATAV for DMA_CH_CTRL

Definition at line 1537 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_UART0TXBL   (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)

Shifted mode UART0TXBL for DMA_CH_CTRL

Definition at line 1555 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)

Shifted mode UART0TXEMPTY for DMA_CH_CTRL

Definition at line 1567 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_UART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0)

Shifted mode UART1RXDATAV for DMA_CH_CTRL

Definition at line 1538 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_UART1TXBL   (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0)

Shifted mode UART1TXBL for DMA_CH_CTRL

Definition at line 1556 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0)

Shifted mode UART1TXEMPTY for DMA_CH_CTRL

Definition at line 1568 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)

Shifted mode USART1RXDATAV for DMA_CH_CTRL

Definition at line 1527 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)

Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 1570 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXBL   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)

Shifted mode USART1TXBL for DMA_CH_CTRL

Definition at line 1545 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)

Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL

Definition at line 1577 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)

Shifted mode USART1TXEMPTY for DMA_CH_CTRL

Definition at line 1559 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)

Shifted mode USART2RXDATAV for DMA_CH_CTRL

Definition at line 1528 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT   (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0)

Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 1571 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART2TXBL   (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)

Shifted mode USART2TXBL for DMA_CH_CTRL

Definition at line 1546 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT   (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0)

Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL

Definition at line 1578 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)

Shifted mode USART2TXEMPTY for DMA_CH_CTRL

Definition at line 1560 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV   (_DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV << 0)

Shifted mode USARTRF0RXDATAV for DMA_CH_CTRL

Definition at line 1526 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF0TXBL   (_DMA_CH_CTRL_SIGSEL_USARTRF0TXBL << 0)

Shifted mode USARTRF0TXBL for DMA_CH_CTRL

Definition at line 1544 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY << 0)

Shifted mode USARTRF0TXEMPTY for DMA_CH_CTRL

Definition at line 1558 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_ADC0   (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

Shifted mode ADC0 for DMA_CH_CTRL

Definition at line 1601 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_AES   (_DMA_CH_CTRL_SOURCESEL_AES << 16)

Shifted mode AES for DMA_CH_CTRL

Definition at line 1617 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_DAC0   (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)

Shifted mode DAC0 for DMA_CH_CTRL

Definition at line 1602 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_I2C0   (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

Shifted mode I2C0 for DMA_CH_CTRL

Definition at line 1608 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_I2C1   (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16)

Shifted mode I2C1 for DMA_CH_CTRL

Definition at line 1609 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_LESENSE   (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16)

Shifted mode LESENSE for DMA_CH_CTRL

Definition at line 1618 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_LEUART0   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

Shifted mode LEUART0 for DMA_CH_CTRL

Definition at line 1606 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_LEUART1   (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)

Shifted mode LEUART1 for DMA_CH_CTRL

Definition at line 1607 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_MSC   (_DMA_CH_CTRL_SOURCESEL_MSC << 16)

Shifted mode MSC for DMA_CH_CTRL

Definition at line 1616 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_NONE   (_DMA_CH_CTRL_SOURCESEL_NONE << 16)

Shifted mode NONE for DMA_CH_CTRL

Definition at line 1600 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER0   (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

Shifted mode TIMER0 for DMA_CH_CTRL

Definition at line 1610 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER1   (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

Shifted mode TIMER1 for DMA_CH_CTRL

Definition at line 1611 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER2   (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)

Shifted mode TIMER2 for DMA_CH_CTRL

Definition at line 1612 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER3   (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16)

Shifted mode TIMER3 for DMA_CH_CTRL

Definition at line 1613 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_UART0   (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)

Shifted mode UART0 for DMA_CH_CTRL

Definition at line 1614 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_UART1   (_DMA_CH_CTRL_SOURCESEL_UART1 << 16)

Shifted mode UART1 for DMA_CH_CTRL

Definition at line 1615 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_USART1   (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)

Shifted mode USART1 for DMA_CH_CTRL

Definition at line 1604 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_USART2   (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)

Shifted mode USART2 for DMA_CH_CTRL

Definition at line 1605 of file ezr32wg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_USARTRF0   (_DMA_CH_CTRL_SOURCESEL_USARTRF0 << 16)

Shifted mode USARTRF0 for DMA_CH_CTRL

Definition at line 1603 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH0ALTC   (0x1UL << 0)

Channel 0 Alternate Clear

Definition at line 742 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH0ALTC_DEFAULT   (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 746 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH10ALTC   (0x1UL << 10)

Channel 10 Alternate Clear

Definition at line 792 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH10ALTC_DEFAULT   (_DMA_CHALTC_CH10ALTC_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 796 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH11ALTC   (0x1UL << 11)

Channel 11 Alternate Clear

Definition at line 797 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH11ALTC_DEFAULT   (_DMA_CHALTC_CH11ALTC_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 801 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH1ALTC   (0x1UL << 1)

Channel 1 Alternate Clear

Definition at line 747 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH1ALTC_DEFAULT   (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 751 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH2ALTC   (0x1UL << 2)

Channel 2 Alternate Clear

Definition at line 752 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH2ALTC_DEFAULT   (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 756 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH3ALTC   (0x1UL << 3)

Channel 3 Alternate Clear

Definition at line 757 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH3ALTC_DEFAULT   (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 761 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH4ALTC   (0x1UL << 4)

Channel 4 Alternate Clear

Definition at line 762 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH4ALTC_DEFAULT   (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 766 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH5ALTC   (0x1UL << 5)

Channel 5 Alternate Clear

Definition at line 767 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH5ALTC_DEFAULT   (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 771 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH6ALTC   (0x1UL << 6)

Channel 6 Alternate Clear

Definition at line 772 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH6ALTC_DEFAULT   (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 776 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH7ALTC   (0x1UL << 7)

Channel 7 Alternate Clear

Definition at line 777 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH7ALTC_DEFAULT   (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 781 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH8ALTC   (0x1UL << 8)

Channel 8 Alternate Clear

Definition at line 782 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH8ALTC_DEFAULT   (_DMA_CHALTC_CH8ALTC_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 786 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH9ALTC   (0x1UL << 9)

Channel 9 Alternate Clear

Definition at line 787 of file ezr32wg_dma.h.

#define DMA_CHALTC_CH9ALTC_DEFAULT   (_DMA_CHALTC_CH9ALTC_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 791 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH0ALTS   (0x1UL << 0)

Channel 0 Alternate Structure Set

Definition at line 678 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH0ALTS_DEFAULT   (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 682 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH10ALTS   (0x1UL << 10)

Channel 10 Alternate Structure Set

Definition at line 728 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH10ALTS_DEFAULT   (_DMA_CHALTS_CH10ALTS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 732 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH11ALTS   (0x1UL << 11)

Channel 11 Alternate Structure Set

Definition at line 733 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH11ALTS_DEFAULT   (_DMA_CHALTS_CH11ALTS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 737 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH1ALTS   (0x1UL << 1)

Channel 1 Alternate Structure Set

Definition at line 683 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH1ALTS_DEFAULT   (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 687 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH2ALTS   (0x1UL << 2)

Channel 2 Alternate Structure Set

Definition at line 688 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH2ALTS_DEFAULT   (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 692 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH3ALTS   (0x1UL << 3)

Channel 3 Alternate Structure Set

Definition at line 693 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH3ALTS_DEFAULT   (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 697 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH4ALTS   (0x1UL << 4)

Channel 4 Alternate Structure Set

Definition at line 698 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH4ALTS_DEFAULT   (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 702 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH5ALTS   (0x1UL << 5)

Channel 5 Alternate Structure Set

Definition at line 703 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH5ALTS_DEFAULT   (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 707 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH6ALTS   (0x1UL << 6)

Channel 6 Alternate Structure Set

Definition at line 708 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH6ALTS_DEFAULT   (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 712 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH7ALTS   (0x1UL << 7)

Channel 7 Alternate Structure Set

Definition at line 713 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH7ALTS_DEFAULT   (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 717 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH8ALTS   (0x1UL << 8)

Channel 8 Alternate Structure Set

Definition at line 718 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH8ALTS_DEFAULT   (_DMA_CHALTS_CH8ALTS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 722 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH9ALTS   (0x1UL << 9)

Channel 9 Alternate Structure Set

Definition at line 723 of file ezr32wg_dma.h.

#define DMA_CHALTS_CH9ALTS_DEFAULT   (_DMA_CHALTS_CH9ALTS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 727 of file ezr32wg_dma.h.

#define DMA_CHENC_CH0ENC   (0x1UL << 0)

Channel 0 Enable Clear

Definition at line 614 of file ezr32wg_dma.h.

#define DMA_CHENC_CH0ENC_DEFAULT   (_DMA_CHENC_CH0ENC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 618 of file ezr32wg_dma.h.

#define DMA_CHENC_CH10ENC   (0x1UL << 10)

Channel 10 Enable Clear

Definition at line 664 of file ezr32wg_dma.h.

#define DMA_CHENC_CH10ENC_DEFAULT   (_DMA_CHENC_CH10ENC_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 668 of file ezr32wg_dma.h.

#define DMA_CHENC_CH11ENC   (0x1UL << 11)

Channel 11 Enable Clear

Definition at line 669 of file ezr32wg_dma.h.

#define DMA_CHENC_CH11ENC_DEFAULT   (_DMA_CHENC_CH11ENC_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 673 of file ezr32wg_dma.h.

#define DMA_CHENC_CH1ENC   (0x1UL << 1)

Channel 1 Enable Clear

Definition at line 619 of file ezr32wg_dma.h.

#define DMA_CHENC_CH1ENC_DEFAULT   (_DMA_CHENC_CH1ENC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 623 of file ezr32wg_dma.h.

#define DMA_CHENC_CH2ENC   (0x1UL << 2)

Channel 2 Enable Clear

Definition at line 624 of file ezr32wg_dma.h.

#define DMA_CHENC_CH2ENC_DEFAULT   (_DMA_CHENC_CH2ENC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 628 of file ezr32wg_dma.h.

#define DMA_CHENC_CH3ENC   (0x1UL << 3)

Channel 3 Enable Clear

Definition at line 629 of file ezr32wg_dma.h.

#define DMA_CHENC_CH3ENC_DEFAULT   (_DMA_CHENC_CH3ENC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 633 of file ezr32wg_dma.h.

#define DMA_CHENC_CH4ENC   (0x1UL << 4)

Channel 4 Enable Clear

Definition at line 634 of file ezr32wg_dma.h.

#define DMA_CHENC_CH4ENC_DEFAULT   (_DMA_CHENC_CH4ENC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 638 of file ezr32wg_dma.h.

#define DMA_CHENC_CH5ENC   (0x1UL << 5)

Channel 5 Enable Clear

Definition at line 639 of file ezr32wg_dma.h.

#define DMA_CHENC_CH5ENC_DEFAULT   (_DMA_CHENC_CH5ENC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 643 of file ezr32wg_dma.h.

#define DMA_CHENC_CH6ENC   (0x1UL << 6)

Channel 6 Enable Clear

Definition at line 644 of file ezr32wg_dma.h.

#define DMA_CHENC_CH6ENC_DEFAULT   (_DMA_CHENC_CH6ENC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 648 of file ezr32wg_dma.h.

#define DMA_CHENC_CH7ENC   (0x1UL << 7)

Channel 7 Enable Clear

Definition at line 649 of file ezr32wg_dma.h.

#define DMA_CHENC_CH7ENC_DEFAULT   (_DMA_CHENC_CH7ENC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 653 of file ezr32wg_dma.h.

#define DMA_CHENC_CH8ENC   (0x1UL << 8)

Channel 8 Enable Clear

Definition at line 654 of file ezr32wg_dma.h.

#define DMA_CHENC_CH8ENC_DEFAULT   (_DMA_CHENC_CH8ENC_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 658 of file ezr32wg_dma.h.

#define DMA_CHENC_CH9ENC   (0x1UL << 9)

Channel 9 Enable Clear

Definition at line 659 of file ezr32wg_dma.h.

#define DMA_CHENC_CH9ENC_DEFAULT   (_DMA_CHENC_CH9ENC_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 663 of file ezr32wg_dma.h.

#define DMA_CHENS_CH0ENS   (0x1UL << 0)

Channel 0 Enable Set

Definition at line 550 of file ezr32wg_dma.h.

#define DMA_CHENS_CH0ENS_DEFAULT   (_DMA_CHENS_CH0ENS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 554 of file ezr32wg_dma.h.

#define DMA_CHENS_CH10ENS   (0x1UL << 10)

Channel 10 Enable Set

Definition at line 600 of file ezr32wg_dma.h.

#define DMA_CHENS_CH10ENS_DEFAULT   (_DMA_CHENS_CH10ENS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 604 of file ezr32wg_dma.h.

#define DMA_CHENS_CH11ENS   (0x1UL << 11)

Channel 11 Enable Set

Definition at line 605 of file ezr32wg_dma.h.

#define DMA_CHENS_CH11ENS_DEFAULT   (_DMA_CHENS_CH11ENS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 609 of file ezr32wg_dma.h.

#define DMA_CHENS_CH1ENS   (0x1UL << 1)

Channel 1 Enable Set

Definition at line 555 of file ezr32wg_dma.h.

#define DMA_CHENS_CH1ENS_DEFAULT   (_DMA_CHENS_CH1ENS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 559 of file ezr32wg_dma.h.

#define DMA_CHENS_CH2ENS   (0x1UL << 2)

Channel 2 Enable Set

Definition at line 560 of file ezr32wg_dma.h.

#define DMA_CHENS_CH2ENS_DEFAULT   (_DMA_CHENS_CH2ENS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 564 of file ezr32wg_dma.h.

#define DMA_CHENS_CH3ENS   (0x1UL << 3)

Channel 3 Enable Set

Definition at line 565 of file ezr32wg_dma.h.

#define DMA_CHENS_CH3ENS_DEFAULT   (_DMA_CHENS_CH3ENS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 569 of file ezr32wg_dma.h.

#define DMA_CHENS_CH4ENS   (0x1UL << 4)

Channel 4 Enable Set

Definition at line 570 of file ezr32wg_dma.h.

#define DMA_CHENS_CH4ENS_DEFAULT   (_DMA_CHENS_CH4ENS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 574 of file ezr32wg_dma.h.

#define DMA_CHENS_CH5ENS   (0x1UL << 5)

Channel 5 Enable Set

Definition at line 575 of file ezr32wg_dma.h.

#define DMA_CHENS_CH5ENS_DEFAULT   (_DMA_CHENS_CH5ENS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 579 of file ezr32wg_dma.h.

#define DMA_CHENS_CH6ENS   (0x1UL << 6)

Channel 6 Enable Set

Definition at line 580 of file ezr32wg_dma.h.

#define DMA_CHENS_CH6ENS_DEFAULT   (_DMA_CHENS_CH6ENS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 584 of file ezr32wg_dma.h.

#define DMA_CHENS_CH7ENS   (0x1UL << 7)

Channel 7 Enable Set

Definition at line 585 of file ezr32wg_dma.h.

#define DMA_CHENS_CH7ENS_DEFAULT   (_DMA_CHENS_CH7ENS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 589 of file ezr32wg_dma.h.

#define DMA_CHENS_CH8ENS   (0x1UL << 8)

Channel 8 Enable Set

Definition at line 590 of file ezr32wg_dma.h.

#define DMA_CHENS_CH8ENS_DEFAULT   (_DMA_CHENS_CH8ENS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 594 of file ezr32wg_dma.h.

#define DMA_CHENS_CH9ENS   (0x1UL << 9)

Channel 9 Enable Set

Definition at line 595 of file ezr32wg_dma.h.

#define DMA_CHENS_CH9ENS_DEFAULT   (_DMA_CHENS_CH9ENS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 599 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH0PRIC   (0x1UL << 0)

Channel 0 High Priority Clear

Definition at line 870 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH0PRIC_DEFAULT   (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 874 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH10PRIC   (0x1UL << 10)

Channel 10 High Priority Clear

Definition at line 920 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH10PRIC_DEFAULT   (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 924 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH11PRIC   (0x1UL << 11)

Channel 11 High Priority Clear

Definition at line 925 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH11PRIC_DEFAULT   (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 929 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH1PRIC   (0x1UL << 1)

Channel 1 High Priority Clear

Definition at line 875 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH1PRIC_DEFAULT   (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 879 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH2PRIC   (0x1UL << 2)

Channel 2 High Priority Clear

Definition at line 880 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH2PRIC_DEFAULT   (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 884 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH3PRIC   (0x1UL << 3)

Channel 3 High Priority Clear

Definition at line 885 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH3PRIC_DEFAULT   (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 889 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH4PRIC   (0x1UL << 4)

Channel 4 High Priority Clear

Definition at line 890 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH4PRIC_DEFAULT   (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 894 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH5PRIC   (0x1UL << 5)

Channel 5 High Priority Clear

Definition at line 895 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH5PRIC_DEFAULT   (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 899 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH6PRIC   (0x1UL << 6)

Channel 6 High Priority Clear

Definition at line 900 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH6PRIC_DEFAULT   (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 904 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH7PRIC   (0x1UL << 7)

Channel 7 High Priority Clear

Definition at line 905 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH7PRIC_DEFAULT   (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 909 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH8PRIC   (0x1UL << 8)

Channel 8 High Priority Clear

Definition at line 910 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH8PRIC_DEFAULT   (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 914 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH9PRIC   (0x1UL << 9)

Channel 9 High Priority Clear

Definition at line 915 of file ezr32wg_dma.h.

#define DMA_CHPRIC_CH9PRIC_DEFAULT   (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 919 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH0PRIS   (0x1UL << 0)

Channel 0 High Priority Set

Definition at line 806 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH0PRIS_DEFAULT   (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 810 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH10PRIS   (0x1UL << 10)

Channel 10 High Priority Set

Definition at line 856 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH10PRIS_DEFAULT   (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 860 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH11PRIS   (0x1UL << 11)

Channel 11 High Priority Set

Definition at line 861 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH11PRIS_DEFAULT   (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 865 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH1PRIS   (0x1UL << 1)

Channel 1 High Priority Set

Definition at line 811 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH1PRIS_DEFAULT   (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 815 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH2PRIS   (0x1UL << 2)

Channel 2 High Priority Set

Definition at line 816 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH2PRIS_DEFAULT   (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 820 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH3PRIS   (0x1UL << 3)

Channel 3 High Priority Set

Definition at line 821 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH3PRIS_DEFAULT   (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 825 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH4PRIS   (0x1UL << 4)

Channel 4 High Priority Set

Definition at line 826 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH4PRIS_DEFAULT   (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 830 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH5PRIS   (0x1UL << 5)

Channel 5 High Priority Set

Definition at line 831 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH5PRIS_DEFAULT   (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 835 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH6PRIS   (0x1UL << 6)

Channel 6 High Priority Set

Definition at line 836 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH6PRIS_DEFAULT   (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 840 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH7PRIS   (0x1UL << 7)

Channel 7 High Priority Set

Definition at line 841 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH7PRIS_DEFAULT   (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 845 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH8PRIS   (0x1UL << 8)

Channel 8 High Priority Set

Definition at line 846 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH8PRIS_DEFAULT   (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 850 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH9PRIS   (0x1UL << 9)

Channel 9 High Priority Set

Definition at line 851 of file ezr32wg_dma.h.

#define DMA_CHPRIS_CH9PRIS_DEFAULT   (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 855 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH0REQMASKC   (0x1UL << 0)

Channel 0 Request Mask Clear

Definition at line 486 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 490 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH10REQMASKC   (0x1UL << 10)

Channel 10 Request Mask Clear

Definition at line 536 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 540 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH11REQMASKC   (0x1UL << 11)

Channel 11 Request Mask Clear

Definition at line 541 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 545 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH1REQMASKC   (0x1UL << 1)

Channel 1 Request Mask Clear

Definition at line 491 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 495 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH2REQMASKC   (0x1UL << 2)

Channel 2 Request Mask Clear

Definition at line 496 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 500 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH3REQMASKC   (0x1UL << 3)

Channel 3 Request Mask Clear

Definition at line 501 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 505 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH4REQMASKC   (0x1UL << 4)

Channel 4 Request Mask Clear

Definition at line 506 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 510 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH5REQMASKC   (0x1UL << 5)

Channel 5 Request Mask Clear

Definition at line 511 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 515 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH6REQMASKC   (0x1UL << 6)

Channel 6 Request Mask Clear

Definition at line 516 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 520 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH7REQMASKC   (0x1UL << 7)

Channel 7 Request Mask Clear

Definition at line 521 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 525 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH8REQMASKC   (0x1UL << 8)

Channel 8 Request Mask Clear

Definition at line 526 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 530 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH9REQMASKC   (0x1UL << 9)

Channel 9 Request Mask Clear

Definition at line 531 of file ezr32wg_dma.h.

#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 535 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH0REQMASKS   (0x1UL << 0)

Channel 0 Request Mask Set

Definition at line 422 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 426 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH10REQMASKS   (0x1UL << 10)

Channel 10 Request Mask Set

Definition at line 472 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 476 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH11REQMASKS   (0x1UL << 11)

Channel 11 Request Mask Set

Definition at line 477 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 481 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH1REQMASKS   (0x1UL << 1)

Channel 1 Request Mask Set

Definition at line 427 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 431 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH2REQMASKS   (0x1UL << 2)

Channel 2 Request Mask Set

Definition at line 432 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 436 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH3REQMASKS   (0x1UL << 3)

Channel 3 Request Mask Set

Definition at line 437 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 441 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH4REQMASKS   (0x1UL << 4)

Channel 4 Request Mask Set

Definition at line 442 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 446 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH5REQMASKS   (0x1UL << 5)

Channel 5 Request Mask Set

Definition at line 447 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 451 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH6REQMASKS   (0x1UL << 6)

Channel 6 Request Mask Set

Definition at line 452 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 456 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH7REQMASKS   (0x1UL << 7)

Channel 7 Request Mask Set

Definition at line 457 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 461 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH8REQMASKS   (0x1UL << 8)

Channel 8 Request Mask Set

Definition at line 462 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 466 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH9REQMASKS   (0x1UL << 9)

Channel 9 Request Mask Set

Definition at line 467 of file ezr32wg_dma.h.

#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 471 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS   (0x1UL << 0)

Channel 0 Request Status

Definition at line 943 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 947 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH10REQSTATUS   (0x1UL << 10)

Channel 10 Request Status

Definition at line 993 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 997 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH11REQSTATUS   (0x1UL << 11)

Channel 11 Request Status

Definition at line 998 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 1002 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS   (0x1UL << 1)

Channel 1 Request Status

Definition at line 948 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 952 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS   (0x1UL << 2)

Channel 2 Request Status

Definition at line 953 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 957 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS   (0x1UL << 3)

Channel 3 Request Status

Definition at line 958 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 962 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH4REQSTATUS   (0x1UL << 4)

Channel 4 Request Status

Definition at line 963 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 967 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH5REQSTATUS   (0x1UL << 5)

Channel 5 Request Status

Definition at line 968 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 972 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH6REQSTATUS   (0x1UL << 6)

Channel 6 Request Status

Definition at line 973 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 977 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH7REQSTATUS   (0x1UL << 7)

Channel 7 Request Status

Definition at line 978 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 982 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH8REQSTATUS   (0x1UL << 8)

Channel 8 Request Status

Definition at line 983 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 987 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH9REQSTATUS   (0x1UL << 9)

Channel 9 Request Status

Definition at line 988 of file ezr32wg_dma.h.

#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 992 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS   (0x1UL << 0)

Channel 0 Single Request Status

Definition at line 1007 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1011 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH10SREQSTATUS   (0x1UL << 10)

Channel 10 Single Request Status

Definition at line 1057 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1061 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH11SREQSTATUS   (0x1UL << 11)

Channel 11 Single Request Status

Definition at line 1062 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1066 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS   (0x1UL << 1)

Channel 1 Single Request Status

Definition at line 1012 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1016 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS   (0x1UL << 2)

Channel 2 Single Request Status

Definition at line 1017 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1021 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS   (0x1UL << 3)

Channel 3 Single Request Status

Definition at line 1022 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1026 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH4SREQSTATUS   (0x1UL << 4)

Channel 4 Single Request Status

Definition at line 1027 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1031 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH5SREQSTATUS   (0x1UL << 5)

Channel 5 Single Request Status

Definition at line 1032 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1036 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH6SREQSTATUS   (0x1UL << 6)

Channel 6 Single Request Status

Definition at line 1037 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1041 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH7SREQSTATUS   (0x1UL << 7)

Channel 7 Single Request Status

Definition at line 1042 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1046 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH8SREQSTATUS   (0x1UL << 8)

Channel 8 Single Request Status

Definition at line 1047 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1051 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH9SREQSTATUS   (0x1UL << 9)

Channel 9 Single Request Status

Definition at line 1052 of file ezr32wg_dma.h.

#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 1056 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH0SWREQ   (0x1UL << 0)

Channel 0 Software Request

Definition at line 226 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH0SWREQ_DEFAULT   (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 230 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH10SWREQ   (0x1UL << 10)

Channel 10 Software Request

Definition at line 276 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH10SWREQ_DEFAULT   (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 280 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH11SWREQ   (0x1UL << 11)

Channel 11 Software Request

Definition at line 281 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH11SWREQ_DEFAULT   (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 285 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH1SWREQ   (0x1UL << 1)

Channel 1 Software Request

Definition at line 231 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH1SWREQ_DEFAULT   (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 235 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH2SWREQ   (0x1UL << 2)

Channel 2 Software Request

Definition at line 236 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH2SWREQ_DEFAULT   (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 240 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH3SWREQ   (0x1UL << 3)

Channel 3 Software Request

Definition at line 241 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH3SWREQ_DEFAULT   (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 245 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH4SWREQ   (0x1UL << 4)

Channel 4 Software Request

Definition at line 246 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH4SWREQ_DEFAULT   (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 250 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH5SWREQ   (0x1UL << 5)

Channel 5 Software Request

Definition at line 251 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH5SWREQ_DEFAULT   (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 255 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH6SWREQ   (0x1UL << 6)

Channel 6 Software Request

Definition at line 256 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH6SWREQ_DEFAULT   (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 260 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH7SWREQ   (0x1UL << 7)

Channel 7 Software Request

Definition at line 261 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH7SWREQ_DEFAULT   (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 265 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH8SWREQ   (0x1UL << 8)

Channel 8 Software Request

Definition at line 266 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH8SWREQ_DEFAULT   (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 270 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH9SWREQ   (0x1UL << 9)

Channel 9 Software Request

Definition at line 271 of file ezr32wg_dma.h.

#define DMA_CHSWREQ_CH9SWREQ_DEFAULT   (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 275 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH08USEBURSTC   (0x1UL << 8)

Channel 8 Useburst Clear

Definition at line 398 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 402 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC   (0x1UL << 0)

Channel 0 Useburst Clear

Definition at line 358 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 362 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH10USEBURSTC   (0x1UL << 10)

Channel 10 Useburst Clear

Definition at line 408 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 412 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH11USEBURSTC   (0x1UL << 11)

Channel 11 Useburst Clear

Definition at line 413 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 417 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC   (0x1UL << 1)

Channel 1 Useburst Clear

Definition at line 363 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 367 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC   (0x1UL << 2)

Channel 2 Useburst Clear

Definition at line 368 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 372 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC   (0x1UL << 3)

Channel 3 Useburst Clear

Definition at line 373 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 377 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH4USEBURSTC   (0x1UL << 4)

Channel 4 Useburst Clear

Definition at line 378 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 382 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH5USEBURSTC   (0x1UL << 5)

Channel 5 Useburst Clear

Definition at line 383 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 387 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH6USEBURSTC   (0x1UL << 6)

Channel 6 Useburst Clear

Definition at line 388 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 392 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH7USEBURSTC   (0x1UL << 7)

Channel 7 Useburst Clear

Definition at line 393 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 397 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH9USEBURSTC   (0x1UL << 9)

Channel 9 Useburst Clear

Definition at line 403 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 407 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS   (0x1UL << 0)

Channel 0 Useburst Set

Definition at line 290 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

Shifted mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 298 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 296 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 297 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH10USEBURSTS   (0x1UL << 10)

Channel 10 Useburst Set

Definition at line 344 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 348 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH11USEBURSTS   (0x1UL << 11)

Channel 11 Useburst Set

Definition at line 349 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 353 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS   (0x1UL << 1)

Channel 1 Useburst Set

Definition at line 299 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 303 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS   (0x1UL << 2)

Channel 2 Useburst Set

Definition at line 304 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 308 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS   (0x1UL << 3)

Channel 3 Useburst Set

Definition at line 309 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 313 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH4USEBURSTS   (0x1UL << 4)

Channel 4 Useburst Set

Definition at line 314 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 318 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH5USEBURSTS   (0x1UL << 5)

Channel 5 Useburst Set

Definition at line 319 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 323 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH6USEBURSTS   (0x1UL << 6)

Channel 6 Useburst Set

Definition at line 324 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 328 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH7USEBURSTS   (0x1UL << 7)

Channel 7 Useburst Set

Definition at line 329 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 333 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH8USEBURSTS   (0x1UL << 8)

Channel 8 Useburst Set

Definition at line 334 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 338 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH9USEBURSTS   (0x1UL << 9)

Channel 9 Useburst Set

Definition at line 339 of file ezr32wg_dma.h.

#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 343 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS   (0x1UL << 0)

Channel 0 Wait on Request Status

Definition at line 162 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 166 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH10WAITSTATUS   (0x1UL << 10)

Channel 10 Wait on Request Status

Definition at line 212 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 216 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH11WAITSTATUS   (0x1UL << 11)

Channel 11 Wait on Request Status

Definition at line 217 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 221 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS   (0x1UL << 1)

Channel 1 Wait on Request Status

Definition at line 167 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 171 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS   (0x1UL << 2)

Channel 2 Wait on Request Status

Definition at line 172 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 176 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS   (0x1UL << 3)

Channel 3 Wait on Request Status

Definition at line 177 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 181 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH4WAITSTATUS   (0x1UL << 4)

Channel 4 Wait on Request Status

Definition at line 182 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 186 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH5WAITSTATUS   (0x1UL << 5)

Channel 5 Wait on Request Status

Definition at line 187 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 191 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH6WAITSTATUS   (0x1UL << 6)

Channel 6 Wait on Request Status

Definition at line 192 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 196 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH7WAITSTATUS   (0x1UL << 7)

Channel 7 Wait on Request Status

Definition at line 197 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 201 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH8WAITSTATUS   (0x1UL << 8)

Channel 8 Wait on Request Status

Definition at line 202 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 206 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH9WAITSTATUS   (0x1UL << 9)

Channel 9 Wait on Request Status

Definition at line 207 of file ezr32wg_dma.h.

#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 211 of file ezr32wg_dma.h.

#define DMA_CONFIG_CHPROT   (0x1UL << 5)

Channel Protection Control

Definition at line 137 of file ezr32wg_dma.h.

#define DMA_CONFIG_CHPROT_DEFAULT   (_DMA_CONFIG_CHPROT_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 141 of file ezr32wg_dma.h.

#define DMA_CONFIG_EN   (0x1UL << 0)

Enable DMA

Definition at line 132 of file ezr32wg_dma.h.

Referenced by DMA_Init().

#define DMA_CONFIG_EN_DEFAULT   (_DMA_CONFIG_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 136 of file ezr32wg_dma.h.

#define DMA_CTRL_DESCRECT   (0x1UL << 0)

Descriptor Specifies Rectangle

Definition at line 1347 of file ezr32wg_dma.h.

#define DMA_CTRL_DESCRECT_DEFAULT   (_DMA_CTRL_DESCRECT_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CTRL

Definition at line 1351 of file ezr32wg_dma.h.

#define DMA_CTRL_PRDU   (0x1UL << 1)

Prevent Rect Descriptor Update

Definition at line 1352 of file ezr32wg_dma.h.

#define DMA_CTRL_PRDU_DEFAULT   (_DMA_CTRL_PRDU_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CTRL

Definition at line 1356 of file ezr32wg_dma.h.

#define DMA_CTRLBASE_CTRLBASE_DEFAULT   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CTRLBASE

Definition at line 149 of file ezr32wg_dma.h.

#define DMA_ERRORC_ERRORC   (0x1UL << 0)

Bus Error Clear

Definition at line 934 of file ezr32wg_dma.h.

Referenced by DMA_Reset().

#define DMA_ERRORC_ERRORC_DEFAULT   (_DMA_ERRORC_ERRORC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ERRORC

Definition at line 938 of file ezr32wg_dma.h.

#define DMA_IEN_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Enable

Definition at line 1278 of file ezr32wg_dma.h.

#define DMA_IEN_CH0DONE_DEFAULT   (_DMA_IEN_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1282 of file ezr32wg_dma.h.

#define DMA_IEN_CH10DONE   (0x1UL << 10)

DMA Channel 10 Complete Interrupt Enable

Definition at line 1328 of file ezr32wg_dma.h.

#define DMA_IEN_CH10DONE_DEFAULT   (_DMA_IEN_CH10DONE_DEFAULT << 10)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1332 of file ezr32wg_dma.h.

#define DMA_IEN_CH11DONE   (0x1UL << 11)

DMA Channel 11 Complete Interrupt Enable

Definition at line 1333 of file ezr32wg_dma.h.

#define DMA_IEN_CH11DONE_DEFAULT   (_DMA_IEN_CH11DONE_DEFAULT << 11)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1337 of file ezr32wg_dma.h.

#define DMA_IEN_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Enable

Definition at line 1283 of file ezr32wg_dma.h.

#define DMA_IEN_CH1DONE_DEFAULT   (_DMA_IEN_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1287 of file ezr32wg_dma.h.

#define DMA_IEN_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Enable

Definition at line 1288 of file ezr32wg_dma.h.

#define DMA_IEN_CH2DONE_DEFAULT   (_DMA_IEN_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1292 of file ezr32wg_dma.h.

#define DMA_IEN_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Enable

Definition at line 1293 of file ezr32wg_dma.h.

#define DMA_IEN_CH3DONE_DEFAULT   (_DMA_IEN_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1297 of file ezr32wg_dma.h.

#define DMA_IEN_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Enable

Definition at line 1298 of file ezr32wg_dma.h.

#define DMA_IEN_CH4DONE_DEFAULT   (_DMA_IEN_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1302 of file ezr32wg_dma.h.

#define DMA_IEN_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Enable

Definition at line 1303 of file ezr32wg_dma.h.

#define DMA_IEN_CH5DONE_DEFAULT   (_DMA_IEN_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1307 of file ezr32wg_dma.h.

#define DMA_IEN_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Enable

Definition at line 1308 of file ezr32wg_dma.h.

#define DMA_IEN_CH6DONE_DEFAULT   (_DMA_IEN_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1312 of file ezr32wg_dma.h.

#define DMA_IEN_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Enable

Definition at line 1313 of file ezr32wg_dma.h.

#define DMA_IEN_CH7DONE_DEFAULT   (_DMA_IEN_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1317 of file ezr32wg_dma.h.

#define DMA_IEN_CH8DONE   (0x1UL << 8)

DMA Channel 8 Complete Interrupt Enable

Definition at line 1318 of file ezr32wg_dma.h.

#define DMA_IEN_CH8DONE_DEFAULT   (_DMA_IEN_CH8DONE_DEFAULT << 8)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1322 of file ezr32wg_dma.h.

#define DMA_IEN_CH9DONE   (0x1UL << 9)

DMA Channel 9 Complete Interrupt Enable

Definition at line 1323 of file ezr32wg_dma.h.

#define DMA_IEN_CH9DONE_DEFAULT   (_DMA_IEN_CH9DONE_DEFAULT << 9)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1327 of file ezr32wg_dma.h.

#define DMA_IEN_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Enable

Definition at line 1338 of file ezr32wg_dma.h.

Referenced by DMA_Init().

#define DMA_IEN_ERR_DEFAULT   (_DMA_IEN_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IEN

Definition at line 1342 of file ezr32wg_dma.h.

#define DMA_IF_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag

Definition at line 1071 of file ezr32wg_dma.h.

#define DMA_IF_CH0DONE_DEFAULT   (_DMA_IF_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IF

Definition at line 1075 of file ezr32wg_dma.h.

#define DMA_IF_CH10DONE   (0x1UL << 10)

DMA Channel 10 Complete Interrupt Flag

Definition at line 1121 of file ezr32wg_dma.h.

#define DMA_IF_CH10DONE_DEFAULT   (_DMA_IF_CH10DONE_DEFAULT << 10)

Shifted mode DEFAULT for DMA_IF

Definition at line 1125 of file ezr32wg_dma.h.

#define DMA_IF_CH11DONE   (0x1UL << 11)

DMA Channel 11 Complete Interrupt Flag

Definition at line 1126 of file ezr32wg_dma.h.

#define DMA_IF_CH11DONE_DEFAULT   (_DMA_IF_CH11DONE_DEFAULT << 11)

Shifted mode DEFAULT for DMA_IF

Definition at line 1130 of file ezr32wg_dma.h.

#define DMA_IF_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag

Definition at line 1076 of file ezr32wg_dma.h.

#define DMA_IF_CH1DONE_DEFAULT   (_DMA_IF_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IF

Definition at line 1080 of file ezr32wg_dma.h.

#define DMA_IF_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag

Definition at line 1081 of file ezr32wg_dma.h.

#define DMA_IF_CH2DONE_DEFAULT   (_DMA_IF_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IF

Definition at line 1085 of file ezr32wg_dma.h.

#define DMA_IF_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag

Definition at line 1086 of file ezr32wg_dma.h.

#define DMA_IF_CH3DONE_DEFAULT   (_DMA_IF_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IF

Definition at line 1090 of file ezr32wg_dma.h.

#define DMA_IF_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag

Definition at line 1091 of file ezr32wg_dma.h.

#define DMA_IF_CH4DONE_DEFAULT   (_DMA_IF_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IF

Definition at line 1095 of file ezr32wg_dma.h.

#define DMA_IF_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag

Definition at line 1096 of file ezr32wg_dma.h.

#define DMA_IF_CH5DONE_DEFAULT   (_DMA_IF_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IF

Definition at line 1100 of file ezr32wg_dma.h.

#define DMA_IF_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Flag

Definition at line 1101 of file ezr32wg_dma.h.

#define DMA_IF_CH6DONE_DEFAULT   (_DMA_IF_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IF

Definition at line 1105 of file ezr32wg_dma.h.

#define DMA_IF_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Flag

Definition at line 1106 of file ezr32wg_dma.h.

#define DMA_IF_CH7DONE_DEFAULT   (_DMA_IF_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IF

Definition at line 1110 of file ezr32wg_dma.h.

#define DMA_IF_CH8DONE   (0x1UL << 8)

DMA Channel 8 Complete Interrupt Flag

Definition at line 1111 of file ezr32wg_dma.h.

#define DMA_IF_CH8DONE_DEFAULT   (_DMA_IF_CH8DONE_DEFAULT << 8)

Shifted mode DEFAULT for DMA_IF

Definition at line 1115 of file ezr32wg_dma.h.

#define DMA_IF_CH9DONE   (0x1UL << 9)

DMA Channel 9 Complete Interrupt Flag

Definition at line 1116 of file ezr32wg_dma.h.

#define DMA_IF_CH9DONE_DEFAULT   (_DMA_IF_CH9DONE_DEFAULT << 9)

Shifted mode DEFAULT for DMA_IF

Definition at line 1120 of file ezr32wg_dma.h.

#define DMA_IF_ERR   (0x1UL << 31)

DMA Error Interrupt Flag

Definition at line 1131 of file ezr32wg_dma.h.

Referenced by DMA_IRQHandler().

#define DMA_IF_ERR_DEFAULT   (_DMA_IF_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IF

Definition at line 1135 of file ezr32wg_dma.h.

#define DMA_IFC_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Clear

Definition at line 1209 of file ezr32wg_dma.h.

#define DMA_IFC_CH0DONE_DEFAULT   (_DMA_IFC_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1213 of file ezr32wg_dma.h.

#define DMA_IFC_CH10DONE   (0x1UL << 10)

DMA Channel 10 Complete Interrupt Flag Clear

Definition at line 1259 of file ezr32wg_dma.h.

#define DMA_IFC_CH10DONE_DEFAULT   (_DMA_IFC_CH10DONE_DEFAULT << 10)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1263 of file ezr32wg_dma.h.

#define DMA_IFC_CH11DONE   (0x1UL << 11)

DMA Channel 11 Complete Interrupt Flag Clear

Definition at line 1264 of file ezr32wg_dma.h.

#define DMA_IFC_CH11DONE_DEFAULT   (_DMA_IFC_CH11DONE_DEFAULT << 11)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1268 of file ezr32wg_dma.h.

#define DMA_IFC_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Clear

Definition at line 1214 of file ezr32wg_dma.h.

#define DMA_IFC_CH1DONE_DEFAULT   (_DMA_IFC_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1218 of file ezr32wg_dma.h.

#define DMA_IFC_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Clear

Definition at line 1219 of file ezr32wg_dma.h.

#define DMA_IFC_CH2DONE_DEFAULT   (_DMA_IFC_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1223 of file ezr32wg_dma.h.

#define DMA_IFC_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Clear

Definition at line 1224 of file ezr32wg_dma.h.

#define DMA_IFC_CH3DONE_DEFAULT   (_DMA_IFC_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1228 of file ezr32wg_dma.h.

#define DMA_IFC_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag Clear

Definition at line 1229 of file ezr32wg_dma.h.

#define DMA_IFC_CH4DONE_DEFAULT   (_DMA_IFC_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1233 of file ezr32wg_dma.h.

#define DMA_IFC_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag Clear

Definition at line 1234 of file ezr32wg_dma.h.

#define DMA_IFC_CH5DONE_DEFAULT   (_DMA_IFC_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1238 of file ezr32wg_dma.h.

#define DMA_IFC_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Flag Clear

Definition at line 1239 of file ezr32wg_dma.h.

#define DMA_IFC_CH6DONE_DEFAULT   (_DMA_IFC_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1243 of file ezr32wg_dma.h.

#define DMA_IFC_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Flag Clear

Definition at line 1244 of file ezr32wg_dma.h.

#define DMA_IFC_CH7DONE_DEFAULT   (_DMA_IFC_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1248 of file ezr32wg_dma.h.

#define DMA_IFC_CH8DONE   (0x1UL << 8)

DMA Channel 8 Complete Interrupt Flag Clear

Definition at line 1249 of file ezr32wg_dma.h.

#define DMA_IFC_CH8DONE_DEFAULT   (_DMA_IFC_CH8DONE_DEFAULT << 8)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1253 of file ezr32wg_dma.h.

#define DMA_IFC_CH9DONE   (0x1UL << 9)

DMA Channel 9 Complete Interrupt Flag Clear

Definition at line 1254 of file ezr32wg_dma.h.

#define DMA_IFC_CH9DONE_DEFAULT   (_DMA_IFC_CH9DONE_DEFAULT << 9)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1258 of file ezr32wg_dma.h.

#define DMA_IFC_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Clear

Definition at line 1269 of file ezr32wg_dma.h.

#define DMA_IFC_ERR_DEFAULT   (_DMA_IFC_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFC

Definition at line 1273 of file ezr32wg_dma.h.

#define DMA_IFS_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Set

Definition at line 1140 of file ezr32wg_dma.h.

#define DMA_IFS_CH0DONE_DEFAULT   (_DMA_IFS_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1144 of file ezr32wg_dma.h.

#define DMA_IFS_CH10DONE   (0x1UL << 10)

DMA Channel 10 Complete Interrupt Flag Set

Definition at line 1190 of file ezr32wg_dma.h.

#define DMA_IFS_CH10DONE_DEFAULT   (_DMA_IFS_CH10DONE_DEFAULT << 10)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1194 of file ezr32wg_dma.h.

#define DMA_IFS_CH11DONE   (0x1UL << 11)

DMA Channel 11 Complete Interrupt Flag Set

Definition at line 1195 of file ezr32wg_dma.h.

#define DMA_IFS_CH11DONE_DEFAULT   (_DMA_IFS_CH11DONE_DEFAULT << 11)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1199 of file ezr32wg_dma.h.

#define DMA_IFS_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Set

Definition at line 1145 of file ezr32wg_dma.h.

#define DMA_IFS_CH1DONE_DEFAULT   (_DMA_IFS_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1149 of file ezr32wg_dma.h.

#define DMA_IFS_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Set

Definition at line 1150 of file ezr32wg_dma.h.

#define DMA_IFS_CH2DONE_DEFAULT   (_DMA_IFS_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1154 of file ezr32wg_dma.h.

#define DMA_IFS_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Set

Definition at line 1155 of file ezr32wg_dma.h.

#define DMA_IFS_CH3DONE_DEFAULT   (_DMA_IFS_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1159 of file ezr32wg_dma.h.

#define DMA_IFS_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag Set

Definition at line 1160 of file ezr32wg_dma.h.

#define DMA_IFS_CH4DONE_DEFAULT   (_DMA_IFS_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1164 of file ezr32wg_dma.h.

#define DMA_IFS_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag Set

Definition at line 1165 of file ezr32wg_dma.h.

#define DMA_IFS_CH5DONE_DEFAULT   (_DMA_IFS_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1169 of file ezr32wg_dma.h.

#define DMA_IFS_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Flag Set

Definition at line 1170 of file ezr32wg_dma.h.

#define DMA_IFS_CH6DONE_DEFAULT   (_DMA_IFS_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1174 of file ezr32wg_dma.h.

#define DMA_IFS_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Flag Set

Definition at line 1175 of file ezr32wg_dma.h.

#define DMA_IFS_CH7DONE_DEFAULT   (_DMA_IFS_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1179 of file ezr32wg_dma.h.

#define DMA_IFS_CH8DONE   (0x1UL << 8)

DMA Channel 8 Complete Interrupt Flag Set

Definition at line 1180 of file ezr32wg_dma.h.

#define DMA_IFS_CH8DONE_DEFAULT   (_DMA_IFS_CH8DONE_DEFAULT << 8)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1184 of file ezr32wg_dma.h.

#define DMA_IFS_CH9DONE   (0x1UL << 9)

DMA Channel 9 Complete Interrupt Flag Set

Definition at line 1185 of file ezr32wg_dma.h.

#define DMA_IFS_CH9DONE_DEFAULT   (_DMA_IFS_CH9DONE_DEFAULT << 9)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1189 of file ezr32wg_dma.h.

#define DMA_IFS_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Set

Definition at line 1200 of file ezr32wg_dma.h.

#define DMA_IFS_ERR_DEFAULT   (_DMA_IFS_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFS

Definition at line 1204 of file ezr32wg_dma.h.

#define DMA_LOOP0_EN   (0x1UL << 16)

DMA Channel 0 Loop Enable

Definition at line 1429 of file ezr32wg_dma.h.

#define DMA_LOOP0_EN_DEFAULT   (_DMA_LOOP0_EN_DEFAULT << 16)

Shifted mode DEFAULT for DMA_LOOP0

Definition at line 1433 of file ezr32wg_dma.h.

#define DMA_LOOP0_WIDTH_DEFAULT   (_DMA_LOOP0_WIDTH_DEFAULT << 0)

Shifted mode DEFAULT for DMA_LOOP0

Definition at line 1428 of file ezr32wg_dma.h.

#define DMA_LOOP1_EN   (0x1UL << 16)

DMA Channel 1 Loop Enable

Definition at line 1442 of file ezr32wg_dma.h.

#define DMA_LOOP1_EN_DEFAULT   (_DMA_LOOP1_EN_DEFAULT << 16)

Shifted mode DEFAULT for DMA_LOOP1

Definition at line 1446 of file ezr32wg_dma.h.

#define DMA_LOOP1_WIDTH_DEFAULT   (_DMA_LOOP1_WIDTH_DEFAULT << 0)

Shifted mode DEFAULT for DMA_LOOP1

Definition at line 1441 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH0   (0x1UL << 0)

Retain Descriptor State

Definition at line 1361 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH0_DEFAULT   (_DMA_RDS_RDSCH0_DEFAULT << 0)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1365 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH1   (0x1UL << 1)

Retain Descriptor State

Definition at line 1366 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH10   (0x1UL << 10)

Retain Descriptor State

Definition at line 1411 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH10_DEFAULT   (_DMA_RDS_RDSCH10_DEFAULT << 10)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1415 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH11   (0x1UL << 11)

Retain Descriptor State

Definition at line 1416 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH11_DEFAULT   (_DMA_RDS_RDSCH11_DEFAULT << 11)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1420 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH1_DEFAULT   (_DMA_RDS_RDSCH1_DEFAULT << 1)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1370 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH2   (0x1UL << 2)

Retain Descriptor State

Definition at line 1371 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH2_DEFAULT   (_DMA_RDS_RDSCH2_DEFAULT << 2)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1375 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH3   (0x1UL << 3)

Retain Descriptor State

Definition at line 1376 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH3_DEFAULT   (_DMA_RDS_RDSCH3_DEFAULT << 3)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1380 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH4   (0x1UL << 4)

Retain Descriptor State

Definition at line 1381 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH4_DEFAULT   (_DMA_RDS_RDSCH4_DEFAULT << 4)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1385 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH5   (0x1UL << 5)

Retain Descriptor State

Definition at line 1386 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH5_DEFAULT   (_DMA_RDS_RDSCH5_DEFAULT << 5)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1390 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH6   (0x1UL << 6)

Retain Descriptor State

Definition at line 1391 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH6_DEFAULT   (_DMA_RDS_RDSCH6_DEFAULT << 6)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1395 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH7   (0x1UL << 7)

Retain Descriptor State

Definition at line 1396 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH7_DEFAULT   (_DMA_RDS_RDSCH7_DEFAULT << 7)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1400 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH8   (0x1UL << 8)

Retain Descriptor State

Definition at line 1401 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH8_DEFAULT   (_DMA_RDS_RDSCH8_DEFAULT << 8)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1405 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH9   (0x1UL << 9)

Retain Descriptor State

Definition at line 1406 of file ezr32wg_dma.h.

#define DMA_RDS_RDSCH9_DEFAULT   (_DMA_RDS_RDSCH9_DEFAULT << 9)

Shifted mode DEFAULT for DMA_RDS

Definition at line 1410 of file ezr32wg_dma.h.

#define DMA_RECT0_DSTSTRIDE_DEFAULT   (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21)

Shifted mode DEFAULT for DMA_RECT0

Definition at line 1462 of file ezr32wg_dma.h.

#define DMA_RECT0_HEIGHT_DEFAULT   (_DMA_RECT0_HEIGHT_DEFAULT << 0)

Shifted mode DEFAULT for DMA_RECT0

Definition at line 1454 of file ezr32wg_dma.h.

#define DMA_RECT0_SRCSTRIDE_DEFAULT   (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10)

Shifted mode DEFAULT for DMA_RECT0

Definition at line 1458 of file ezr32wg_dma.h.

#define DMA_STATUS_CHNUM_DEFAULT   (_DMA_STATUS_CHNUM_DEFAULT << 16)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 127 of file ezr32wg_dma.h.

#define DMA_STATUS_EN   (0x1UL << 0)

DMA Enable Status

Definition at line 93 of file ezr32wg_dma.h.

#define DMA_STATUS_EN_DEFAULT   (_DMA_STATUS_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 97 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_DEFAULT   (_DMA_STATUS_STATE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 112 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_DONE   (_DMA_STATUS_STATE_DONE << 4)

Shifted mode DONE for DMA_STATUS

Definition at line 122 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_IDLE   (_DMA_STATUS_STATE_IDLE << 4)

Shifted mode IDLE for DMA_STATUS

Definition at line 113 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_PERSCATTRANS   (_DMA_STATUS_STATE_PERSCATTRANS << 4)

Shifted mode PERSCATTRANS for DMA_STATUS

Definition at line 123 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_RDCHCTRLDATA   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)

Shifted mode RDCHCTRLDATA for DMA_STATUS

Definition at line 114 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_RDDSTENDPTR   (_DMA_STATUS_STATE_RDDSTENDPTR << 4)

Shifted mode RDDSTENDPTR for DMA_STATUS

Definition at line 116 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_RDSRCDATA   (_DMA_STATUS_STATE_RDSRCDATA << 4)

Shifted mode RDSRCDATA for DMA_STATUS

Definition at line 117 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_RDSRCENDPTR   (_DMA_STATUS_STATE_RDSRCENDPTR << 4)

Shifted mode RDSRCENDPTR for DMA_STATUS

Definition at line 115 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_STALLED   (_DMA_STATUS_STATE_STALLED << 4)

Shifted mode STALLED for DMA_STATUS

Definition at line 121 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_WAITREQCLR   (_DMA_STATUS_STATE_WAITREQCLR << 4)

Shifted mode WAITREQCLR for DMA_STATUS

Definition at line 119 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_WRCHCTRLDATA   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)

Shifted mode WRCHCTRLDATA for DMA_STATUS

Definition at line 120 of file ezr32wg_dma.h.

#define DMA_STATUS_STATE_WRDSTDATA   (_DMA_STATUS_STATE_WRDSTDATA << 4)

Shifted mode WRDSTDATA for DMA_STATUS

Definition at line 118 of file ezr32wg_dma.h.