36 #if defined( CMU_PRESENT )
59 #define CMU_NOSEL_REG 0
60 #define CMU_HFCLKSEL_REG 1
61 #define CMU_LFACLKSEL_REG 2
62 #define CMU_LFBCLKSEL_REG 3
63 #define CMU_LFCCLKSEL_REG 4
64 #define CMU_LFECLKSEL_REG 5
65 #define CMU_DBGCLKSEL_REG 6
66 #define CMU_USBCCLKSEL_REG 7
68 #define CMU_SEL_REG_POS 0
69 #define CMU_SEL_REG_MASK 0xf
72 #define CMU_NODIV_REG 0
73 #define CMU_NOPRESC_REG 0
74 #define CMU_HFPRESC_REG 1
75 #define CMU_HFCLKDIV_REG 1
76 #define CMU_HFEXPPRESC_REG 2
77 #define CMU_HFCLKLEPRESC_REG 3
78 #define CMU_HFPERPRESC_REG 4
79 #define CMU_HFPERCLKDIV_REG 4
80 #define CMU_HFCOREPRESC_REG 5
81 #define CMU_HFCORECLKDIV_REG 5
82 #define CMU_LFAPRESC0_REG 6
83 #define CMU_LFBPRESC0_REG 7
84 #define CMU_LFEPRESC0_REG 8
86 #define CMU_PRESC_REG_POS 4
87 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
88 #define CMU_PRESC_REG_MASK 0xf
89 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
92 #define CMU_NO_EN_REG 0
93 #define CMU_CTRL_EN_REG 1
94 #define CMU_HFPERCLKDIV_EN_REG 1
95 #define CMU_HFPERCLKEN0_EN_REG 2
96 #define CMU_HFCORECLKEN0_EN_REG 3
97 #define CMU_HFBUSCLKEN0_EN_REG 5
98 #define CMU_LFACLKEN0_EN_REG 6
99 #define CMU_LFBCLKEN0_EN_REG 7
100 #define CMU_LFCCLKEN0_EN_REG 8
101 #define CMU_LFECLKEN0_EN_REG 9
102 #define CMU_PCNT_EN_REG 10
104 #define CMU_EN_REG_POS 8
105 #define CMU_EN_REG_MASK 0xf
108 #define CMU_EN_BIT_POS 12
109 #define CMU_EN_BIT_MASK 0x1f
112 #define CMU_HF_CLK_BRANCH 0
113 #define CMU_HFCORE_CLK_BRANCH 1
114 #define CMU_HFPER_CLK_BRANCH 2
115 #define CMU_HFBUS_CLK_BRANCH 4
116 #define CMU_HFEXP_CLK_BRANCH 5
117 #define CMU_DBG_CLK_BRANCH 6
118 #define CMU_AUX_CLK_BRANCH 7
119 #define CMU_RTC_CLK_BRANCH 8
120 #define CMU_RTCC_CLK_BRANCH 9
121 #define CMU_LETIMER0_CLK_BRANCH 10
122 #define CMU_LEUART0_CLK_BRANCH 11
123 #define CMU_LEUART1_CLK_BRANCH 12
124 #define CMU_LFA_CLK_BRANCH 13
125 #define CMU_LFB_CLK_BRANCH 14
126 #define CMU_LFC_CLK_BRANCH 15
127 #define CMU_LFE_CLK_BRANCH 16
128 #define CMU_USBC_CLK_BRANCH 17
129 #define CMU_USBLE_CLK_BRANCH 18
130 #define CMU_LCDPRE_CLK_BRANCH 19
131 #define CMU_LCD_CLK_BRANCH 20
132 #define CMU_LESENSE_CLK_BRANCH 21
133 #define CMU_CSEN_LF_CLK_BRANCH 22
135 #define CMU_CLK_BRANCH_POS 17
136 #define CMU_CLK_BRANCH_MASK 0x1f
138 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
140 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
149 #define cmuClkDiv_1 1
150 #define cmuClkDiv_2 2
151 #define cmuClkDiv_4 4
152 #define cmuClkDiv_8 8
153 #define cmuClkDiv_16 16
154 #define cmuClkDiv_32 32
155 #define cmuClkDiv_64 64
156 #define cmuClkDiv_128 128
157 #define cmuClkDiv_256 256
158 #define cmuClkDiv_512 512
159 #define cmuClkDiv_1024 1024
160 #define cmuClkDiv_2048 2048
161 #define cmuClkDiv_4096 4096
162 #define cmuClkDiv_8192 8192
163 #define cmuClkDiv_16384 16384
164 #define cmuClkDiv_32768 32768
167 typedef uint32_t CMU_ClkDiv_TypeDef;
169 #if defined( _SILICON_LABS_32B_SERIES_1 )
174 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
178 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,
179 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,
180 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
181 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
182 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
183 #if defined( CMU_HFRCOCTRL_BAND_28MHZ )
184 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ,
186 } CMU_HFRCOBand_TypeDef;
189 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
193 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ,
194 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ,
195 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,
196 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,
197 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,
198 #if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
199 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ,
201 } CMU_AUXHFRCOBand_TypeDef;
204 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
209 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
211 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
212 } CMU_USHFRCOBand_TypeDef;
215 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
229 cmuHFRCOFreq_UserDefined = 0,
231 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
232 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
235 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
249 cmuAUXHFRCOFreq_UserDefined = 0,
251 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
252 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
264 #if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
265 || defined( _CMU_HFPRESC_MASK )
267 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
268 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
269 | (0 << CMU_EN_BIT_POS)
270 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
273 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
274 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
275 | (0 << CMU_EN_BIT_POS)
276 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
281 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
282 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
283 | (0 << CMU_EN_BIT_POS)
284 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
288 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
289 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
290 | (0 << CMU_EN_BIT_POS)
291 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
293 #if defined( _CMU_HFEXPPRESC_MASK )
300 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
301 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
302 | (0 << CMU_EN_BIT_POS)
303 | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
313 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
314 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
315 | (0 << CMU_EN_BIT_POS)
316 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
321 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
322 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
324 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
330 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
331 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
333 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
339 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
340 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
342 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
348 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
349 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
351 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
357 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
358 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
360 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
366 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
367 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
369 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
374 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
375 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
377 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
379 #if defined( CMU_HFBUSCLKEN0_PRS )
382 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
383 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
385 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
396 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
397 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
399 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
402 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
403 | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
404 | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
405 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
408 #if defined( CMU_HFPERCLKEN0_USART0 )
411 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
412 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
414 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
417 #
if defined( CMU_HFPERCLKEN0_USARTRF0 )
419 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
420 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
421 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
422 | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
423 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
426 #
if defined( CMU_HFPERCLKEN0_USARTRF1 )
428 cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
429 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
430 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
431 | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
432 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
438 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
439 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
441 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
447 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
448 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
450 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
453 #
if defined( CMU_HFPERCLKEN0_USART3 )
455 cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
456 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
457 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
458 | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
459 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
462 #
if defined( CMU_HFPERCLKEN0_USART4 )
464 cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
465 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
466 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
467 | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
468 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
471 #
if defined( CMU_HFPERCLKEN0_USART5 )
473 cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
474 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
475 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
476 | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
477 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
481 #
if defined( CMU_HFPERCLKEN0_UART0 )
483 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
484 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
485 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
486 | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
487 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
490 #
if defined( CMU_HFPERCLKEN0_UART1 )
492 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
493 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
494 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
495 | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
496 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
502 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
503 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
505 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
511 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
512 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
514 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
517 #
if defined( CMU_HFPERCLKEN0_TIMER2 )
519 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
520 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
521 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
522 | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
523 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
526 #
if defined( CMU_HFPERCLKEN0_TIMER3 )
528 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
529 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
530 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
531 | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
532 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
538 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
539 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
541 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
544 #
if defined( CMU_HFPERCLKEN0_WTIMER1 )
546 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
547 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
548 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
549 | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
550 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
556 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
557 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
559 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
565 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
566 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
568 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
574 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
575 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
577 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
580 #
if defined( CMU_HFPERCLKEN0_PRS )
583 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
584 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
585 | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
586 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
589 #
if defined( CMU_HFPERCLKEN0_DAC0 )
591 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
592 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
593 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
594 | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
595 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
601 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
602 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
604 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
610 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
611 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
613 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
616 #
if defined( CMU_HFPERCLKEN0_GPIO )
619 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
620 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
621 | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
622 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
625 #
if defined( CMU_HFPERCLKEN0_VCMP )
627 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
628 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
629 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
630 | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
631 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
637 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
638 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
640 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
646 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
647 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
649 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
655 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
656 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
658 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
661 #
if defined( CMU_HFPERCLKEN0_I2C2 )
663 cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
664 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
665 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
666 | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
667 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
673 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
674 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
676 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
682 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
683 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
685 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
694 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
695 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
696 | (0 << CMU_EN_BIT_POS)
697 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
699 #if defined( CMU_HFCORECLKEN0_AES )
701 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
702 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
703 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
704 | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
705 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
708 #
if defined( CMU_HFCORECLKEN0_DMA )
710 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
711 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
712 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
713 | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
714 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
717 #
if defined( CMU_HFCORECLKEN0_LE )
720 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
721 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
722 | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
723 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
726 #
if defined( CMU_HFCORECLKEN0_EBI )
728 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
729 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
730 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
731 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
732 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
735 #
if defined( CMU_HFCORECLKEN0_USBC )
737 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
738 | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
739 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
740 | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
741 | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
745 #
if defined( CMU_HFCORECLKEN0_USB )
747 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
748 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
749 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
750 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
751 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
760 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
761 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
762 | (0 << CMU_EN_BIT_POS)
763 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
765 #if defined( CMU_LFACLKEN0_RTC )
767 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
768 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
769 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
770 | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
771 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
777 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
778 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
780 | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
783 #
if defined( CMU_LFACLKEN0_LCD )
785 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
786 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
787 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
788 | (0 << CMU_EN_BIT_POS)
789 | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
793 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
794 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
795 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
796 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
797 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
800 #if defined( CMU_PCNTCTRL_PCNT0CLKEN )
803 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
804 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
806 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
809 #
if defined( CMU_PCNTCTRL_PCNT1CLKEN )
811 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
812 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
813 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
814 | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
815 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
818 #
if defined( CMU_PCNTCTRL_PCNT2CLKEN )
820 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
821 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
822 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
823 | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
824 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
829 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
830 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
832 | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
841 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
842 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
843 | (0 << CMU_EN_BIT_POS)
844 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
846 #if defined( CMU_LFBCLKEN0_LEUART0 )
849 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
850 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
852 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
858 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
859 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
861 | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
864 #
if defined( CMU_LFBCLKEN0_LEUART1 )
866 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
867 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
868 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
869 | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
870 | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
876 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
877 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
879 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
882 #
if defined( _CMU_LFCCLKEN0_MASK )
888 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
889 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
890 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
891 | (0 << CMU_EN_BIT_POS)
892 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
894 #
if defined( CMU_LFCCLKEN0_USBLE )
896 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
897 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
898 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
899 | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
900 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
911 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
912 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
913 | (0 << CMU_EN_BIT_POS)
914 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
919 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
920 | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
922 | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
930 #define cmuClock_CORELE cmuClock_HFLE
942 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
945 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
948 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
974 #if defined( CMU_STATUS_USHFRCOENS )
977 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
978 cmuSelect_USHFRCODIV2,
980 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
983 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
988 #if defined( CMU_HFCORECLKEN0_LE )
991 #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
995 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
999 cmuHFXOTuningMode_Auto = 0,
1006 #if defined( _CMU_CTRL_LFXOBOOST_MASK )
1010 cmuLfxoBoost70 = 0x0,
1011 cmuLfxoBoost100 = 0x2,
1012 #if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
1013 cmuLfxoBoost70Reduced = 0x1,
1014 cmuLfxoBoost100Reduced = 0x3,
1016 } CMU_LFXOBoost_TypeDef;
1027 #if defined( _CMU_LFXOCTRL_MASK )
1031 CMU_LFXOBoost_TypeDef boost;
1037 #if defined( _CMU_LFXOCTRL_MASK )
1040 #define CMU_LFXOINIT_DEFAULT \
1042 _CMU_LFXOCTRL_TUNING_DEFAULT, \
1043 _CMU_LFXOCTRL_GAIN_DEFAULT, \
1044 _CMU_LFXOCTRL_TIMEOUT_DEFAULT, \
1045 cmuOscMode_Crystal, \
1047 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
1051 _CMU_LFXOCTRL_TIMEOUT_2CYCLES, \
1052 cmuOscMode_External, \
1056 #define CMU_LFXOINIT_DEFAULT \
1059 _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
1060 cmuOscMode_Crystal, \
1062 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
1065 _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
1066 cmuOscMode_External, \
1074 #if defined( _CMU_HFXOCTRL_MASK )
1092 bool glitchDetector;
1097 #if defined( _CMU_HFXOCTRL_MASK )
1102 #if defined( _EFR_DEVICE )
1103 #define CMU_HFXOINIT_DEFAULT \
1109 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
1110 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
1111 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1115 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1118 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
1119 cmuOscMode_Crystal, \
1122 #define CMU_HFXOINIT_DEFAULT \
1128 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
1129 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
1130 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1134 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1137 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
1138 cmuOscMode_Crystal, \
1141 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
1149 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1153 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1155 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, \
1156 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, \
1157 cmuOscMode_External, \
1163 #define CMU_HFXOINIT_DEFAULT \
1165 _CMU_CTRL_HFXOBOOST_DEFAULT, \
1166 _CMU_CTRL_HFXOTIMEOUT_DEFAULT, \
1168 cmuOscMode_Crystal, \
1170 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
1173 _CMU_CTRL_HFXOTIMEOUT_8CYCLES, \
1175 cmuOscMode_External, \
1184 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
1188 #elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
1195 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
1206 #if defined( _SILICON_LABS_32B_SERIES_1 )
1215 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
1219 #elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
1224 uint32_t CMU_HFRCOStartupDelayGet(
void);
1225 void CMU_HFRCOStartupDelaySet(uint32_t delay);
1227 #if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
1230 bool enEM0EM1StartSel);
1244 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
1254 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
1255 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(
void);
1256 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
1260 #if defined( CMU_CALCTRL_CONT )
1288 #if defined( CMU_CMD_CALSTOP )
1316 EFM_ASSERT((div > 0U) && (div <= 32768U));
1319 log2 = (31U - __CLZ(div));
1403 return CMU->IF & ien;
1455 #if defined( _SILICON_LABS_32B_SERIES_1 )
1472 EFM_ASSERT(presc < 32768U);
1475 log2 = (31U - __CLZ(presc + 1));
1495 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
1529 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
uint8_t xoCoreBiasTrimSteadyState
#define _CMU_LFBCLKEN0_LEUART0_SHIFT
#define _CMU_HFBUSCLKEN0_LE_SHIFT
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
__STATIC_INLINE void CMU_Lock(void)
Lock the CMU in order to protect some of its registers against unintended modification.
#define CMU_HFPERCLKEN0_ADC0
uint8_t regIshSteadyState
Emlib peripheral API "assert" implementation.
#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
#define CMU_HFPERCLKEN0_TRNG0
#define _CMU_LFBCLKEN0_CSEN_SHIFT
RAM and peripheral bit-field set and clear API.
__STATIC_INLINE uint32_t CMU_IntGet(void)
Get pending CMU interrupts.
#define CMU_LFACLKEN0_LESENSE
#define _CMU_HFPERCLKEN0_TIMER0_SHIFT
#define CMU_HFBUSCLKEN0_CRYPTO
#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT
#define _CMU_HFPERCLKEN0_USART0_SHIFT
#define CMU_HFBUSCLKEN0_CRYPTO0
__STATIC_INLINE void CMU_IntSet(uint32_t flags)
Set one or more pending CMU interrupts.
__STATIC_INLINE void CMU_CalibrateCont(bool enable)
Configures continuous calibration mode.
#define CMU_HFBUSCLKEN0_LDMA
#define CMU_LFECLKEN0_RTCC
void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc)
Set clock prescaler.
#define CMU_HFPERCLKEN0_I2C1
#define CMU_HFPERCLKEN0_WTIMER0
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define _CMU_HFPERCLKEN0_USART2_SHIFT
uint8_t thresholdPeakDetect
#define _CMU_LFBCLKEN0_SYSTICK_SHIFT
#define _CMU_HFPRESC_MASK
__STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
Get enabled and pending CMU interrupt flags.
__STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
Set HFRCO calibration for the selected target frequency.
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
#define _CMU_HFPERCLKEN0_TRNG0_SHIFT
#define CMU_HFPERCLKEN0_VDAC0
#define _CMU_HFPERCLKEN0_VDAC0_SHIFT
void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
Set HFXO control registers.
#define CMU_HFPERCLKEN0_USART1
#define _CMU_HFPERCLKEN0_ACMP0_SHIFT
bool autoStartSelOnRacWakeup
uint32_t CMU_ClkDiv_TypeDef
#define CMU_LFBCLKEN0_SYSTICK
#define _CMU_HFBUSCLKEN0_MASK
#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT
#define CMU_CMD_HFXOSHUNTOPTSTART
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
#define _CMU_LFECLKEN0_RTCC_SHIFT
#define CMU_HFPERCLKEN0_TIMER1
CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void)
Get current HFRCO frequency.
#define _CMU_HFPERCLKEN0_ACMP1_SHIFT
#define CMU_LOCK_LOCKKEY_UNLOCK
#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT
__STATIC_INLINE void CMU_CalibrateStart(void)
Starts calibration.
CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void)
Get current AUXHFRCO frequency.
#define _CMU_HFPERCLKEN0_IDAC0_SHIFT
#define CMU_HFPERCLKEN0_IDAC0
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
#define CMU_HFPERCLKEN0_ACMP0
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)
Configure clock calibration.
__STATIC_INLINE void CMU_IntDisable(uint32_t flags)
Disable one or more CMU interrupts.
#define CMU_HFPERCLKEN0_I2C0
#define _CMU_HFPERCLKEN0_I2C1_SHIFT
#define CMU_LOCK_LOCKKEY_LOCK
#define CMU_HFPERCLKEN0_ACMP1
#define CMU_HFPERCLKEN0_CRYOTIMER
uint8_t timeoutPeakDetect
#define CMU_CMD_HFXOPEAKDETSTART
#define CMU_HFPERCLKEN0_TIMER0
__STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
Get current HFRCO frequency.
uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
Get clock prescaler.
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
uint32_t CMU_ClkPresc_TypeDef
uint8_t xoCoreBiasTrimStartup
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
#define CMU_HFBUSCLKEN0_GPIO
#define _CMU_CTRL_HFPERCLKEN_SHIFT
__STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
Convert prescaler dividend to logarithmic value. Only works for even numbers equal to 2^n...
#define _CMU_HFPERCLKEN0_USART1_SHIFT
#define CMU_HFBUSCLKEN0_GPCRC
#define _CMU_LFECLKEN0_MASK
#define _CMU_LFACLKEN0_LETIMER0_SHIFT
uint8_t timeoutShuntOptimization
void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)
Set HFRCO calibration for the selected target frequency.
#define _CMU_HFPERCLKEN0_ADC0_SHIFT
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
#define _CMU_HFBUSCLKEN0_LDMA_SHIFT
#define _CMU_HFPERCLKEN0_WTIMER0_SHIFT
#define CMU_LFBCLKEN0_CSEN
__STATIC_INLINE void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
Set AUXHFRCO calibration for the selected target frequency.
#define _CMU_HFPERCLKEN0_I2C0_SHIFT
#define CMU_HFBUSCLKEN0_CRYPTO1
CMU_HFXOTuningMode_TypeDef
#define _CMU_LFACLKEN0_LESENSE_SHIFT
#define CMU_HFPERCLKEN0_CSEN
#define CMU_HFPERCLKEN0_USART2
bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait)
Start and optionally wait for oscillator tuning optimization.
void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
Set AUXHFRCO calibration for the selected target frequency.
#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT
__STATIC_INLINE void CMU_IntClear(uint32_t flags)
Clear one or more pending CMU interrupts.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _CMU_HFBUSCLKEN0_GPIO_SHIFT
__STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
Get current AUXHFRCO frequency.
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)
Set LFXO control registers.
__STATIC_INLINE void CMU_IntEnable(uint32_t flags)
Enable one or more CMU interrupts.
#define _CMU_HFPERCLKEN0_TIMER1_SHIFT
#define _CMU_HFPERCLKEN0_CSEN_SHIFT
#define CMU_LFACLKEN0_LETIMER0
uint16_t ctuneSteadyState
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
#define _CMU_CALCTRL_CONT_SHIFT
bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode)
Wait for oscillator tuning optimization.
__STATIC_INLINE void CMU_Unlock(void)
Unlock the CMU so that writing to locked registers again is possible.
void CMU_HFXOAutostartEnable(uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel)
Enable or disable HFXO autostart.
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
#define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT
__STATIC_INLINE void CMU_CalibrateStop(void)
Stop the calibration counters.
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.
#define _CMU_HFBUSCLKEN0_PRS_SHIFT