em_core.h

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/***************************************************************************/
#ifndef EM_CORE_H
#define EM_CORE_H

#include "em_device.h"
#include "em_common.h"

#include <stdbool.h>

/***************************************************************************/
/***************************************************************************/
/*******************************************************************************
 *******************************   DEFINES   ***********************************
 ******************************************************************************/

#define CORE_ATOMIC_METHOD_PRIMASK  0

#define CORE_ATOMIC_METHOD_BASEPRI  1

#define CORE_NVIC_REG_WORDS   ((EXT_IRQ_COUNT + 31) / 32)

#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES   (EXT_IRQ_COUNT + 16)

// Compile time sanity check.
#if (CORE_NVIC_REG_WORDS > 3)
#error "em_core: Unexpected NVIC external interrupt count."
#endif

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 ************************   MACRO API   ***************************************
 ******************************************************************************/

//
//  CRITICAL section macro API.
//

#define CORE_DECLARE_IRQ_STATE        CORE_irqState_t irqState

#define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq()

#define CORE_CRITICAL_IRQ_ENABLE()  CORE_CriticalEnableIrq()

#define CORE_CRITICAL_SECTION(yourcode) \
{                                       \
  CORE_DECLARE_IRQ_STATE;               \
  CORE_ENTER_CRITICAL();                \
  {                                     \
    yourcode                            \
  }                                     \
  CORE_EXIT_CRITICAL();                 \
}

#define CORE_ENTER_CRITICAL()   irqState = CORE_EnterCritical()

#define CORE_EXIT_CRITICAL()    CORE_ExitCritical(irqState)

#define CORE_YIELD_CRITICAL()   CORE_YieldCritical(void)

//
//  ATOMIC section macro API.
//

#define CORE_ATOMIC_IRQ_DISABLE()   CORE_AtomicDisableIrq()

#define CORE_ATOMIC_IRQ_ENABLE()    CORE_AtomicEnableIrq()

#define CORE_ATOMIC_SECTION(yourcode) \
{                                     \
  CORE_DECLARE_IRQ_STATE;             \
  CORE_ENTER_ATOMIC();                \
  {                                   \
    yourcode                          \
  }                                   \
  CORE_EXIT_ATOMIC();                 \
}

#define CORE_ENTER_ATOMIC()   irqState = CORE_EnterAtomic()

#define CORE_EXIT_ATOMIC()    CORE_ExitAtomic(irqState)

#define CORE_YIELD_ATOMIC()   CORE_YieldAtomic(void)

//
//  NVIC mask section macro API.
//

#define CORE_DECLARE_NVIC_STATE       CORE_nvicMask_t nvicState

#define CORE_DECLARE_NVIC_MASK(x)     CORE_nvicMask_t x

#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = {{0}}

#define CORE_NVIC_DISABLE(mask)   CORE_NvicDisableMask(mask)

#define CORE_NVIC_ENABLE(mask)    CORE_NvicEnableMask(mask)

#define CORE_NVIC_SECTION(mask, yourcode)   \
{                                           \
  CORE_DECLARE_NVIC_STATE;                  \
  CORE_ENTER_NVIC(mask);                    \
  {                                         \
    yourcode                                \
  }                                         \
  CORE_EXIT_NVIC();                         \
}

#define CORE_ENTER_NVIC(disable)  CORE_EnterNvicMask(&nvicState,disable)

#define CORE_EXIT_NVIC()          CORE_NvicEnableMask(&nvicState)

#define CORE_YIELD_NVIC(enable)   CORE_YieldNvicMask(enable)

//
//  Miscellaneous macros.
//

#define CORE_IRQ_DISABLED()       CORE_IrqIsDisabled()

#define CORE_IN_IRQ_CONTEXT()     CORE_InIrqContext()

/*******************************************************************************
 *************************   TYPEDEFS   ****************************************
 ******************************************************************************/

typedef uint32_t CORE_irqState_t;

typedef struct {
  uint32_t a[CORE_NVIC_REG_WORDS];    
} CORE_nvicMask_t;

/*******************************************************************************
 *****************************   PROTOTYPES   **********************************
 ******************************************************************************/

void CORE_CriticalDisableIrq(void);
void CORE_CriticalEnableIrq(void);
void CORE_ExitCritical(CORE_irqState_t irqState);
void CORE_YieldCritical(void);
CORE_irqState_t CORE_EnterCritical(void);

void  CORE_AtomicDisableIrq(void);
void  CORE_AtomicEnableIrq(void);
void  CORE_ExitAtomic(CORE_irqState_t irqState);
void  CORE_YieldAtomic(void);
CORE_irqState_t CORE_EnterAtomic(void);

bool  CORE_InIrqContext(void);
bool  CORE_IrqIsBlocked(IRQn_Type irqN);
bool  CORE_IrqIsDisabled(void);

void  CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask);
bool  CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask);

void  CORE_EnterNvicMask(CORE_nvicMask_t *nvicState,
                         const CORE_nvicMask_t *disable);
void  CORE_NvicDisableMask(const CORE_nvicMask_t *disable);
void  CORE_NvicEnableMask(const CORE_nvicMask_t *enable);
void  CORE_YieldNvicMask(const CORE_nvicMask_t *enable);
void  CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask);
void  CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask);
bool  CORE_NvicIRQDisabled(IRQn_Type irqN);

void *CORE_GetNvicRamTableHandler(IRQn_Type irqN);
void  CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler);
void  CORE_InitNvicVectorTable(uint32_t *sourceTable,
                               uint32_t sourceSize,
                               uint32_t *targetTable,
                               uint32_t targetSize,
                               void *defaultHandler,
                               bool overwriteActive);

#ifdef __cplusplus
}
#endif

#endif /* EM_CORE_H */